HT82V26 16-Bit CCD/CIS Analog Signal Processor Features · Operating voltage: 5V · Internal voltage reference · Low power consumption at 400mW (Typ.) · Multiplexed byte-wide output (8+8 format) · Power-down mode: Under 2mA (Typ.) · Programmable 3-wire serial interface · 16-bit 30 MSPS A/D converter · 3V/5V digital I/O compatibility · Guaranteed won¢t miss codes · 3-channel operation up to 30 MSPS · 1~6 programmable gain · 2-channel (Even-Odd) operation up to 30 MSPS · Correlated Double Sampling · 1-channel operation up to 25 MSPS · ±250mV programmable offset · 28-pin SSOP/SOP package (lead-free on request) · Input clamp circuitry Applications Flatbed document scanners Digital color copiers Film scanners Multifunction peripherals General Description The 16-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset and operating mode adjustments. The HT82V26 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of tri-linear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), and a high performance 16-bit A/D converter. The HT82V26 operates from a single 5V power supply, typically consumes 400mW of power. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. Block Diagram A V D D V IN R A V S S R E F T R E F B + A V D D C D S A V S S D R V D D P G A O E 9 - B it D A C V IN G + B A N D G A P R e fe re n c e C D S C D S O F F S E T C D S C L K 1 Rev. 1.50 1 6 1 6 :8 M U X 8 D O U T + C o n fig u r a tio n R e g is te r M U X R e g is te r P G A 6 In p u t C la m p B ia s 1 6 - B it A D C 3 .1 M U X P G A 9 - B it D A C V IN B D R V S S 9 - B it D A C 9 R E D G R E E N B L U E R E D G R E E N B L U E G a in R e g is te r s D ig ita l C o n tro l In te rfa c e S C L K S L O A D S D A T A O ffs e t R e g is te r s C D S C L K 2 A D C C L K 1 June 24, 2004 HT82V26 Pin Assignment C D S C L K 1 1 2 8 A V D D C D S C L K 2 2 2 7 A V S S A D C C L K 3 2 6 V IN R O E 4 2 5 O F F S E T D R V D D 5 2 4 V IN G D R V S S 6 2 3 C M L D 7 (M S B ) 7 2 2 V IN B D 6 8 2 1 R E F T D 5 9 2 0 R E F B D 4 1 0 1 9 A V S S D 3 1 1 1 8 A V D D D 2 1 2 1 7 S L O A D D 1 1 3 1 6 S C L K D 0 (L S B ) 1 4 1 5 S D A T A H T 8 2 V 2 6 2 8 S S O P -A /S O P -A Pin Description Pin No. Pin Name I/O Description 1 CDSCLK1 DI CDS reference clock pulse input 2 CDSCLK2 DI CDS data clock pulse input 3 ADCCLK DI A/D sample clock input for 3-channels mode 4 OE DI Output enable, active low 5 DRVDD P Digital driver power 6 DRVSS P Digital driver ground 7~14 D7~D0 DO 15 SDATA DI/DO 16 SCLK DI Clock input for serial interface 17 SLOAD DI Serial interface load pulse 18, 27 AVSS P Analog ground 19, 28 AVDD P Analog supply 20 REFB AO 21 REFT AO Reference decoupling 22 VINB AI Analog input, blue 23 CML AO Internal reference output 24 VING AI Analog input, green 25 OFFSET AO Clamp bias level decoupling 26 VINR AI Analog input, red Digital data output Serial data input/output Reference decoupling Absolute Maximum Ratings Supply Voltage ..........................VSS-0.3V to VSS+5.5V Storage Temperature ...........................-50°C to 125°C Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.50 2 June 24, 2004 HT82V26 D.C. Characteristics Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit ¾ ¾ V Logic Inputs VIH High Level Input Voltage ¾ ¾ 0.8´VDD VIL Low Level Input Voltage ¾ ¾ ¾ ¾ 0.2´VDD V IIH High Level Input Current ¾ ¾ ¾ 10 ¾ mA IIL Low Level Input Current ¾ ¾ ¾ 10 ¾ mA CIN Input Capacitance ¾ ¾ ¾ 10 ¾ pF V Logic Outputs VOH High Level Output Voltage ¾ ¾ VDD-0.5 ¾ ¾ VOL Low Level Output Voltage ¾ ¾ ¾ ¾ 0.5 V IOH High Level Output Voltage ¾ ¾ ¾ 1 ¾ mA IOL Low Level Output Voltage ¾ ¾ ¾ 1 ¾ mA Min. Typ. Max. Unit A.C. Characteristics Symbol Parameter Test Conditions VDD Conditions Power Supplies VADD AVDD ¾ ¾ 4.75 5 5.25 V VDRDD DRVDD ¾ ¾ 3 5 5.25 V Maximum Conversion Rate tMAX3 3-channel Mode with CDS ¾ ¾ 30 ¾ ¾ MSPS tMAX2 2-channel Mode with CDS ¾ ¾ 30 ¾ ¾ MSPS tMAX1 1-channel Mode with CDS ¾ ¾ 25 ¾ ¾ MSPS ADC Resolution ¾ ¾ ¾ 16 ¾ Bits Integral Nonlinear (INL) ¾ ¾ ¾ ±32 ¾ LSB Differential Nonlinear (DNL) ¾ ¾ -1 ¾ 1 LSB Offset Error ¾ ¾ -100 ¾ 100 mV Gain Error ¾ ¾ ¾ 5 ¾ %FSR 2.0 ¾ Vp-p Accuracy (Entire Signal Path) Analog Inputs RFS Full-scale Input Range ¾ ¾ ¾ Vi Input Limits ¾ ¾ AVSS-0.3 ¾ AVDD+0.3 V Ci Input Capacitance ¾ ¾ ¾ 10 ¾ pF Ii Input Current ¾ ¾ ¾ 10 ¾ nA Amplifiers Rev. 1.50 PGA Gain at Minimum ¾ ¾ ¾ 1 ¾ V/V PGA Gain at Maximum ¾ ¾ ¾ 5.85 ¾ V/V PGA Gain Resolution ¾ ¾ ¾ 6 ¾ Bits Programmable Offset at Minimum ¾ ¾ ¾ -250 ¾ mV Programmable Offset at Maximum ¾ ¾ ¾ 250 ¾ mV Offset Resolution ¾ ¾ ¾ 9 ¾ Bits 3 June 24, 2004 HT82V26 Symbol Parameter Test Conditions Min. Typ. Max. Unit ¾ 0 ¾ 70 °C ¾ ¾ 400 ¾ mW VDD Conditions ¾ ¾ Temperature Range tA Operating Power Consumption Ptot Total Power Consumption Timing Specification Symbol Parameter Min. Typ. Max. Unit Clock Parameters tPRA 3-channel pixel rate 100 ¾ ¾ ns tPRB 2-channel (Even-Odd) pixel rate 66 ¾ ¾ ns tPRC 1-channel pixel rate 40 ¾ ¾ ns tADCLK ADCCLK Pulse Width 16 ¾ ¾ ns tC1 CDSCLK1 Pulse Width 12 ¾ ¾ ns tC2 CDSCLK2 Pulse Width 12 ¾ ¾ ns tC1C2 CDSCLK1 Falling to CDSCLK2 Rising 0 ¾ ¾ ns tADC1 ADCCLK Rising to CDSCLK1 Falling 0 ¾ ¾ ns tADC2 ADCCLK Rising to CDSCLK2 Falling 0 ¾ ¾ ns tAD Analog Sampling Delay 5 ¾ ¾ ns 3-Channel Mode Only taC2C1 CDSCLK2 Falling to CDSCLK1 Rising 30 ¾ ¾ ns taC2ADR CDSCLK2 Falling to ADCCLK Rising 30 ¾ ¾ ns 2-Channel Mode Only tbC2ADR CDSCLK2 Falling to ADCCLK Rising 30 ¾ ¾ ns tbC1ADR CDSCLK1 Rising to ADCCLK Rising 15 ¾ ¾ ns tbC2C1 CDSCLK2 Falling to CDSCLK1 Rising 15 ¾ ¾ ns 1-Channel Mode Only tcC2C1 CDSCLK2 Falling to CDSCLK1 Rising 15 ¾ ¾ ns tcC1ADF CDSCLK1 Rising to ADCCLK Falling 0 ¾ ¾ ns tcC2ADR CDSCLK2 Falling to CDSCLK1 Rising 20 ¾ ¾ ns Serial Interface fSCLK Maximum SCLK Frequency 10 ¾ ¾ MHz tLS SLOAD to SCLK Setup Time 10 ¾ ¾ ns tLH SCLK to SLOAD Hold Time 10 ¾ ¾ ns tDS SDATA to SCLK Rising Setup Time 10 ¾ ¾ ns tDH SCLK Rising to SDATA Hold Time 10 ¾ ¾ ns tRDV Falling to SDATA Valid 10 ¾ ¾ ns Output Delay ¾ 8 ¾ ns Latency (Pipeline Delay) ¾ 9 ¾ Cycles Data Output tOD Rev. 1.50 4 June 24, 2004 HT82V26 Functional Description The offset error is the deviation of the actual first code transition level from the ideal level. Integral Nonlinear (INL) Integral nonlinear error refers to the deviation of each individual code from a line drawn from zero scale through a positive full scale. The point used as zero scale occurs 1/2 LSB before the first code transition. A positive full scale is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Gain Error The last code transition should occur for an analog value of 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and the last code transitions and the ideal difference between the first and the last code transitions. Differential Nonlinear (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed for the 16-bit resolution indicates that all the 65536 codes respectively, are present in the over-all operating range. Aperture Delay The aperture delay is the time delay that occurs when a sampling edge is applied to the HT82V26 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clock¢s falling edge to the instant the actual internal sample is taken. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. Internal Register Descriptions Address Data Bits Register Name A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Configuration 0 0 0 0 0 1 3-CH CDS on Clamp Voltage Enable Power Down Output Delay 1 byte out MUX 0 0 1 0 RGB/ Red Green Blue BGR Delay enable Red PGA 0 1 0 0 0 0 MSB LSB Green PGA 0 1 1 0 0 0 MSB LSB Blue PGA 1 0 0 0 0 0 MSB LSB Red Offset 1 0 1 MSB LSB Green Offset 1 1 0 MSB LSB Blue Offset 1 1 1 MSB LSB CDSCLK1 CDSCLK2 ADCCLK delay delay delay Internal Register Map Configuration Register The configuration register controls the HT82V26¢s operating mode and bias levels. Bits D6 should always be set high. Bit D5 will configure the HT82V26 for the 3-channel (high) mode of operation. Setting the bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the HT82V26¢s input clamp. This bit should always be set high for the 4V clamp bias, unless a CCD with a reset feed through transient exceeding 2V is used. Setting the bit D3 low, the clamp voltage is 3V. Bit D2 controls the power-down mode. Setting bit D2 high will place the HT82V26 into a very low power ²sleep² mode. All register contents are retained while the HT82V26 is in the power-down state. Setting bit D1 high will configure the HT82V26 for the digital output (D0~D7) delay 2ns. Bit D0 controls the output mode of the HT82V26. Setting bit D0 high will enable a single byte output mode where only 8 MSBs of the 16b ADC is output. If bit D0 is set low, then the 16b ADC output is multiplexed into two bytes. Rev. 1.50 5 June 24, 2004 HT82V26 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 channels CDS operation Clamp bias Power-down 1 byte out Output delay (High-byte only) 1=On* 1=CDS mode* 1=4V* 1=On 1=On 0=Off 0=SHA mode 0=Off (Normal)* 0=Off* Set to 0 Set to 0 Set to 1 0=3V 1=On 0=Off* Configuration Register Settings Note: * Power-on default value MUX Register The MUX register controls the sampling channel order and the 2-channel mode configuration in the HT82V26. Bits D8 should always be set low. Bit D7 is used when operating in the 3-channel mode or the 2-channel mode. Setting bit D7 high will sequence the MUX to sample the red channel first, then the green channel, and then the blue channel. When in the 3-channel mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first (see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 rising edge will always reset the MUX to sample the blue channel first. Bits D6, D5 and D4 are used when operating in 1 or 2-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-channel mode. The two channel mode is selected by setting two of the channel select bits (D4~D6) high. The MUX samples the channels in the order selected by bit D7. Bits D0~D3 are used for controlling CDSCLK1, CDSCLK2 and ADCCLK internal delay. D8 D7 D6 D5 MUX Order Set to 0 1=R-G-B* 0=B-G-R D4 D3 Channel Select 1=RED* 1=GREEN 0=Off 0=Off* D2 D1 Enable Delay CDS1 Delay 1=BLUE 0=Off* D0 CDS2 Delay ADCK Delay 0=Off 0=2ns* 0=2ns* 0=0ns* 1=On* 1=4ns 1=4ns 1=2ns MUX Register Settings Note: * Power-on default value PGA Gain Registers There are three PGA registers for use in individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See figure for a graph of the PGA gain versus PGA register code. The coding for the PGA registers is a straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x). The HT82V26 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1x (0dB) to 5.85x (15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in nonlinear proportion with the register 5.85 code, according to the following the equation: Gain= 63 - G 1+ 4.85 ´´ ( ) 63 Where G is the decimal value of the gain register contents, and varies from 0 to 63. 5 .8 5 1 2 5 .0 4 .0 6 3 .0 3 2 .0 G A IN -d B ( 9 0 G A IN -V /V ( ) ) 1 5 1 .0 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 4 4 4 8 5 2 5 6 6 0 6 3 P G A r e g is te r v a lu e - - D e c im a l PGA Gain Transfer Function Rev. 1.50 6 June 24, 2004 HT82V26 D8 D7 D6 D5 D4 Set to 0 Set to 0 Set to 0 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D3 D2 D1 D0 Gain (V/V) Gain (dB) 1.0 1.013 . . . 5.43 5.85 0.0 0.12 . . . 14.7 15.3 LSB 0 0 . . . 1 1 0 0 0 0 0* 1 1 1 1 1 0 1 PGA Gain Register Settings Note: * Power-on default value Offset Registers There are three PGA registers for use in individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control the offset range from -250mV to 250mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. The Table shows the offset range as a function of the bits D8 through D0. D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB Offset (mV) LSB 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 0 0 . . . 1 0 0 . . . 1 0 0 0 0 0* 1 1 0 0 1 0 0 1 0 1 1 1 1 0 0.98 . . . 250 0 -0.98 . . . -250 Note: * Power-on default value Timing Diagrams S D A T A A 2 R /W b tD A 1 A 0 H tD D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S S C L K tL tL S H S L O A D Serial Write Operation Timing S D A T A R /W b A 2 A 1 A 0 D 8 tR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D V S C L K tL tL S H S L O A D Serial Read Operation Timing Rev. 1.50 7 June 24, 2004 HT82V26 A n a lo g In p u t (R , G , B ) P ix e l ( N + 3 ) tA P ix e l ( N + 4 ) P ix e l ( N + 5 ) D tC tP 1 R A C D S C L K 1 tC tC 1 C 2 ta 2 C 2 C 1 C D S C L K 2 tA ta D C 2 tA C 2 A D R tA D C 1 tA D C L K D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 G (N -2 ) H ig h B y te G (N -2 ) B (N -2 ) B (N -2 ) L o w B y te H ig h B y te R (N -1 ) R (N -1 ) H ig h B y te L o w B y te L o w B y te G (N -1 ) G H ig h B y te (N -1 ) L o w B y te D B (N -1 ) B (N -1 ) R (N ) R (N ) G H ig h B y te L o w B y te H ig h B y te L o w B y te H ig h B y te (N ) G (N ) B (N ) L o w B y te H ig h B y te 3-Channel CCD Mode Timing (Select R-G-B Mode) P ix e l ( N + 3 ) A n a lo g In p u t (G , B ) tC tA 1 P ix e l ( N + 4 ) P ix e l ( N + 5 ) D tP P ix e l ( N + 6 ) R B C D S C L K 1 tC tC 1 C 2 2 tb C 2 C 1 tb C 1 A D R C D S C L K 2 tA tA D C 2 tA D C 1 tA D C L K D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 B (N -4 ) B (N -4 ) H ig h B y te L o w B y te G (N -3 ) G H ig h B y te (N -3 ) L o w B y te B (N -3 ) B (N -3 ) H ig h B y te L o w B y te G (N -2 ) G H ig h B y te (N -2 ) L o w B y te B (N -2 ) B (N -2 ) H ig h B y te L o w B y te G (N -1 ) G H ig h B y te D (N -1 ) B (N -1 ) B (N -1 ) L o w B y te H ig h B y te L o w B y te G (N ) H ig h B y te 2-Channel CCD Mode Timing (Select G-B Mode) Rev. 1.50 8 June 24, 2004 HT82V26 P ix e l (N + 5 ) P ix e l (N + 6 ) tA A n a lo g In p u t tC P ix e l (N + 7 ) P ix e l (N + 8 ) P ix e l (N + 9 ) P ix e l (N + 1 0 ) P ix e l (N + 1 1 ) D tP 1 R C C D S C L K 1 tC tC C 2 C 1 tC 1 C 2 2 C D S C L K 2 tC tA C 1 A D F tA D C 2 tA D C L K D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 P ix e l (N -7 ) P ix e l (N -6 ) H ig h B y te P ix e l (N -6 ) L o w B y te P ix e l (N -5 ) H ig h B y te P ix e l (N -5 ) L o w B y te P ix e l (N -4 ) H ig h B y te P ix e l (N -4 ) L o w B y te P ix e l (N -3 ) H ig h B y te P ix e l (N -3 ) L o w B y te P ix e l (N -2 ) H ig h B y te P ix e l (N -2 ) L o w B y te P ix e l (N -1 ) H ig h B y te P ix e l (N -1 ) L o w B y te D P ix e l (N ) H ig h B y te P ix e l (N ) L o w B y te P (N H B ix e l + 1 ) ig h y te 1-Channel CCD Mode Timing P ix e l ( N + 3 ) A n a lo g In p u t (R , G , B ) tA tC P ix e l ( N + 5 ) P ix e l ( N + 4 ) D tP 2 R A C D S C L K 2 tA D C 2 ta tA C 2 A D R tA D C 2 D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 G (N -2 ) H ig h B y te G (N -2 ) L o w B y te B (N -2 ) B (N -2 ) H ig h B y te L o w B y te R (N -1 ) R (N -1 ) H ig h B y te L o w B y te G (N -1 ) G H ig h B y te (N -1 ) L o w B y te B (N -1 ) B (N -1 ) R (N ) R (N ) G H ig h B y te L o w B y te H ig h B y te L o w B y te H ig h B y te D (N ) G (N ) L o w B y te B (N ) H ig h B y te 3-Channel SHA Mode Timing (Select R-G-B Mode) Rev. 1.50 9 June 24, 2004 HT82V26 P ix e l ( N + 5 ) P ix e l ( N + 3 ) P ix e l ( N + 4 ) A n a lo g In p u t (G , B ) tA tC tb 2 P ix e l ( N + 6 ) D tb C 2 A D R P R B C D S C L K 2 tA D C L K tA tA D C 2 tb D C 2 tA C 2 A D R D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 B (N -4 ) B (N -4 ) H ig h B y te L o w B y te (N -3 ) G G H ig h B y te (N -3 ) L o w B y te B (N -3 ) B (N -3 ) H ig h B y te L o w B y te G (N -2 ) G H ig h B y te (N -2 ) L o w B y te B (N -2 ) B (N -2 ) H ig h B y te L o w B y te G (N -1 ) G H ig h B y te D (N -1 ) B (N -1 ) B (N -1 ) L o w B y te H ig h B y te L o w B y te G (N ) H ig h B y te 2-Channel SHA Mode Timing (Select G-B Mode) P ix e l (N + 6 ) P ix e l (N + 5 ) P ix e l (N + 8 ) A n a lo g In p u t tA P ix e l (N + 1 0 ) P ix e l (N + 7 ) P ix e l (N + 1 1 ) P ix e l (N + 9 ) D tC tP 2 R C C D S C L K 2 tC tA C 2 A D F tA D C 2 D C 2 tC tA C 2 A D F tA D C L K D C L K A D C C L K tO O u tp u t D a ta D 7 ~ D 0 P ix e l (N -7 ) P ix e l (N -6 ) H ig h B y te P ix e l (N -6 ) L o w B y te P ix e l (N -5 ) H ig h B y te P ix e l (N -5 ) L o w B y te P ix e l (N -4 ) H ig h B y te P ix e l (N -4 ) L o w B y te P ix e l (N -3 ) H ig h B y te P ix e l (N -3 ) L o w B y te P ix e l (N -2 ) H ig h B y te P ix e l (N -2 ) L o w B y te P ix e l (N -1 ) H ig h B y te P ix e l (N -1 ) L o w B y te D P ix e l (N ) H ig h B y te P ix e l (N ) L o w B y te P (N H B ix e l + 1 ) ig h y te 1-Channel SHA Mode Timing Rev. 1.50 10 June 24, 2004 HT82V26 Application Circuits The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below. The recommended input coupling capacitor value is 0.1mF. A single ground plane is recommended for the HT82V26. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V26. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1mF decoupling capacitors should be located as close as possible to the HT82V26 pins. When operating in a single channel mode, the unused analog inputs should be grounded. V C lo c k In p u ts 1 2 3 A V D D C D S C L K 2 A V S S A D C C L K 5 V /3 V 4 O E 5 6 7 8 9 1 0 1 1 1 2 1 3 D a ta In p u ts C D S C L K 1 1 4 V IN R O F F S E T D R V D D V IN G D R V S S C M L D 7 (M S B ) V IN B D 6 R E F T D 5 R E F B D 4 A V S S D 3 A V D D D 2 S L O A D D 1 S C L K D 0 (L S B ) S D A T A D D 2 8 0 .1 m F 2 7 2 6 0 .1 m F 2 4 0 .1 m F 2 3 2 2 0 .1 m F 0 .1 m F 2 0 1 9 0 .1 m F 1 0 m F 1 8 2 3 4 C D S C L K 2 A V S S O E 5 6 7 8 9 1 0 1 1 1 2 1 3 Note: A V D D A D C C L K 5 V /3 V D a ta In p u ts C D S C L K 1 5 V 1 6 1 5 1 4 V IN R O F F S E T D R V D D V IN G D R V S S C M L D 7 (M S B ) V IN B D 6 R E F T D 5 R E F B D 4 A V S S D 3 A V D D D 2 S L O A D D 1 S C L K D 0 (L S B ) S D A T A H T 8 2 V 2 6 (S H A M o d e ) 2 8 0 .1 m F 0 .1 m F 1 7 S e r ia l In p u ts V 1 1 .0 m F 0 .1 m F 2 1 H T 8 2 V 2 6 (C D S M o d e ) C lo c k In p u ts 0 .1 m F 2 5 D D 0 .1 m F R e d In p u t G re e n In p u t B lu e In p u t 2 7 2 6 2 5 2 4 2 3 R e d In p u t G re e n In p u t B lu e In p u t D C L e v e l 0 .1 m F 2 2 2 1 0 .1 m F 2 0 1 9 1 8 1 7 1 6 1 5 0 .1 m F 1 0 m F 0 .1 m F 0 .1 m F 5 V S e r ia l In p u ts For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V26 without the use of coupling capacitors. The OFFSET pin should be grounded if the inputs to the HT82V26 are to be referenced to ground, or a DC offset voltage should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs. The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground. Rev. 1.50 11 June 24, 2004 HT82V26 Package Information 28-pin SSOP (209mil) Outline Dimensions 1 5 2 8 A B 1 4 1 C C ' G H D E Symbol Rev. 1.50 a F Dimensions in mil Min. Nom. Max. A 291 ¾ 323 B 196 ¾ 220 C 9 ¾ 15 C¢ 396 ¾ 407 D 65 ¾ 73 E ¾ 25.59 ¾ F 4 ¾ 10 G 26 ¾ 34 H 4 ¾ 8 a 0° ¾ 8° 12 June 24, 2004 HT82V26 28-pin SOP (300mil) Outline Dimensions 2 8 1 5 A B 1 1 4 C C ' G H D E Symbol Rev. 1.50 a F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 697 ¾ 713 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 13 June 24, 2004 HT82V26 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 28W (300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.2±0.2 Rev. 1.50 14 June 24, 2004 HT82V26 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 28W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width 24.0±0.3 P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 10.85±0.1 B0 Cavity Width 18.34±0.1 K0 Cavity Depth 2.97±0.1 t Carrier Tape Thickness 0.35±0.01 C Cover Tape Width Rev. 1.50 21.3 15 June 24, 2004 HT82V26 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 16 June 24, 2004