UTC-IC TSSOP-28

UNISONIC TECHNOLOGIES CO., LTD
M1008
Preliminary
CMOS IC
16-BIT CCD/CIS ANALOG
SIGNAL PROCESSOR
„
DESCRIPTION
The M1008 is a 16-bit CCD/CIS analog signal processor for
imaging applications. A 3-channel architecture is designed to sample
and control the outputs of tri-linear color CCD arrays. Each channel
processes one color analog signal and includes an input clamp,
Correlated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), and a 16-bit A/D converter.
If there are sensors such as Contact Image Sensors (CIS) and
CMOS active pixel sensors, the CDS amplifiers are not necessary.
The 16-bit digital output is composed of high and low 8-bit
output and is assessed by two reading cycles. The internal registers
are programmed by a 3-wire serial interface which provides gain,
offset and operating mode adjustments.
The typical operation power of M1008 is 400mW in 5V power
supply.
„
TSSOP-28
FEATURES
* 400mW In 5V Operation Supply
* Under 2mA Power-Down Mode
* Built-In16-Bit 30 Msps A/D Converter
* No Missing Codes
* Input Clamp Circuitry
* Correlated Double Sampling
* Programmable Gain
* 250mV Programmable Offset
* Built-In Voltage Reference
* Programmable 3-Wire Serial Interface
* 3V/5V Digital I/O Compatibility
* Up To 25 Msps In 1-Channel Operation
* Up To 30 Msps In 2-Channel (Even-Odd) Operation
* Up To 30 Msps In 3-Channel Operation
„
ORDERING INFORMATION
Ordering Number
M1008G-P28-T
M1008G-P28-R
Package
TSSOP-28
TSSOP-28
M1008G-P28-T
(1) Packing Type
(2) Package Type
(3) Halogen Free
www.unisonic.com.tw
Copyright © 2010 Unisonic Technologies Co., Ltd
Packing
Tube
Tape Reel
(1) T: Tube, R: Tape Reel
(2) P28: TSSOP-28
(3) G: Halogen Free
1 of 11
QW-R502-434.a
M1008
Preliminary
„
PIN CONFIGURATIONS
„
PIN DESCRIPTION
CMOS IC
PIN NO.
PIN NAME
PIN TYPE
PIN DESCRIPTION
1
CDSCLK1
DI
CDS reference clock pulse input
2
CDSCLK2
DI
CDS data clock pulse input
3
ADCCLK
DI
A/D sample clock input for 3-channels mode
4
DI
Output enable, active low
OE
5
DRVDD
P
Digital driver power
6
DRVSS
P
Digital driver ground
7~14
D7~D0
DO
Digital data output
15
SDATA
DI/DO
Serial data input/output
16
SCLK
DI
Clock input for serial interface
17
SLOAD
DI
Serial interface load pulse
18,28
AVDD
P
Analog supply
19,27
AVSS
P
Analog ground
20
REFB
AO
Reference decoupling
21
REFT
AO
Reference decoupling
22
VINB
AI
Analog input, blue
23
CML
AO
Internal reference output
24
VING
AI
Analog input, green
25
OFFSET
AO
Clamp bias level decoupling
26
VINR
AI
Analog input, red
Note: I=input, O=output, I/O=input/output, P=power supply, G=ground
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
BLOCK DIAGRAM
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VDD
VSS-0.3 to VSS+5.5
V
Input Voltage
VIN
VSS-0.3 to VDD+0.3
V
Ambient Operation Temperature
TOPR
-25 ~ +75
°C
Storage Temperature
TSTG
-50 ~ +125
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„
ELECTRICAL CHARACTERISTICS (AVDD=5V, DVDD=3V, TA=25°C. Unless otherwise specified)
PARAMETER
Analog Power Supply
Digital Power Supply
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
ADC Resolution
Integral Nonlinear (INL)
Differential Nonlinear (DNL)
Offset Error
Gain Error
Full-Scale Input Range
Input Limits
Input Current
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution
Programmable Offset at Minimum
Programmable Offset at Maximum
Offset Resolution
Operating
Total Power Consumption
High Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE , SCK, SLOAD)
Low Level Input Voltage
(CDSCLK1, CDSCLK2, ADCCLK,
OE , SCK, SLOAD)
High Level Input Voltage (SDATA)
Low Level Input Voltage (SDATA)
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
(SDATA, D0~D7)
Low Level Output Voltage
(SDATA, D0~D7)
High Level Output Current
Low Level Output Current
SYMBOL
VADD
VDRDD
tMAX3
tMAX2
tMAX1
MIN
4.75
3
30
30
25
TYP
5
5
MAX
5.25
5.25
16
±32
-1
-100
RFS
VI(LIMIT)
IIN
AVSS-0.3
TA
Ptot
0
VIH
0.8*VDD
1
100
V
0.2*VDD
VIH1
VIL1
IIH
IIL
CIN
0.8*VDD
VOH
VDD-0.5
0.2*VDD
10
10
10
V
V
V
uA
uA
pF
V
0.5
VOL
IOH
IOL
UNIT
V
V
MSPS
MSPS
MSPS
Bits
LSB
LSB
mV
%FSR
5
2.0
VP-P
AVDD+0.3
5
V
10
nA
1
V/V
5.85
V/V
6
Bits
-250
mV
250
mV
9
Bits
70
°C
400
mW
VIL
UNISONIC TECHNOLOGIES CO., LTD
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TEST CONDITION
1
1
V
mA
mA
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
TIMING SPECIFICATION
PARAMETER
3-Channel Pixel Rate
2-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Rising to CDSCLK1 Falling
ADCCLK Rising to CDSCLK2 Falling
Analog Sampling Delay
3-CHANNEL Mode Only
CDSCLK2 Falling to CDSCLK1 Rising
CDSCLK2 Falling to ADCCLK Rising
2-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Rising
CDSCLK2 Falling to CDSCLK1 Rising
1-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDARA Hold Time
Falling to SDATA Valid
DATA OUTPUT
Output Delay
Latency(Pipeline Delay)
SYMBOL
tPRA
tPRB
tPRC
tADCLK
tC1
tC2
tC1C2
tADC1
tADC2
tAD
MIN
100
66
40
16
12
12
0
0
0
5
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
taC2C1
taC2ADR
30
30
ns
ns
tbC2ADR
tbC1ADR
tbC2C1
30
15
15
ns
ns
ns
tcC2ADR
tcC1ADF
tcC2C1
20
0
15
ns
ns
ns
fSCLK
tLS
tLH
tDS
tDH
tRDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
tOD
UNISONIC TECHNOLOGIES CO., LTD
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TEST CONDITION
8
9
ns
Cycles
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QW-R502-434.a
M1008
Preliminary
CMOS IC
FUNCTIONAL DESCRIPTION
„
Offset Error
At a level of 1/2 LSB above the nominal zero scale voltage, the first ADC code transition should come. The
offset error is defined as the deviation between the actual first code transition level with the ideal level.
Gain Error
At a level of 1/2 LSB below the nominal full-scale voltage, the last code transition should come. Gain error is
defined as the deviation of the actual difference between the first and the last code transitions and the ideal
difference between the first and the last code transitions.
Internal Register Descriptions
Register
Name
Address
A2 A1 A0
D8
D7
D6
D5
D4
Configuration
0
0
0
0
0
1
3-CH
CDS
on
MUX
0
0
1
0
RGB/
BGR
Red
Green
Blue
Red PGA
Green PGA
Blue PGA
Red Offset
Green Offset
Blue Offset
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
MSB
MSB
MSB
0
0
0
0
0
0
MSB
MSB
MSB
Data Bits
D3
Clamp
Voltage
Delay
enable
D2
D1
Enable
Power Down
CDSCLK1
Delay
Output
Delay
CDSCLK
2 Delay
D0
1 byte out
ADCCLK
Delay
LSB
LSB
LSB
LSB
LSB
LSB
Internal Register Map
Configuration Register
The configuration register sets the M1008’s operating mode and bias levels. Bits D6 should always hold high.
Bit D5 configures the M1008 for the 3-channel(high) operation mode. Bit D4 will be set high to implement the CDS
mode operation, and be set low to implement the SHA mode operation.
Bit D3 controls the dc bias level of the M1008’s input clamp. This bit should hold high for the 4V clamp bias,
unless a CCD with a reset feed through transient exceeding 2V is applied. The clamp voltage is 3V with this bit low.
Bit D2 controls the power-down mode. With bit D2 high, the M1008 will come to a very low power “sleep” mode,
in which all register contents are retained. Bit D1 is set high for the digital output (D0~D7) delay 2ns. Bit D0
configures the output mode of the M1008. Setting the bit high can implement a single byte output mode in which only
one byte of the 16b ADC is output. Inversely, the 16b ADC output is multiplexed into two bytes.
D8
D7
D6
D5
3-Channels
0
0
1
1=on (Note)
0=off
D4
D3
D2
CDS Operation
Clamp Bias
Power-Down
1=CDS mode
1=4V (Note)
1=on
(Note)
0=SHA mode
0=3V
0=off (Note)
Configuration Register Settings
D1
Output Delay
D0
High Byte Out
1=on
1=on
0=off (Note)
0=off
Note: Power-on default value
MUX Register
The sampling channel order and 2-channel mode configuration in the M1008 are both controlled by the MUX
register. Bits D8 should hold low. Bit D7 goes into effect in the 3-channel mode or the 2-channel mode of operation.
Setting it high will sequence the MUX to sample the red channel first, then the green channel, and the last blue
channel. In the 3-channel mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first
(see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red third,
the CDSCLK2 rising edge will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 go into
effect when operating in 1 or 2-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to
sample the green channel. Bit D4 is set high to sample the blue channel. The MUX remains stationary during
1-channel mode. Setting two of Bits D4~D6 high to configure the two channel mode, and the sequence of sampling
is selected by bit D7. Bits D0~D3 are applied to controlling CDSCLK1, CDSCLK2 and ADCCLK internal delay.
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QW-R502-434.a
M1008
Preliminary
CMOS IC
FUNCTIONAL DESCRIPTION (Cont.)
„
D8
D7
D6
MUX order
0
1=R-G-B
(Note)
0=B-G-R
D5
D4
Channel Select
1=Red
(Note)
0=off
1=Green
0=off
(Note)
1=Blue
0=off
(Note)
D3
Enable
Delay
1=on
(Note)
0=off
D2
CDS1
Delay
D1
CDS2
Delay
D0
ADCK
Delay
1=4ns
1=4ns
1=2ns
0=2ns
(Note)
0=2ns
(Note)
0=0ns
(Note)
MUX Register Settings
Note: Power-on default value
PGA Gain Registers
There are three PGA registers for use in respectively programming the gain of the red, green and blue
channels. Bits D8, D7 and D6 in each register must hold low, and bits D5 through D0 control the gain range in 64
increments. The coding for the PGA registers is a straight binary. An all zero word corresponds to the minimum gain
setting (1x) and an all one word corresponds to the maximum gain setting (5.85x).
The M1008 distributes one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range
from 1x (0dB) to 5.85x (15.3dB), adjustable in 64 steps. Although the gain curve is approximately linear in dB, the
gain in V/V varies in nonlinear proportion with the register code, according to the following the equation:
5.85
Gain =
63 - G
1 + 4.85 * (
)
63
Where G is the decimal value of the gain register contents, and varies from 0 to 63.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain(V/V) Gain(dB)
0
0
0
MSB
LSB
1.0
0.0
0
0
0
0
0 (Note)
0
0
0
0
1.013
0.12
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
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.
.
.
5.43
14.7
1
1
1
0
0
0
0
1
1
5.85
15.3
1
0
0
0
1
1
1
1
1
Note: Power-on default value
Offset Registers
There are three PGA registers for use in respectively programming the offset of the red, green, and blue
channels. Bits D8 through D0 control the offset range from -250mV to 250mV in 512 increments.
The coding for the offset registers is sign magnitude, with D8 as the sign bit. The following table shows the
offset range as a function of the bits D8 through D0.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset(mV)
MSB
LSB
0
0
0
0
0
0
0
0
0
0 (Note)
0.98
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
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.
.
.
.
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.
250
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
-0.98
1
0
0
0
0
0
0
0
1
.
.
.
.
.
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.
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.
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.
.
.
-250
1
1
1
1
1
1
1
1
1
Note: Power-on default value
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
TIMING DIAGRAMS
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M1008
„
Preliminary
CMOS IC
TIMING DIAGRAMS (Cont.)
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
TYPICAL APPLICATIONS CIRCUIT
CDS Mode
5V
CDSCLK1
1
CDSCLK1
AVDD
28
CDSCLK2
2
CDSCLK2
AVSS
27
ADCCLK
3
ADCCLK
5V/3V
µP
4
OE
5
DRVDD
VINR
26
OFFSET
25
VING
24
CML
23
VINB
22
D6
REFT
21
9
D5
REFB
20
10
D4
AVSS
19
11
D3
AVDD
18
12
D2
SLOAD
17
13
D1
SCLK
16
SDATA
15
6
DRVSS
7
D7(MSB)
8
M1008
0.1µF
Red Input
Green Input
Blue Input
0.1µF
0.1µF
1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
10µF
0.1µF
SLOAD
SCLK
SDATA
14
D0(LSB)
0.1µF
5V
Data outputs
SHA Mode
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QW-R502-434.a
M1008
„
Preliminary
CMOS IC
APPLICATION CONSIDERATIONS
The digital outputs load should be minimized, either by using short traces to the digital ASIC, or by using
external digital buffers. In order to minimize the number of code conversion in the main output of the impact of
transients, which should happen in the coincidences CDSCLK2 falling on or before ADCCLK rising edge. All 0.1μF
decoupling capacitor should be located as close as possible to the M1008 pins. When operating in a single channel
mode, the unused analog inputs should be grounded.
For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the
analog input signals are directly connected to the M1008 without the use of coupling capacitors. The OFFSET pin
should be grounded if the inputs to the M1008 are to be referenced to ground, or a DC offset voltage should be
applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs. The analog input
signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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