HYNIX GM6535

GM6535
GM6535
60 MHz Universal Programmable
Dual PLL Frequency synthesizer
GENERAL DESCRIPTIONS
FEATURES
The GM6535 is a dual phase – locked loop
(PLL) frequency synthesizer especially designed for
CT-1 cordless phone applications worldwide. This
frequency synthesizer is also for any products with
frequency operation at 60 MHz or below.
• Operating Voltage Range: 2.5 to 5.5 V
• Operating Temperature Range:-40 to +75¡ É
• Operating Power Consumption:[email protected]
• Maximum Operating Frequency:
60MHz@200mVp-p, VDD=2.5V
• 3 or 4 Pins Used for serial MCU Interface
• Power Saving Mode Controlled by MCU
• Lock Detect Signal
• On-Chip Reference Oscillator Supports External
Crystals to 16.0 MHz
• Reference Frequency Counter Division Range: 16 to
4095
• Auxiliary Reference Frequency Counter Division
Range: 16 to 16,383
• Transmit Counter Division Range:16 to 65,535
• Receive Counter Division Range: 16 to 65,53
The device features fully programmable
receive, transmit, reference, and auxiliary reference
counters accessed through an MCU serial interface,
this feature allows this device to operate in any CT1 cordless phone application.
The device consists of two independent phase
detectors for transmit and receive loops. A common
reference oscillator, driving two independent
reference frequency counters, provides independent
reference frequencies for transmit and receive loops.
The auxiliary reference counter allows the
user to select an additional reference frequency for
receive and transmit loops if required.
PIN CONFIGURATION
CLK
AD in
D in
ENB
MCUCLK
Vss
OSCout
OSCi
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
LD
Tx PDOUT
CLK
AD in
D in
ENB
MCUCLK
Vss
OSCout
OSCi
fin-T
TxPS/fTx
VDD
RxPS/fRx
RxPDo
1
16
LD
2
15
3
14
4
13
5
12
6
11
7
8
10
Tx PDOUT
fin-T
TxPS/fTx
VDD
RxPS/fRx
RxPDo
fin-R
9
fin-R
16 SOP (150Mil)
16DIP
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to vss )
Ranting
Symbol
VDD
DC Supply Voltage
Vin
Input Voltage, all Inputs
Iin , Iout
DC Current Drain Per Pin
IDD , ISS
DC Current Drain VDD or VSS Pins
Tstg
Storage Temperature Range
1
Value
-0.5 to +6.0
-0.5 to VDD +0.5
10
30
-65 to + 150
Unit
V
V
mA
mA
¡ É
GM6535
BLOCK DIAGRAM
A
OSCin
12-Bit Programmable
Reference Counter
8
÷4
÷ 25
OSCout
14-Bit Programmable
Auxiliary Reference
Counter
7
B
fR1
C
fR2
D
TRANSMIT
SELECT
MCUCLK
÷3 / ÷4
5
14-Bit Shift
Register
12-Bit Shift
Register
Rx
Phase
Detector
ADin
TxPDout
15
2
CLK
1
Din
3
ENB
4
TxPS/fTX
13
PxPS/fRX
11
MCU Interface Programming
Mode control Register
LD
16
16-Bit Shift Register
f in -T
14
16-Bit Tx Programmable
Counter
RECEIVE
SELECT
Rx
Phase
Detector
16-Bit Shift Register
f in -R
9
16-Bit Rx Programmable
Counter
2
VDD = PIN 12
VSS = PIN 6
RxPDout
10
GM6535
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA =25 ¡ É
)
Symbol
VDD
VOL
VOH
VIL
Characteristic
VDD
Power Supply Voltage
Output Voltage
(Iout = 0)
0 Level
(Vin =VDD or 0)
Input Voltage
(Vout 0.5 V or VDD – 0.5V)
1 Level
0 Level
1 Level
VIH
VOH
IOL
IIL
Output
Current (Vout = 2.2V)
(Vout = 5.0V)
(Vout = 0.3V)
(Vout = 0.5V)
Input Current
(Vin = 0)
Source
Sink
OSCin , fin-T , fin-R
ADin , CLK , Din , ENB
(Vin = VDD –0.5)
IIH
IOZ
Cin
Cout
IDD
(standby)
IDD
OSCin , fin-T , fin-R
ADin , CLK , Din , ENB
Three-Stats Leakage Current (Vout = 0 V or 5.5 V)
Input Capacitance
Output Capacitance
Standby Current
(All Counters are in Power-Down Mode with Oscillator On)
Operating Current (200mVp-p input at fin-T = 60MHz, and fin-R
=60MHz, OSC = 10.24MHz)
3
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
5.5
2.5
5.5
2.5
5.5
Guaranteed Limit
Min
Max
2.5
5.5
0.1
0.1
2.45
5.45
0.75
1.65
1.75
3.85
-0.18
-0.55
0.18
0.55
-30
-66
-1.0
-1.0
30
61
5.0
5.0
¡ ¾
100
8.0
8.0
0.3
1.5
3.0
10
Unit
V
V
V
mA
¥ ì
A
¥ ì
A
nA
pF
pF
mA
mA
GM6535
SWITCHING CHARACTERISTICS (TA = 25¡ É, C L = 50 pF)
Symbol
tTLH
tTHL
tT, tf
tW
fmax
tsu
th
trec
tsul
thl
Characteristic
Figure #
Output Rise Time
1
Output Fall Time
1
Input Rise and Fall Time, OSCin
2
Input Pulse Width, CLK and ENB
3
Input frequency
(Input = Sine Wave @ ≥ 200mVp-p
Setup Time
OSCin
fin-T
fin-R
Data to CLK
ENB to CLK
5
Hold Time, CLK to Data
5
Recovery Time, ENB to CLK
5
Setup Time, ENB to CLK
Hold Time, CLK to ENB
4
4
SWITCHING WAVERORMS
tTLH
ANY
OUTPUT
tTHL
90%
10%
Figure 1.
tf
tr
CLK, OSC in
f in-T, f in-R
VDD
90%
10%
VSS
Figure 2.
tW
ENB, CLK
VDD
50%
VSS
Figure 3.
4
VDD
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
5.5-5.5
2.5
5.5
2.5
5.5
2.5-5.5
2.5-5.5
Min
80
60
100
200
80
40
80
40
80
600
Max
200
100
200
100
5.0
4.0
16
60
60
-
Unit
ns
ns
µs
ns
MHz
ns
ns
ns
ns
ns
GM6535
VDD
CLK
FIRST
CLK
LAST
CLK
VSS
thl
tsul
VDD
ENB
VSS
Figure 4.ENB High During Serial Transfer
VDD
AD in,
D in
50%
VSS
tsu
th
VDD
CLK
50%
LAST
CLK
FIRST
CLK
VSS
trec
tsu
VDD
ENB
50%
VSS
PREVIOUS
DATA LATCHED
Figure 5. ENB Low During Serial Transfer
5
GM6535
fin-T/fin-R
Transmit/Receive Counter Inputs (Pins14, 9)
fin-T and fin-R are inputs to the transmit and the
receive counters, respectively. These signals are
typically driven from the loop VCO and ac-coupled.
The minimum input signal level is 200mVp-p @
60.0MHz.
TxPDout/RxPDout
Transmit/Receive Phase detector Outputs (Pins15,
10)
These are three-state outputs of the transmit and
receive phase detectors for use as loop error signals
(see Figure7 for phase detector output waveforms).
Frequency fV > fR or fV leading: output=negative pulse.
Frequency fV < fR or fV lagging: output = positive pulse.
Frequency fV = fR and phase coincidence: output = high
impedance state.
fR is the divided-down reference frequency at the
phase detector input and fV is the divided-down VCO
frequency at the phase detector input.
LD Lock Detect (Pin16)
The lock detect signal is associated with the transmit
loop. The output at a high level indicates an out-oflock condition (see Figure 7 for the LD output
waveform).
VDD Positive Power Supply (Pin 12)
VDD is the most positive power supply potential
ranging from 2.5 to 5.5V with respect to VSS.
VSS Negative Power Supply (Pin 6)
VSS is the most negative supply potential and is
usually connected to ground.
PIN DESCRIPTIONS
OSCin/OSCout
Reference Oscillator Input/Output (Pins8, 7)
These pins form a reference oscillator when
connected to an external parallel-resonant crystal
frequencies and reference frequencies for cordless
phone applications in various countries. OSCin may
also serve as input for an externally generated
reference signal which is typically ac coupled.
ADin, Din, CLK, ENB
Auxiliary Data In, Data In, Clock, Enable (Pins2, 3,
1, 4)
These four pins provide an MCU serial interface for
programming the reference counter, the transmitchannel counter, and the receive-channel counter. They
also provide various controls of the PLL including the
power saving mode and the programming format.
TxPS/fTx,RxPS/fRx
Transmit Power Save, Receive Power Save (Pins 13,
11)
For a normal application, these output pins provide
the status of the internal power saving mode operation.
If the transmit channels counter circuitry is in power
down mode, TxPS/fTx outputs a high state. If the
receive-channels counter circuitry is in power down
mode, RxPS/fRx is set high. These output can be
applied for controlling the external power switch for
the transmitter and the receiver to save MCU control
pins. In the Tx/Rx channel counter test mode, the
TxPS/fTx and RxPS/fRx pins output the divided value of
the transmit channel counter (fTx) and the receive
channel counter (fRx), respectively. This test mode
operation is controlled by the control register. Details
of the counter test mode are in the Tx/Rx Channel
Counter Test section of this data sheet.
A
B
OSC in
÷ N (12 bits)
f R1
÷4
C
÷25
D
OSC out
÷ M ( 14bits )
Crystal
¡ ÀN Value
fR1 ¡ æB
fR2 ¡ æC
11.150 MHz
446
6.25 MHz
1.0 MHz
11.150 MHz
223
12.5 MHz
10.240 MHz
512
5.0 MHz
12.000 MHz
600
5.0 MHz
Figure 6. Reference Frequencies for Cordless Phone
Applications of Various Countries
6
f R2
GM6535
VH
f R ,REFERENCE
(OSC in ÷ REFERENCE COUNTER)
VL
VH
f v ,FEEDBACK
(F in - T ÷ Tx COUNTER OR
f in -_R ÷ Rx COUNTER)
VL
VH
TxPDout
OR
RxPD out
HIGH IMPEDANCE
LD
V H = High voltage level
V L = Low voltage level
*At this point, when both fR and fv are in phase, the output is forced to near mid supply.
NOTE: The TxPDout and PxPDout generates error pulses during out-of-lock conditions.
When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined
By the low-pass filter capacitor
Figure 7. Phase Detector/Lock Detector Output Waveforms
MCU PROGRAMMING SCHEME
The MCU programming scheme is defined in
two formats controlled by the ENB input. If the
enable signal is high during the serial data transfer,
control register/reference frequency programming is
selected. If the ENB is low, programming of the
transmit and receive counters is selected. During
programming of the transmit and receive counters,
both AD in and D in pins can input the data to the
transmit and receive counters. Both counters data is
clocked into the PLL internal shift register at the
leading edge of the CLK signal. It is not necessary
to
reprogram
the
reference
frequency
counter/control register when using the enable
signal to program the transmit/receive channels.
In programming the control register/reference
frequency scheme, the most significant bit (MSB) of
the programming word identifies whether the input
data is the control word. If the MSB is 1, the input
data is the control word (Figure 8). Also see figure
NO TAG and Table 1 for control register and bit
function. If the MSB is 0, the input data is the
reference frequency (Figure 9).
The reference frequency data word is 32-bit word
containing the 12-bit reference frequency data, the
14-bit auxiliary reference frequency counter
information, the reference frequency selection plus,
the auxiliary reference frequency counter enable
bit(Figure 9).
If the AUX REF ENB bit is high, the 14-bit
auxiliary reference frequency counter provides an
additional phase reference frequency output for the
loops. If AUX REF ENB bit is low, the auxiliary
reference frequency counter is forced into powerdown modes for current saving. (other power down
modes are also provided through the control register
per Table 2 and Figure 8). At the falling edge of the
ENB signal, the data is stored in the registers.
There are two interfacing schemes for the
universal channel mode: the three-pin and four-pin
interfacing schemes. The three-pin interfacing
scheme is suited for use with the MCU SPI (serial
peripheral interface) (Figure 10), while the four-pin
interfacing scheme is commonly used for general
I/O port connection (Figure 11).
For the three-pin interfacing scheme, the
auxiliary data select bit is set to 0. All 32 bits of data,
which define both the 16-bit transmit counter and
the 16-bit receive counter, latch into the PLL
internal register though the data in pins at the
leading edge of CLK. See Figure 12 and 13.
For the four-pin interfacing scheme, the auxiliary
data select bit is set to 1. In this scheme, the 16-bit
transmit counter’s data enters into the ADin pin at
the same time as the 16-bit receive. This
simultaneous entry of the transmit and receive
counters causes the programming period of the fourpin scheme to be half that of the three-pin scheme
(see Figures 14 and 15).
While programming Tx/Rx Channel Counter,
the ENB pin must be pulsed to provide falling edge
to latch the shifted data after the rising edge of the
last clock. Maximum data transfer rate is 500 kbps.
7
GM6535
COMTROL REGISTER IDENTIFIER = 1
COMTROL REGISTER DATA
D in
1
0
TEST
BIT
AUX
Data
Select
REF
OUT
÷3/÷4
TxPD
Enable
RxPD
Enable
MSB
Ref PD
Enable
LSB
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 8. Programming Format of the control Register
Table 1. Control Register Function Bits Description
Test Bit
Aux Data
Select
REF out÷3/÷4
TxPD Enable
RxPD Enable
Ref PD
Enable
Set to 1 for Tx/Rx channel counter test mode
Set to 0 for normal application
Set to 1 for both ADin and Din pins inputting the transmit 16-bits data and receive 16-bits data respectively
Set to 0 for normal application interfacing with MCU serial peripheral interface.
Does not use AD in pin; tie AD in to VSS.
If set to 1, REFout output frequency is equal to OSC out ÷ 3.
If set to 0, REFout output is OSC out ÷ 4.
If set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power-down
mode. TxPS/fTx is set “High”.
If set to 1, the receive counter, receive phase detector, and the associated circuitry is in power-down mode.
RxPS/fTx is set “High”.
If set to 1, both 12-bit and 14-bit reference frequency counters are in power-down mode
Table 2. Control Register Power Down Bits Function
TxPD
Enable
0
0
0
0
1
1
1
1
RxPD
Enable
0
0
1
1
0
0
1
1
REF PD
Enable
0
1
0
1
0
1
0
1
Tx-Channel Counter
Rx-channel Counter
Power Down
Power Down
Power Down
Power Down
Power Down
Power Down
Power Down
Power Down
8
Reference
Frequency Counter
Power Down
Power Down
Power Down
Power Down
GM6535
Reference Frequency
Counter Identifier = 0
D in
0
Reference
Frequency
Select
AUX
Rx-0
Tx-0
REF
ENABLE SELECT SELECT
Select
Aux Reference
Frequency Counter
Divide Ratio
Reference
Frequency
Select
Reference Frequency
Counter Divide Ratio
12-BITS REF FREQ
DATA
fR1
S2
fR1
S1
14-BITS AUX REF FREQ
DATA
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 9. Programming Format of Auxiliary/reference Frequency Counter
D in
MCU Using
Serial Peripheral
Interface Port
Universal PLL
Aux Data Bit = 0
CLK
ENB
Figure 10. MCU Interface Using SPI
ADin
MCU Using
Normal I/O Port
D in
Universal PLL
Aux Data Bit = 1
CLK
ENB
Figure 11. MCU Interface Using Normal I/O Ports with Both Din
And A Din for Faster Programming Time
Control Register
Identifier = 1
Control Register Data
D in
1
0
TEST
BIT
MSB
AUX
Data
Select
REF
OUT
÷3/÷4
TxPD
Enable
RxPD
Enable
AUX DATA SELECT = 0
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 12. Programming Format for control Register (3-Pin Interfacing Scheme)
9
Ref PD
Enable
LSB
GM6535
16-BIT Rx COUNTER
DIVIDE RATIO
16-BIT Tx COUNTER
DIVIDE RATIO
D in
Last
Clock
CLK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 13. Programming Format for Transmit and Receive Counters
(3-Pin Interfacing Scheme)
Control Register
Identifier = 1
Control Register Data
D in
1
0
TEST
BIT
MSB
AUX
Data
Select
REF
OUT
÷3/÷4
TxPD
Enable
RxPD
Enable
AUX DATA SELECT = 1
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 14. Programming Format for control Register
(4-Pin Interfacing Scheme)
AD in
16-BIT Tx COUNTER
DIVIDE RATIO
D in
16-BIT Rx COUNTER
DIVIDE RATIO
Last
Clock
CLK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 15. Programming Format for Transmit and Receive Counters
(4-Pin Interfacing Scheme)
10
Ref PD
Enable
LSB
GM6535
Table 3. Global CT-1 Reference frequency Setting vs Channel Frequencies
Country
U.S.A
Channel Frequency
46/49MHz(10,15,25 Channels)
France
26/41 MHz
Spain
Australia
U.K
New
Zealand
31/41 MHz
30/39 MHz
1.7/47 MHz
1.7/34/40 MHz
fR1
5.0 KHz
6.25 KHz/12.5
KHz
5.0 KHz
5.0 KHz
6.25 KHz
fR2
-
1.0 KHz
6.25 KHz
1.0 KHz
-
frequencies for global CT-1 transmit and receive
channel requirements. Users can select their own
reference frequency by introducing the additional
14-bit auxiliary reference frequency counter.
Again, the 14-bit auxiliary reference frequency
counter can be shut down by the auxiliary reference
enable bit in the reference counter programming
word by setting the bit to 0. At this state, the fR2 is
automatically connected to point C (the ÷ 25 block
output), and fR1 cha be connected to point A or B by
setting the fR1-S1 and fR1-S2 bits in the reference
counter program word. The 14-bit auxiliary
reference frequency counter data will be in Don’t
Care state.
If the 14-bit auxiliary reference frequency counter
is enabled (auxiliary reference enable = 1), the fR2 is
automatically connected to point D (14-bit counter
output), and fR1 can be selected to connect to point
A,B, or C, depending on the bit setting of fR1-S1 and
fR1-S2.
Table 4 and Figure 16 describe the functions of
the auxiliary reference enable bit and the fR1-S1 and
fR1-S2 bits selection.
REFERENCE FREQUENCY SELECTION
AND PROGRAMMING
Figure 16 shows the bit function of the reference
frequency programming word. The user can either
select the fixed reference frequency for all channels
accordingly or provide a specific reference
frequency for a particular channel by using two
reference frequency counters (e.g., for an
application in France, the base set transmit channel
common fixed reference frequency is 6.25 KHz or
12.5 KHz). (See Table 3 Figure 6 for reference
frequencies for various countries.)
However, transmit channels 6, 8, and 14 can be
set to 25 KHz, and channel 8 reference frequency
can be set to 50 KHz. But this reference frequency
may not be applied to the receiving side; therefore,
the receiving side reference frequency must be
generated by another reference frequency counter.
The higher the reference frequency, the better the
phase noise performance and faster the lock time,
but the PLL consumes more current if both
reference frequency counters are in operation. In
general, the 12-bit reference frequency counter plus
the ÷ 4 and ÷ 25 module can offer all the reference
Table 4. Bit Function and the Reference Frequency Selection Bit Setting of the
Reference Frequency Counter Programming Word
N/A Not Applicable
fR1
fR1
AUX REF
Auxiliary Reference Frequency
Module
fR1
Routin
S2
Enable
Counter Mode
Select
S1
g
N/A
14-Bit Auxiliary Reference Frequency
fR2→ C
0
0
Counter Disable
fR1→ A
0
1
0
1
0
fR1→ B
1
1
N/A
14-Bit Auxiliary Reference Frequency
N/A
fR2→ D
0
0
Counter Disable
fR1→ A
1
0
1
1
0
fR1→ B
1
1
fR1→ C
11
GM6535
f R1
12-Bits Programmable
Reference Counter
OSC in
÷4
÷25
f R2
14-Bits Programmable
Auxiliary Reference
Counter
OSC out
Tx
Phase
Detector
1
Maximum
Crystal Frequency
16.0 MHZ
0
Tx-0
SELECT
LD
1
0
Reffrequency
Counter
Identifier = 0
D in
0
Reference
Frequency
Select
AUX
REF
Enable
Select
TxPDout
Tx-0
Select
Rx-0
Select
Reference
Frequency
Counter
Reference
Frequency
Select
12-BITS REF FREQ
DATA
fR1
S1
fR1
S2
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 16. Reference Frequency Counter/selection Programming Mode
12
Rx-0
SELECT
Rx
Phase
Detector
Auxiliary Reference
Frequency Counter
14-BITS AUX REF FREQ
DATA
RxPDout
GM6535
POWER SAVING OPERATION
This PLL has a programmable power-saving
scheme. The transmit counter, receive counter and
the reference frequency counter can be powered
down individually by setting the TxPD enable,
RxPD enable and Ref PD enable bits of the control
register. The functions of the power down control
bits are explained in Table 2 and the programming
format is in Figure 8.
The output pins TxPS/fTx and RxPS/fRx output the
status of the internal power saving setting. If the bit
TxPD enable is set high (transmit counter is set to
power-down mode), then the TxPS/fTx pin will also
output a high state. This TxPS/fTx output can control
an external power switch to switch off the
transmitter, as shown in Figure 17. This scheme
can be applied to the RxPS/fRx output to control the
receiver power saving operation as required.
UNIVERSAL DUAL PLL
Power Supply
VDD
TxPS/fTx
Q
POWER SWITCH
FOR TRANSMITTER
Tx Power-Down
Enable Flag
Tx Divider chain Counter, Phase Detector
VDD
TX
Power
AMP
RxPS/fRx
Q
Rx Divider chain Counter, Phase Detector
To control
The Receiver
Power Switch
Figure 17. TxPS/fTx and RxPS/fRx Outputs to Control Power Switches
of the Transmitter and Receiver
13
Rx Power-Down
Enable Flag
GM6535
TX/RX CHANNEL COUNTER TEST
channel counter multiplex out to TxPS/fTx and
RxPS/fRx respectively. The user can verify the
divided-down output waveform associated with the
RF input level in the PLL circuitry implementation
(Figure 18).
In normal applications, the TxPS/fTx and the
RxPS/fRx output pins indicate the power saving
mode status. However, the user can examine the Tx
and Rx channel counter outputs by setting the Test
bit in the control register to 1. The final value of
the transmit-channel counter and the receive-
16-BIT Tx PROGAMMABLE
CHANNELS COUNTER
fin-T
f Tx
TxPS/f Tx
TxPS
IF TEST BIT TO 1, THE f Tx
AND f Rx ARE MIXED OUT AT PINS
TxPS/f Tx AND RxPS/f Rx
RESPECTIVEY, FOR Rx/Tx
CHANNEL COUNTER TEST.
CONTROL REGISTER
IDENTIFIER = 1
CONTROL REGISTER
D in
1
TEST
BIT
0
AUX
DATA
SELECT
f in-R
TxPS/f Rx
REF
OUT
÷3/÷4
TxPD
RxPD
Ref PD
ENABLE ENABLE ENABLE
16-BIT Rx PROGRAMMABLE
CHANNELS COUNTER
fRx
RxPS
Figure 18. RF Buffer Sensitivity
14
GM6535
Table 5. France CT-1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
26.4875
26.4750
26.4625
26.4500
26.4375
26.4250
26.4125
26.4000
26.3875
26.3750
26.3625
26.3500
26.3375
26.3250
26.3125
Tx Counter
Value
(Ref. Freq.=
6.25 KHz)
4238
4236
4234
4232
4230
4228
4226
4224
4222
4220
4218
4216
4214
4212
4210
fin-R Input
Frequency(MHz)
[1st IF = 10.7MHz]
Rx Counter Value
(Ref. Freq. =
6.25 KHz)
30.7875
30.7750
30.7625
30.7500
30.7375
30.7250
30.7125
30.7000
30.6875
30.6750
30.6625
30.6500
30.6375
30.6250
30.6125
4926
4924
4922
4920
4918
4916
4914
4912
4910
4908
4906
4904
4902
4900
4898
Table 6. France CT-1 Hand Set Frequency
Channel
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Tx-Channel
Frequency
(MHz)
41.4875
41.4750
41.4625
41.4500
41.4375
41.4250
41.4125
41.4000
41.3875
41.3750
41.3625
41.3500
41.3375
41.3250
41.3125
Tx Counter Value
(Ref. Freq. =
6.25 KHz)
6638
6636
6634
6632
6630
6628
6626
6624
6622
6620
6618
6616
6614
6612
6610
15
fin-R Input
Frequency(MHz)
[1st IF = 10.7MHz]
37.1875
37.1750
37.1625
37.1500
37.1375
37.1250
37.1125
37.1000
37.0875
37.0750
37.0625
37.0500
37.0375
37.0250
37.0125
Rx Counter Value
(Ref. Freq. =
6.25 KHz)
5950
5948
5946
5944
5942
5940
5938
5936
5934
5932
5930
5928
5926
5924
5922
GM6535
Table 7. Spain CT – 1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. = 5.00KHz)
fin-R Input
Frequency (MHz)
[1st IF= 10.695 MHz]
Rx counter value
(Ref. Freq.=5.00KHz)
1
31.0250
6205
29.2300
5846
2
31.0500
6210
29.2550
5851
3
31.0750
6215
29.2800
5856
4
31.1000
6220
29.3050
5861
5
31.1250
6225
29.3300
5866
6
31.1500
6230
29.3550
5871
7
31.1750
6235
29.3800
5876
8
31.2000
6240
29.4050
5881
9
31.2500
6250
29.4550
5891
10
31.2750
6255
29.4800
5896
11
31.3000
6260
29.5050
5901
12
31.3250
6265
29.5300
5906
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. = 5.00KHz)
fin-R Input
Frequency (MHz)
[1st IF= 10.7 MHz]
Rx counter value
(Ref. Freq.=5.00KHz)
1
39.9250
7985
20.3300
4066
2
39.9500
7990
20.3550
4071
3
39.9750
7995
20.3800
4076
4
40.0000
8000
20.4050
4081
5
40.0250
8005
20.4300
4086
6
40.0500
8010
20.4550
4091
7
40.0750
8015
20.4800
4096
8
40.1000
8020
20.5050
4101
9
40.1500
8030
20.5550
4111
10
40.1750
8035
20.5800
4116
11
40.2000
8040
20.6050
4121
12
40.2250
8045
20.6300
4126
Table 8. Spain CT – 1 Hand Set Frequency
16
GM6535
Table 9. New Zealand CT – 1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
fin-R Input
Frequency (MHz)
[1st IF= 10.7 MHz]
Rx counter value
(Ref. Freq.=6.25KHz)
1
1.7820
1782
29.7625
4762
2
1.7620
1762
29.7500
4760
3
1.7420
1742
29.7375
4758
4
1.7220
1722
29.7250
4756
5
1.7020
1702
29.7125
4754
6
34.3500
5496
29.7000
4752
7
34.3625
5498
29.6875
4750
8
34.3750
5500
Ref. Freq.
29.6750
4748
9
34.3875
5502
= 6.25KHz
29.6625
4746
10
34.4000
5504
29.6500
4744
Tx Counter Value
Ref. Freq.
= 1.0KHz
Table 10. New Zealand CT – 1 Hand Set Frequency
1
Tx-Channel
Frequency
(MHz)
40.4625
6474
2.2370
2237
2
40.4500
6472
2.2170
2217
3
40.4375
6470
2.1970
Ref. Freq.
2197
Ref. Freq.
4
40.4250
6468
2.1770
=45.5KHz
2177
=1.0KHz
5
40.4125
6466
2.1570
2157
6
40.4000
6464
23.6500
3784
7
40.3875
6462
2.6625
8
40.3750
6460
23.6750
Ref. Freq.
3788
Ref. Freq.
9
40.3625
6458
23.6875
=10.7KHz
3790
=6.25KHz
10
40.3500
6456
23.7000
Channel
Number
Tx Counter Value
(Ref. Freq. = 6.25KHz)
17
fin-R Input
Frequency (MHz)
Rx counter value
3786
3792
GM6535
Table 11. Australia CT – 1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. = 5.00KHz)
fin-R Input
Frequency (MHz)
[1st IF= 10.695 MHz]
Rx counter value
(Ref. Freq.=5.00KHz)
1
30.0750
6015
29.0800
5816
2
30.1250
6025
29.1300
5826
3
30.1750
6035
29.1800
5836
4
30.2250
6045
29.2300
5846
5
30.2750
6055
29.2800
5856
6
30.1000
6020
29.1050
5821
7
30.1500
6030
29.1550
5831
8
30.2000
6040
29.2050
5841
9
30.2500
6050
29.2550
5851
10
30.3000
6060
29.3050
5861
Table 12. Australia CT – 1 Hand Set Frequency
1
Tx-Channel
Frequency
(MHz)
39.7750
7955
Fin-R Input
Frequency (MHz)
[1st IF= 10.7 MHz]
19.3800
2
38.8250
7965
19.4300
3886
3
37.8750
7975
19.4800
3896
4
36.9250
7985
19.5300
3906
5
35.9750
7995
19.5800
3916
6
39.8000
7960
19.4050
3881
7
39.8500
7970
19.4550
3891
8
39.9000
7980
19.5050.
3901
9
39.9500
7990
19.5550
3911
10
40.0000
8000
19.6050
3921
Channel
Number
Tx Counter Value
(Ref. Freq. = 5.00KHz)
18
Rx counter value
(Ref. Freq.=5.00KHz)
3876
GM6535
Table 13. U.K. CT – 1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. = 1.00KHz)
fin-R Input
Frequency (MHz)
[1st IF= 10.7 MHz]
Rx counter value
(Ref. Freq.=6.25KHz)
1
1.6420
1642
36.75625
5881
2
1.6620
1662
36.76875
5883
3
1.6820
1682
36.78125
5885
4
1.7020
1702
36.79375
5887
5
1.7220
1722
36.80625
5889
6
1.7420
1742
36.81875
5891
7
1.7620
1762
36.83125
5893
8
1.7820
1782
36.84375
5895
Table 14. U.K. CT – 1 Hand Set Frequency
1
Tx-Channel
Frequency
(MHz)
47.45625
7593
fin-R Input
Frequency (MHz)
[1st IF= 45.5 KHz]
2.097
2
47.46875
7595
2.117
2117
3
47.48125
7597
2.137
2137
4
47.49375
7599
2.157
2157
5
47.50625
7601
2.177
2177
6
47.51875
7603
2.197
2197
7
47.53125
7605
2.217
2217
8
47.54375
7607
2.237
2237
Channel
Number
Tx Counter Value
(Ref. Freq. = 0.25KHz)
19
Rx counter value
(Ref. Freq.=1.00KHz)
2097
GM6535
Table 15. U.S.A. CT-1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.695 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
46.610
9322
38.975
7795
2
46.630
9326
38.150
7830
3
46.670
9334
38.165
7833
4
46.710
9342
39.075
7815
5
46.730
9346
39.180
7836
6
46.770
9354
39.135
7827
7
46.830
9366
39.195
7839
8
46.870
9374
39.235
7847
9
46.930
9386
39.295
7859
10
46.970
9394
39.275
7855
Table 16. U.S.A. CT-1 Hand Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
49.670
9934
35.915
7183
2
49.845
9969
35.935
7187
3
49.860
9972
35.975
7195
4
49.770
9954
36.015
7203
5
49.875
9975
36.035
7207
6
49.830
9966
36.075
7215
7
49.890
9978
36.135
7227
8
49.930
9986
36.175
7235
9
49.990
9998
36.235
7247
10
49.970
9994
36.275
7255
20
GM6535
Table 17. U.S.A. CT-1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
43.72
8744
38.06
7612
2
43.74
8748
38.14
7628
3
43.82
8764
38.16
7632
4
43.84
8768
38.22
7644
5
43.92
8784
38.32
7664
6
43.96
8788
38.38
7678
7
44.12
8824
38.40
7680
8
44.16
8832
38.46
7692
9
44.18
8836
38.50
770
10
44.20
8840
38.54
7708
11
44.32
8864
38.58
7716
12
44.36
8872
38.66
7732
13
44.40
8880
38.70
7740
14
44.46
8892
38.76
7752
15
44.48
8896
38.80
7760
16
46.61
9322
38.97
7794
17
46.63
9326
39.145
7829
18
46.67
9331
39.16
7832
19
46.71
9342
39.07
7814
20
46.73
9346
39.175
7835
21
46.77
9354
39.13
7826
22
46.83
9366
39.19
7838
23
46.87
9374
39.23
7846
24
46.93
9386
39.29
7858
25
46.97
9394
39.27
7854
21
GM6535
Table 18 U.S.A. CT-1 Hand Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
48.76
9752
33.02
6604
2
48.84
9768
33.04
6608
3
48.86
9772
33.12
6624
4
48.92
9748
33.14
6628
5
49.02
9804
33.22
6644
6
49.08
9816
33.26
6652
7
49.10
9820
33.42
6684
8
49.16
9832
33.46
6692
9
49.20
9840
33.48
6696
10
49.24
9848
33.50
6700
11
49.28
9856
33.62
6724
12
49.36
9872
33.66
6732
13
49.40
9880
33.70
6740
14
49.46
9892
33.76
6752
15
49.50
9900
33.78
6756
16
49.67
9934
33.91
7182
17
49.845
9969
33.93
7186
18
49.88
9972
33.97
7194
19
49.77
9954
36.01
7202
20
49.875
9975
36.03
7206
21
49.83
9966
36.07
7214
22
449.89
9978
36.13
7226
23
49.93
9986
36.17
7234
24
49.99
9998
36.23
7246
25
49.97
9994
36.27
7254
22
GM6535
Table 19 Korea CT-1 Base Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.695 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
46.610
9322
38.975
7795
2
46.630
9326
38.150
7830
3
46.670
9334
38.165
7833
4
46.710
9342
39.075
7815
5
46.730
9346
39.180
7836
6
46.770
9354
39.135
7827
7
46.830
9366
39.195
7839
8
46.870
9374
39.235
7847
9
46.930
9386
39.295
7859
10
46.970
9394
39.275
7855
11
46.510
9302
39.000
7800
12
46.530
9306
39.015
7803
13
46.550
9310
39.030
7806
14
46.570
9314
39.045
7809
15
46.590
9318
39.060
7812
Table 20. Korea CT-1 Hand Set Frequency
Channel
Number
Tx-Channel
Frequency
(MHz)
Tx Counter Value
(Ref.Freq. =
5.00 KHz)
fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]
Rx Counter Value
(Ref. Freq. =
5.00 KHz)
1
49.670
9934
35.915
7183
2
49.845
9969
35.935
7187
3
49.860
9972
35.975
7195
4
49.770
9954
36.015
7203
5
49.875
9975
36.035
7207
6
49.830
9966
36.075
7215
7
49.890
9978
36.135
7227
8
49.930
9986
36.175
7235
9
49.990
9998
36.235
7247
10
49.970
9994
36.275
7255
11
49.695
9939
35.815
7163
12
49.710
9942
35.835
7167
13
49.725
9945
35.855
7171
14
49.740
9948
35.875
7175
15
49.755
9951
35.895
7179
23