TI SN74AUP3G06DCUR

SN74AUP3G06
www.ti.com
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
LOW-POWER TRIPLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
Check for Samples: SN74AUP3G06
FEATURES
1
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 μA Maximum)
Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Wide Operating VCC Range of 0.8 V to 3.6 V
DCU PACKAGE
(TOP VIEW)
1A
3Y
2A
GND
1
2
7
3
6
4
1A
3Y
2A
GND
1Y
3A
2Y
5
•
•
•
•
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 4.3 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
1
8
2
7
3
6
4
5
VCC
1Y
3A
2Y
YFP PACKAGE
(TOP VIEW)
RSE PACKAGE
(TOP VIEW)
DQE PACKAGE
(TOP VIEW)
VCC
8
•
•
VCC
1Y
8
1
3A
2
2Y
3
1A
7
4
6
3Y
5
2A
1A
3Y
2A
GND
A1
1 8
A2
B1
2 7
B2
C1
3 6
C2
D1
45
D2
VCC
1Y
3A
2Y
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
100%
60%
3.3-V
Logic(A)
40%
Voltage (V)
40%
Switching Characteristics
at 25 MHz(A)
80%
80%
60%
Dynamic-Power Consumption
(pF)
100%
3.3-V
(A)
Logic
20%
20%
AUP
AUP
0%
(A)
0%
AUP
Single, dual, and triple gates
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Input
0
5
(A)
Figure 1. AUP – The Lowest-Power Family
Output
10
15
20 25 30
Time (ns)
35
40
45
SN74AUP3Gxx data at CL = 15 pF.
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN74AUP3G06
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
www.ti.com
The output of SN74AUP3G06 is open drain and can be connected to other open-drain outputs to implement
active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
–40°C to 85°C
(1)
(2)
(3)
ORDERABLE
PART NUMBER
PACKAGE (2)
TA
TOP-SIDE
MARKING (3)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000
SN74AUP3G06YFPR
__HT_
uQFN – DQE
Reel of 5000
SN74AUP3G06DQER
TV
QFN – RSE
Reel of 5000
SN74AUP3G06RSER
PREVIEW
SSOP – DCU
Reel of 3000
SN74AUP3G06DCUR
H06_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(Each Inverter)
INPUT
A
OUTPUT
Y
H
L
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
7
1A
1Y
3
5
2A
2Y
6
2
3A
3Y
Pin numbers shown are for the DCU and DQE packages.
2
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Product Folder Link(s): SN74AUP3G06
SN74AUP3G06
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SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Output voltage range in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
DCU package
220
DQE package
261
RSE package
253
YFP package
(1)
(2)
(3)
V
°C/W
132
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP3G06
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
MIN
MAX
0.8
3.6
UNIT
V
VCC
0.65 × VCC
V
1.6
2
VCC = 0.8 V
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VI
Input voltage
0
3.6
VO
Output voltage
0
VCC
V
VCC = 0.8 V
20
μA
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
IOL
Low-level output current
0.9
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
V
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AUP3G06
www.ti.com
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
VCC
TA = 25°C
MIN
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
IOL = 20 μA
0.8 V to 3.6 V
0.1
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
IOL = 2.3 mA
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
3V
IOL = 4 mA
UNIT
V
0 V to 3.6 V
0.1
0.5
μA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
μA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
μA
ICC
VI = GND or
(VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
μA
ΔICC
VI = VCC – 0.6 V (1),
IO = 0
3.3 V
40
50
μA
II
A or B input VI = GND to 3.6 V
VCI i= VCC or GND
Co
(1)
VO = GND
0V
1.5
3.6 V
1.5
0V
pF
3
pF
One input at VCC – 0.6 V, other input at VCC or GND
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SN74AUP3G06
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
12.4
1.2 V ± 0.1 V
2.7
12
9.9
2
12.8
1.5 V ± 0.1 V
2.1
3.5
6.2
1.5
7.6
1.8 V ± 0.15 V
2.1
3.1
4.7
1.2
5.9
2.5 V ± 0.2 V
1.4
2.2
3.2
1
3.9
3.3 V ± 0.3 V
1.3
2.2
3.3
0.8
3.6
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
15.1
1.2 V ± 0.1 V
3.6
12
11.2
2.7
14.1
1.5 V ± 0.1 V
2.9
4.3
7
2.2
8.6
1.8 V ± 0.15 V
2.7
3.9
5.4
1.8
6.7
2.5 V ± 0.2 V
2.1
2.9
3.8
1.4
4.5
3.3 V ± 0.3 V
1.7
3
4.5
1.2
4.9
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
17.4
1.2 V ± 0.1 V
4.9
12
12.2
3.4
15.2
1.5 V ± 0.1 V
3.5
5
7.7
2.7
9.4
1.8 V ± 0.15 V
3.2
4.8
6.6
2.2
7.3
2.5 V ± 0.2 V
2.5
3.5
4.5
1.7
5.1
3.3 V ± 0.3 V
2
3.8
6
1.5
6.5
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
6
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
TYP
MAX
MIN
MAX
25.3
1.2 V ± 0.1 V
7.6
12
16
5.6
19.3
1.5 V ± 0.1 V
3.5
7.6
12.3
3.0
13.0
1.8 V ± 0.15 V
4.8
7.4
10.7
3.6
11
2.5 V ± 0.2 V
3.7
5.4
7.1
2.8
7.8
3.3 V ± 0.3 V
3.2
6.5
10.5
2.5
10.8
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UNIT
ns
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP3G06
SN74AUP3G06
www.ti.com
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.1
3.3 V ± 0.3 V
4.3
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UNIT
pF
7
SN74AUP3G06
SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
VCC
Timing Input
0V
tPLH
tPHL
tsu
VOH
Output
VCC/2
VM
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for
propagation delays tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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SCES775A – DECEMBER 2009 – REVISED DECEMBER 2009
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 x V CC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 x V CC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 xV CC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + V ∆
VOL
tPHZ
VCC/2
VOH - V ∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPLH and tPHL are the same as tpd.
G.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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9
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP3G06DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP3G06DQER
ACTIVE
X2SON
DQE
8
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP3G06YFPR
PREVIEW
DSBGA
YFP
8
3000
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
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Addendum-Page 1
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Amplifiers
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amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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Digital Control
Medical
Military
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Telephony
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Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
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