ETC ES1371

ENSONIQ Proprietary Information
ENSONIQ AudioPCI™ 97
ES1371
Specification
1.
INTRODUCTION
AudioPCI 97 is the new ENSONIQ AC97 digital controller which provides the next
generation of audio performance to the PC market. AudioPCI 97 is a 5.0 Volt PCI bus
compatible device that enables the ENSONIQ SoundScape PCI solution. AudioPCI 97
along with an AC97 CODEC offer the next generation of audio performance in a PC
while maintaining full legacy compatibility without old ISA bus solutions. Some of the
capabilities of AudioPCI 97 are:
• SoundScape WaveTable synthesizer .
• Full DOS Game Compatibility
• Multiple sample rate support
• PCI Bus Master for fast DMA
• Sounds are stored in Main memory.
• Access to Ensoniq’s World Famous Sound Library of over 4000 Sounds
• 3 Stereo inputs and 3 mono inputs can be mixed into the output stream.
• Direct I/O space access of the control registers.
• 100 Pin PQFP or TQFP
• External I2S input
• No ISA bus pins required
• Fully Compliant with PC97 Power Management specification
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2.
DESIGN CONCEPT
AudioPCI 97 is a PCI bus master and slave device that is best understood by looking at the device as four
interactive subsystems: the PCI interface, DMA control, LEGACY functions, and the CODEC.
2.1.
PCI Interface
The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache
buffers full and empties the A/D Converter (or I2S input) buffer to main memory as required.
The fundamental concept of AudioPCI 97 is that the PCI interface controller has a sufficiently large internal
(on-chip) memory cache to meet the memory bandwidth requirements. There is a Sound Cache block of 64
bytes for each of the audio channels. It is the responsibility of the DMA control and the software to keep
the buffers full.
All system control registers are accessed via I/O on the PCI bus. AudioPCI 97 uses 16 Long Words in the
I/O space for control registers. All registers are read as Long Words. All registers are written in byte word
or longword format.
2.2.
DMA Control
AudioPCI 97 essentially implements a 3 channel DMA controller. These virtual DMA channels are
implemented via the CCB, PCI and Serial interface modules. The Serial interface signals the CCB module
when a cache transfer is required (playback or record). The CCB module then signals the PCI module to
initiate a bus master data transfer. At this point the CCB and PCI modules will control the data transfer
between host system memory and the AudioPCI 97 internal cache.
2.3.
LEGACY
The LEGACY subsystem is the circuitry required to perform SoundBlaster, OPL-FM and MPU-401
emulation. Functionally AudioPCI 97 traps on access of the SoundBlaster registers and then issues the
appropriate IRQ or SERR command on the PCI bus. AudioPCI 97 handles the Legacy DMA function in a
similar fashion. The exact functionality of the block cannot be fully disclosed at this time due to pending
patent protection for the application of this technique.
2.4.
CODEC
The Codec controller supports any AC97 compliant CODEC. The functionality of the A/D and D/A
sections are similar to those found in other standard CODECs. The A/D portion of the Codec is handled as
an independent asynchronous event with a DMA buffer control structure. Each time the A/D FIFO is filled,
a Bus Master request occurs and the FIFO is transferred to main memory.
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BLOCK DIAGRAM
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
CLK
RST#
INTA#
PCI Interface Block
Legacy
GPIO[3:0]
Chip Select
& IRQ
& GPIO
XTALi
XTALo
Clock Generation
Host Interface
Control
Host Data Bus
Ext IRQ
Host Address Bus
Cache
Control Block
High Speed
Bus Mux
Cache
Memory
Joystick
UART
MIDI Out
MIDI In
SRC CACHE
RAM
Sample Rate
Converter
AC97 CODEC
Controller
Memory Address Bus
Joy[7:0]
Memory Data Bus
3.
AC LINK:
ac97_sync
sdata_out
bclk
sdata_in
Serial Control
I2S
[bclk,lrclk,data]
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4.
THE SYSTEM Components
4.1.
PCI Interface/LEGACY
The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache
buffers full and empties the A/D Converter (or I2S input) buffer to main memory as required.
All system control registers are accessed via I/O on the PCI bus. AudioPCI 97 uses 16 Long Words in the
I/O space for control registers. All registers are read as Long Words. All registers are written in byte word
or longword format.
The PCI block also includes the functions necessary to provide legacy mode support. This block generates
IRQ or SERR# at a specified ADLib access, SoundBlaster access, DMA controller access, IRQ (PIC)
controllers access, Microsoft WSS access, or Soundscape access.
4.2.
Bus Master Cache Control (CCB)
This block controls the transfer of data between the PCI memory and the internal memory. The Serial block
signals when a cache fill/transfer is required in the three memory buffers. The CCB calculates the PCI
address from the frame data and issues a command to the PCI interface. When the PCI interface signals that
the data is available the CCB channels the data to the proper place in memory. This block is functionally
equivalent to a 3 channel DMA controller.
4.3.
Serial Interface
This block performs a parallel transfer to/from the internal memory for the record and playback channels
respectfully. The record channel source can be either the I2S inputs or the AC97 CODEC ADC serial input
signal. This block also signals the CCB block when a cache fill/transfer is required.
4.4.
Host Interface
This block arbitrates a PCI access to the internal memory. When the data transfer is complete, it responds
with an acknowledge to the PCI interface block. This block provides direct access to the internal memory. It
can be used to access the playback/record channels cache, the UART FIFO or the CCB registers.
4.5.
CODEC Controller
This block reads/writes configuration data from the host bus to the AC97 CODEC using the serial protocol
of the AC97 CODEC. This block also merges the mixed playback channel data into the AC97 CODEC’s
serial data input, and it retrieves the record channel data from the AC97 CODEC’s serial data output.
4.6.
IRQ & Chip Select Block
The functions for this block are:
1. Decode the internal address bus to generate chip selects to each block.
2. Contains internal registers whose outputs are control bits used by internal blocks for control/selection.
3. Summarizes all system IRQ’s (UART, CODEC, etc.) to generate a single AudioPCI 97 IRQ to the host.
This also includes the playback and record DMA channels. Any IRQ masking is performed within the
individual blocks except for the CCB block interrupt.
4.7.
Joystick
This block contains the logic required to implement the joystick interface for AudioPCI 97.
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4.8.
UART
This block includes both the transmitter and receiver for the AudioPCI 97 MIDI interface. The UART
controller also implements an eight byte FIFO in the internal memory. This FIFO is then accessed through
the HOST interface block.
4.9.
Sample Rate Converter
This block receives or sends samples from/to the serial interface block for the playback/record channels.
The Sample Rate converter block converts two variable input rate playback channels to one fixed rate
(48Khz) output channel. It also takes one fixed input rate (48Khz) record channel and converts it to a
variable rate output channel. The channels are programmed by writing several ram locations that are a
function of the input and output rates. The Sample Rate Converter block has it’s own memory section. The
Sample Rate Converter memory is accessible only by the Sample Rate Converter block.
Sample Rate Converter Flow
Synth & Wave
Channels
4k-48k Stereo
N
FIR
Filter
Linear
Interp
olate
Codec 48K
Record Data
4k-48k
Codec 48K
The first stage consists of expanding the number of input samples by an integer number (N), up to a
maximum of 16, and filling in between the samples with zeros. Then the new samples are filtered by a long
1/32 band FIR filter. In practice, the zeros are not multiplied with their corresponding FIR coefficients.
The input samples are fed into an input FIFO and the hardware figures out which FIR coefficient
corresponds to each FIFO sample. The starting coefficient and the spacing between successive coefficients
are calculated by aligning the FIR filter with a virtual FIFO which is the expanded version of the real FIFO.
The coefficient positions also depend on the third stage in the block diagram, the linear interpolator. This
interpolator uses frequency and accumulator registers to interpolate between 2 samples.
4.10. Memory Bus
This pathway is used exclusively to transfer data between the internal sound cache memory and the various
sub-systems. The access priority for this bus is (highest to lowest):
Cache Control block
Host Interface
UART Interface
Serial Interface
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4.11. Internal Memory
There are two separate sections of memory in AudioPCI 97. One section is allocated as a cache for the
playback and record channels and also as a FIFO for the UART. The other section is allocated to the
Sample Rate Converter module and is used as a cache for sample rate conversion and also as control
register space for the playback and record channels in the sample rate converter.
The internal memory for the sound cache in AudioPCI 97 is organized as 4 blocks of 64 bytes each. Each
block is divided into 4 pages of 16 bytes each (4 longwords). Memory can be accessed as longwords only.
In order to access a specific page of memory the memory page register must first be setup for the specific
page to be accessed. The first three blocks of memory contain the 3 circular buffers for the 2 playback
channels and the record channel. The last block contains the frame information for the playback and record
channels and also includes the UART FIFO. The memory block and page organization is shown below :
Block
Page
0 - DAC 1
1 - DAC2
2 - ADC
3 - Frame/UART
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Higher
Address
DAC1 sample bytes 15 - 0
Lower half buffer
DAC1 sample bytes 31 - 16
DAC1 sample bytes 47 - 32 Upper half buffer
DAC1 sample bytes 63 - 48
DAC2 sample bytes 15 - 0
Lower half buffer
DAC2 sample bytes 31 - 16
DAC2 sample bytes 47 - 32 Upper half buffer
DAC2 sample bytes 63 - 48
ADC sample bytes 15 - 0
Lower half buffer
ADC sample bytes 31 - 16
ADC sample bytes 47 - 32 Upper half buffer
ADC sample bytes 63 - 48
DAC1, DAC2 frame information (see register descriptions)
ADC frame information (plus 2 open longwords)
UART fifo (only bits 8 - 0 of each longword are used)
UART fifo
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Lower
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The internal memory organization for the Sample Rate Converter in AudioPCI 97 is shown below. The
memory is accessed through the Sample Rate Converter interface register located at address 10H.
Loc(hex)
0
PLAY/REC Registers
Fifo Ram 128x16
15 14 13 12 11 10 9
S
TRUNC_START
0 M
F
PLAY 1 Left
8
7
6
5
4
3
N
2
1
0
HSTART
10
PLAY 1 Right
VF.I
1
20
0
AC.I
2 0
AC.F
3 0
VF.F
PLAY 2 Left
30
PLAY 2 Right
Volume Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
40
6c
0
REC.N
(copy)
0
Rec Right 6d
0
REC.N
(copy)
0
Rec Left
REC Left
56
6e
6f
Unused
Unused
REC Right
Play 1 L
6c
70
74
78
7c
Volume Reg Rec
PLAY 1 Regs
PLAY 2 Regs
REC Regs
Volume Reg Play
Play 1 R
Play 2 L
Play 2 R
S
7c G
N
S
7d G
N
S
7e G
N
S
7f G
N
P1.VOL.I
P1.VOL.F
P1.VOL.I
P1.VOL.F
P2.VOL.I
P2.VOL.F
P2.VOL.I
P2.VOL.F
Sample Rate Converter Interface
31 30 29 28 27 26 25 24 23
B
RAM ADDR
W U
E S
Y
22
D
I
S
21
D
P
1
20
D
P
2
19 18 17 16 15 14 13 12 11 10 9 8 7 6
D
R unused
RAM DATA
E
C
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5.
PCI Data Transfers
The internal control registers of the AudioPCI 97 Chip and the AC97 CODEC are accessed via 16 Long
Words in PCI direct I/O space. These registers are always read as 32 bit longwords but can be written as
bytes, words or longwords.
PCI bus mastering is used to transfer audio data between system memory and AudioPCI 97 internal
memory. The internal Cache Control Block and the PCI Interface control these transfers. Only burst
read/write transfers are allowed. All data transfers are 8 Long Word burst transfers.
5.1.
Audio Read Transfers
The CCB requests a read data transfer from the PCI interface block (PCIB). The PCIB arbitrates for the
PCI bus and initiates an 8 long word read starting at the system address specified by the CCB in the read
request. When the data is acquired, the PCIB signals the CCB to begin moving the data to internal memory.
The CCB performs any byte alignment required and writes the data to the appropriate buffer in the internal
memory. The CCB will complete the current transfer request and then proceed to the next highest priority
request.
5.2.
Audio Write Transfers
The CCB will first write up to 8 long words into the intermediate PCI buffer. The CCB will then request a
write transfer from the PCIB to main memory and specify the starting address of the transfer. The PCIB
arbitrates for the PCI bus and transfers 8 Long Words into system memory. Eight Long words will always
be transferred during this operation.
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6.
PCI CONFIGURATION SPACE
The following information is the PCI configuration space for the AudioPCI 97 chip. All bits not specifically
mentioned below are zero and read only.
Vendor ID
Address 00H
Addressable as word
Power on reset value 1274H
Bit(s) R/W Name
15:0
R
VENDOR ID
Configuration Space
Data Value
1274H
Device ID
Address 02H
Addressable as word
Power on reset value 1371H
Bit(s) R/W Name
15:0
R
DEVICE ID
Configuration Space
Data Value
1371H
Command
Address 04H
Addressable as word
Power on reset value 0000H
Bit(s) R/W Name
15:10 R
RESERVED
9
R
ZERO
8
R/W
SERR#_EN
7:3
R
ZERO
2
R/W
PCI_MASTER
1
R
ZERO
0
R/W
IO_ACCESS
Configuration Space
Data Value
These bits are reserved and always read back as zeros.
This command bit is not implemented and always reads back as
zero.
Enable bit for SERR# driver.
0 - SERR# driver disabled.
1 - SERR# driver enabled.
These command bits are not implemented and always read back as
zeros.
PCI Bus Master enable bit. This bit controls a device’s ability to act
as a PCI Bus Master. The ES1371 can act as a bus master.
0 - PCI Bus Mastering disabled.
1 - PCI Bus Mastering enabled.
This command bit is not implemented and always reads back as
zero.
I/O Space access bit. This bit controls whether the device can be
accessed in I/O space. The ES1371 is accessed in this space.
0 - I/O Space access disabled.
1 - I/O space access enabled.
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Status
Address 06H
Addressable as word
Power on reset value x610H
Bit(s) R/W Name
15
R
PARITY
14
R
SERR#
13
R
MASTER-ABORT
12
R
TARGET-ABORT
11
10:9
R
R
ZERO
DEVSEL#
8:5
R
ZERO
4
R
CAPABILITIES
3:0
R
ZERO
Configuration Space
Data Value
Parity Error status bit.
0 - No Parity error.
1 - Parity error detected.
SERR# PCI bus signal active status bit. This bit will be set if the
AudioPCI 97 ASIC is asserting the PCI SERR# signal.
0 - SERR# signal inactive.
1 - SERR# signal active.
Master Abort status bit. This bit will be set whenever a AudioPCI
97 ASIC bus mastering transaction has been terminated by a
Master-Abort.
Target Abort status bit. This bit will be set whenever a AudioPCI 97
ASIC bus mastering transaction has been terminated by a TargetAbort.
This status bit is not implemented and always reads back as zero.
DEVSEL# timing. These status bits encode the timing of the PCI
DEVSEL# signal. AudioPCI 97 implements the slow timing mode.
00 - Fast
01 - Medium
10 - Slow
11 - Reserved
These status bits are not implemented and always read back as
zeros.
Indicates support for ACPI. The AudioPCI 97 ASIC does support
ACPI so this bit is set to a one.
These status bits are reserved and always read back as zeros.
Class Code & Revision ID
Addressable as long word
Power on reset value 04010000H
Bit(s) R/W Name
31:8
R
CLASS CODE
7:0
R
REVISION ID
Address 08H
Configuration Space
Data Value
040100H (Multimedia Audio device)
02H
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Cache Line Size
Address 0CH
Addressable as Byte
Power on reset value 00H
Bit(s) R/W Name
7:0
R
CACHE LINE
SIZE
Configuration Space
Data Value
00H
Latency Timer
Address 0DH
Addressable as byte
Power on reset value xxH
Bit(s) R/W Name
7:3
R/W LATENCY
2:0
R
ZERO
Configuration Space
Data Value
Latency Timer specified in PCI bus clocks.
0H
Header Type
Address 0EH
Addressable as byte
Power on reset value 00H
Bit(s) R/W Name
7:0
R
HEADER TYPE
Configuration Space
Data Value
00H
BIST
Address 0FH
Addressable as byte
Power on reset value 00H
Bit(s) R/W Name
7:0
R
BIST
Configuration Space
Data Value
00H
Base Address
Address 10H
Addressable as long word
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:6
R/W BASE ADDRESS
5:1
R
ZERO
0
R
ONE
Configuration Space
Data Value
Variable
00H (address 64 byte aligned)
1H
Base Address
Address 14, 18, 1C, 20, 24H
Addressable as long word
Power on reset value 00000000H
Bit(s) R/W Name
31:0
R
Not implemented
Configuration Space
Data Value
00000000H
Cardbus CIS Pointer
Addressable as long word
Power on reset value 00000000H
Bit(s) R/W Name
31:0
R
Not implemented
Address 28H
Configuration Space
Data Value
00000000H
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Subsystem Vendor ID
Addressable as word
Power on reset value 1274H
Bit(s) R/W Name
15:0
R
SUBSYSTEM
VENDOR ID
Address 2CH
Configuration Space
Data Value
1274H
Subsystem ID
Address 2EH
Addressable as word
Power on reset value 1371H
Bit(s) R/W Name
15:0
R
SUBSYSTEM ID
Configuration Space
Data Value
1371H
Expansion ROM Address
Addressable as long word
Power on reset value 00000000H
Bit(s) R/W Name
31:0
R
EXP ROM ADDR
Address 30H
Configuration Space
Data Value
00000000H
Capabilities Pointer
Addressable as long word
Power on reset value DCH
Bit(s) R/W Name
7:0
R
CAP_PTR
Address 34H
Configuration Space
Data Value
DCH - Pointer to first entry of capabilities list in configuration
space
Interrupt Line
Address 3CH
Addressable as byte
Power on reset value xxH
Bit(s) R/W Name
7:0
R/W INTERRUPT
Configuration Space
Data Value
Variable
Interrupt Pin
Address 3DH
Addressable as byte
Power on reset value 01H
Bit(s) R/W Name
7:0
R
INTERRUPT PIN
Configuration Space
Data Value
01H
Min_Gnt
Address 3EH
Addressable as byte
Power on reset value 0CH
Bit(s) R/W Name
7:0
R
MIN_GNT
Configuration Space
Data Value
0CH
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Max_Lat
Address 3FH
Addressable as byte
Power on reset value 80H
Bit(s) R/W Name
7:0
R
MAX_LAT
Configuration Space
Data Value
80H
Capabilities Identifier
Addressable as byte
Power on reset value 01H
Bit(s) R/W Name
7:0
R
CAP_ID
Address DCH
Configuration Space
Data Value
01H - Indicates Power Management Capability
Next Item Pointer
Address DDH
Addressable as byte
Power on reset value 00H
Bit(s) R/W Name
7:0
R
Next_Item_Ptr
Configuration Space
Data Value
00H - Indicates last entry in capabilities list
Power Management Capabilities - PMC
Addressable as word - Read Only
Power on reset value 6C31H
Bit(s) R/W Name
15:11 R
PME_Support
10
R
D2_Support
9
R
D1_Support
8:6
R
Reserved
5
R
DSI
4
R
AUXPWR
3
R
PMECLK
2:0
R
Version
Address DEH
Configuration Space
Data Value
0DH - Determines level from which PME# can be asserted
1H - D2 is supported
0H - D1 is not supported
0H
1H - Device Specific Initialization Required
1H - Auxiliary power required for PME generation
0H - PCI clock is not required for PME# generation
1H - Indicates conformance to the PCI Power Management 1.0
Specification
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Power Management Control/Status - PMCSR
Address E0H
Addressable as byte, word or long word
Power on reset value 00000001H
Configuration Space
Bit(s) R/W Name
Data Value
15
R/W PME_Status
Set if PME# condition exists regardless of state of PME_En bit. A
clear
write of a 1 to this bit clears the PME condition.
14:13 R
Not Implemented
0H -Data Field not implemented, therefore data scale read only
12:9
R
Not Implemented
0H -Data Field not implemented, therefore data select read only
8
R/W PME_En
Enables the assertion of the PME# pin
7:2
R
Reserved
00H
1:0
R/W PowerState
00 - D0
01 - D1
10 - D2
11 - D3
Whenever this register is written such that the value of the Power State bits change, an interrupt will be
generated. This will appear on the INTA# pin if the PWRINTEN bit is set in the Interrupt Control Register.
The interrupt is cleared by writing the CURPDLEV bits in the interrupt control register to equal the value of
the Power State bits.
7.
REGISTER MAP
All Control registers in AudioPCI 97 are addressed in the direct PCI I/O space. There are control registers
for each of the major blocks of the AUDIOPCI system. The memory map is shown below:
AudioPCI 97 Memory Map
Base
Address
00H
08H
0CH
10H
14H
18H
20H
30H
Upper
Address
07H
0BH
0FH
13H
17H
1FH
2FH
3FH
Module
Interrupt/Chip Select
UART
Host Interface - Memory Page
Sample Rate Converter
CODEC
LEGACY
Serial Interface
Host Interface - Memory
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7.1.
IRQ & Chip Select Block
The IRQ/Chip Select block contains two 32 bit registers. The first register is the control register which can
be read and written. The second register is the status register which is a read only register. The control
registers includes bits for module enables, interrupt control, general purpose I/O pins and power
management functions.
Interrupt/Chip Select Control Register
Addressable as byte, word, longword
Power on reset value FCxF0000H
Bit(s) R/W Name
31:26 R
ONES
25:24 R/W JOY_ASEL[1:0]
23:20
19:16
R
R/W
GPIO_IN[3:0]
GPIO_OUT[3:0]
15
R/W
MSFMTSEL
14
R/W
SYNC_RES
13
R/W
ADC_STOP
12
R/W
PWR_INTRM
11
R/W
M_CB
10
R/W
CCB_INTRM
9:8
R/W
PDLEV[1:0]
Address 00H
Direct Mapped
Function
These bits are not implemented and read back as ones.
These two bits are dedicated to Dave Sowa and will map the
joystick port to 4 different base addresses as follows:
00 - Joystick base address $200
01 - Joystick base address $208
10 - Joystick base address $210
11 - Joystick base address $218
These bits will read the current value on the GPIO [3:0] pins.
These bits when set low will set the corresponding GPIO output
low. If these bits are set high then the GPIO pads will be high or
they can be used as inputs.
This bit selects the MPEG serial data format.
0 - SONY (lrclk high = left channel ; data left justified)
1 - I2S (lrclk low = left channel ; data 1 bit clock delayed)
This bit is used to generate a Warm AC97 Reset as described in
section 5.2.1.2. of the Audio Codec 97 specification.
This bit when set high will prevent the CCB module from doing a
record channel PCI transfer.
0 - CCB will transfer record information.
1 - CCB will not transfer record information.
This bit selects is the interrupt mask bit for detecting changes in the
power management level.
0 - Power level change interrupts are disabled.
1 - Power level change interrupts are enabled.
This bit selects either I2S or the CODEC ADC as the source for the
record channel in the serial module.
0 - CODEC ADC is record channel source.
1 - I2S is record channel source.
This bit is the interrupt mask bit for the CCB module voice
interrupts.
0 - CCB voice interrupts are disabled.
1 - CCB voice interrupts are enabled.
Current power down level. These bits reflect the power down level
the part is currently programmed to. When the Power State bits
programmed in configuration space differs from these bits, an
interrupt is generated. The ISR should program this to equal the
value in configuration space in order to clear the interrupt.
00 - D0
01 - D1
10 - D2
11 - D3
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7
R/W
BREQ
6
R/W
DAC1_EN
5
R/W
DAC2_EN
4
R/W
ADC_EN
3
R/W
UART_EN
2
R/W
JYSTK_EN
1
R/W
XTALCKDIS
0
R/W
PCICLKDIS
This bit controls access to the internal memory. It is for test
purposes only. If this bit is ever set high it will prevent the CCB,
Serial, UART and HOSTIF modules from accessing the memory.
0 - Memory bus request disabled (power on state)
1 - Memory bus request enabled ( disables memory access )
This bit enables the DAC1 playback channel (CODEC FM DAC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - DAC1 playback channel disabled
1 - DAC1 playback channel enabled
This bit enables the DAC2 playback channel (CODEC DAC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - DAC2 playback channel disabled
1 - DAC2 playback channel enabled
This bit enables the ADC playback channel (CODEC ADC).
To restart a channel that had stopped, this bit must be reset low and
then set high.
0 - ADC record channel disabled
1 - ADC record channel enabled
This bit enables UART module operation.
0 - UART disabled
1 - UART enabled
This bit enables Joystick module operation.
0 - Joystick disabled
1 - Joystick enabled
Xtal Clock Disable. This bit when set high will shut down the
crystal clock input to all internal modules.
0 - Xtal Clock enabled.
1 - Xtal Clock Disabled.
PCI Clock Disable. This bit when set high will shut down the PCI
clock input to all internal modules except the PCI module and the
Interrupt/Chip Select module.
0 - PCI Clock Enabled
1 - PCI Clock Disabled
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Interrupt/Chip Select Status Register
Addressable as longword only
Power on reset value 7FFFFEC0H
Bit(s) R/W Name
31
R
INTR
30:9
8
R
R
ONES
SYNC_ERR
7:6
R
VC[1:0]
5
R
MPWR
4
R
MCCB
3
R
UART
2
R
DAC1
1
R
DAC2
0
R
ADC
Address 04H
Direct Mapped
Function
This bit is the summary interrupt bit.
0 - No interrupt pending
1 - Interrupt from DAC1, DAC2, ADC, UART, CCB or power
management has occurred.
These bits always read back as ones.
This bit indicates a synchronization error has occurred in the
CODEC interface module.
0 - CODEC synchronization error has not occurred.
1 - CODEC synchronization error has occurred.
These bits are the voice code from the CCB module. These bits are
only valid if the CCB interrupt bit (mccb) is high.
00 - DAC1
01 - DAC2
10 - ADC
11 - Undefined
This bit indicates whether a power level interrupt has occurred.
0 - No Power Level interrupt.
1 - Power Level interrupt pending.
This bit is the masked CCB interrupt bit. A CCB interrupt will occur
if a PCI bus abort condition occurs during a voice buffer transfer.
The CCB interrupt is masked with the CCB interrupt mask bit
(ccb_intrm) in the control register.
0 - No CCB interrupt
1 - CCB interrupt pending
This bit is the UART interrupt bit.
0 - No UART interrupt
1 - UART interrupt pending
This is the DAC1 playback channel interrupt bit.
0 - No DAC1 channel interrupt
1 - DAC1 channel interrupt pending
This is the DAC2 playback channel interrupt bit.
0 - No DAC2 channel interrupt
1 - DAC2 channel interrupt pending
This is the ADC record channel interrupt bit.
0 - No ADC channel interrupt
1 - ADC channel interrupt pending
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7.2.
UART
The UART contains three 8 bit registers. The data register can be read or written and is used to receive or
transmit MIDI information. The second register is a 8 bit control register which is write only. The third
register is a 8 bit status register which is read only.
UART Data Register
Addressable as byte only
Power on reset value ??H
Bit(s) R/W Name
7:0
R/W DATA[7:0]
Address 08H
Direct Mapped
Function
The UART data register provides access to MIDI serial data
input/output.
UART Status Register
Addressable as byte only
Power on reset value 00H
Bit(s) R/W Name
15
R
RXINT
14:11
R
ZERO
10
R
TXINT
9
R
TXRDY
8
R
RXRDY
Address 09H
Direct Mapped
Function
This bit is the UART receiver interrupt bit.
0 - No UART receiver interrupt
1 - UART receiver interrupt pending
These bits always read back as zeros to allow for soundscape
detection.
This bit is the UART transmitter interrupt bit
0 - No UART transmitter interrupt
1 - UART transmitter interrupt pending
This bit is the UART transmitter ready bit.
0 - UART transmitter not ready
1 - UART transmitter ready
This bit is the UART receiver ready bit.
0 - UART receiver not ready
1 - UART receiver ready
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UART Control Register
Addressable as byte only
Power on reset value 00H
Bit(s) R/W Name
15
W
RXINTEN
14:13
W
TXINTEN[1:0]
12:10
9:8
W
UNDEFINED
CNTRL[1:0]
Address 09H
Direct Mapped
Function
This bit is the UART receiver interrupt enable bit.
0 - UART receiver interrupts disabled
1 - UART receiver interrupts enabled
These two bits are the control bits for the UART transmitter
operation.
00 01 - Txrdy interrupts enabled
10 11 These bits are undefined
These two bits are the control bits for the UART.
00 01 10 11 - Software Reset
UART Reserved Register
Addressable as byte only
Power on reset value 00H
Bit(s) R/W Name
7:1
UNDEFINED
0
R/W TEST_MODE
7.3.
Address 0AH
Direct Mapped
Function
These bits are undefined.
This bit enables the UART test mode. When the test mode bit is set
the UART clock is switched to the PCI bus clock. The faster clock
reduces the size of the test vectors and also shortens the run time of
the test vectors. The power up state is normal mode enabled.
0 - Normal mode enabled.
1 - UART test mode enabled.
Host Interface - Memory Page
The memory page register is a four bit register used to access one of 16 memory pages within the
AUDIOPCI chip. This register can be read or written but any unused bits are undefined on read back.
Memory Page Register
Addressable as byte, word, longword
Power on reset value ???????0H
Bit(s) R/W Name
31:4
UNDEFINED
3:0
R/W MEMORY PAGE
Address 0CH
Direct Mapped
Function
These bits are undefined.
These bits select what memory page will be accessed. Each memory
page is 16 bytes and is addressed from 30H - 3FH.
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7.4.
Sample Rate Converter
This block receives or sends samples from/to the serial interface block for the playback/record channels. It
also provides the necessary sample rate conversion for the AC97 CODEC. The Sample Rate Converter
block contains one 32 bit register. This register is used to read/write the Sample Rate Converter
FIFO/Control RAM.
Sample Rate Converter Interface Register
Addressable as longword
Power on reset value 00000000H
Bit(s) R/W Name
31:25 R/W SRC_RAM_ADR
24
R/W
SRC_RAM_WE
23
R
SRC_RAM_BUSY
22
R/W
SRC_DISABLE
21
R/W
DIS_P1
20
R/W
DIS_P2
19
R/W
DIS_REC
18:16
15:0
R/W
R/W
UNDEFINED
SRC_RAM_DATA
Address 10H
Direct Mapped
Function
These bits are the address of the Sample Rate Converter RAM
location to be accessed.
This bit is the read/write control bit for accessing the Sample Rate
Converter RAM.
This bit when high indicates the Sample Rate Converter is accessing
the RAM. This bit will be set within 3 PCI clocks after accessing
this register. This bit will be Reset when the requested
read/write RAM operation has been completed.
This is the enable bit for the Sample Rate Converter.
0 - Sample Rate Converter enabled.
1 - Sample Rate Converter disabled.
This bit when high will disable Playback channel 1 from updating
the accumulator.
0 - Playback channel 1 accumulator update enabled.
1 - Playback channel 1 accumulator update disabled.
This bit when high will disable Playback channel 2 from updating
the accumulator.
0 - Playback channel 2 accumulator update enabled.
1 - Playback channel 2 accumulator update disabled.
This bit when high will disable Record channel from updating the
accumulator.
0 - Record channel accumulator update enabled.
1 - Record channel accumulator update disabled.
These bits are undefined.
These bits are the value of the RAM to be read/written from /to the
RAM at the location pointed to by the SRC_RAM_ADR address
pointer above.
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7.5.
CODEC Interface
The CODEC interface register is a 32 bit register that provides access to the AC97 CODEC control
registers. This register is a pseudo read/write and must be accessed as a longword. A write to this register
will initiate a CODEC register read/write operation. A read from this register is used to read a CODEC
register that was initiated by a previous write to the CODEC interface register.
CODEC Write Register
Addressable as longword
Power on reset value 00000000H
Bit(s) R/W Name
31:24 W
ZERO
23
W
PIRD
22:16
W
PIADD
15:0
W
PIDAT
Address 14H
Direct Mapped
Function
These bits are always zeros.
AC97 Codec register read/write control bit
0 - Write AC97 CODEC register.
1 - Read AC97 CODEC register.
These bits are the address of the AC97 CODEC register to be
read/written.
These bits are the data value to be written into the AC97 CODEC
register. Set to zero for a AC97 CODEC register read.
CODEC Read Register
Addressable as longword
Power on reset value 00000000H
Bit(s) R/W Name
31
R
RDY
30
R
WIP
29:24
23
R
R
ZERO
PORD
22:16
R
POADD
15:0
R
PODAT
Address 14H
Direct Mapped
Function
This bit when high indicates that this register contains valid read
data from the AC97 CODEC register file.
This bit when high indicates that a register read/write to the AC97
CODEC is in progress.
0 - AC97 CODEC register interface inactive.
1 - AC97 CODEC register access in progress.
These bits always read back as zeros.
AC97 Codec register read/write control bit
0 - Write AC97 CODEC register.
1 - Read AC97 CODEC register.
These bits are the address of the AC97 CODEC register for the read
register operation.
These bits are the data value read from the AC97 CODEC register
at the above address.
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7.6.
Legacy
The Legacy register is a 32 bit register that performs both control and status functions. Basically the
lower word functions as the status register and the upper word functions as the control register. The only
exception to this is bit zero which is a control bit for a write and a status bit for a read.
Legacy Control/Status Register
Address 18H
Addressable as byte, word, longword
Power on reset value 00?????00000000011111?????????0?b
Direct Mapped
Bit(s) R/W Name
Function
31
R/W JFAST
This bit selects fast (vs ISA) joystick timing.
0 - ISA joystick timing
1 - FAST joystick timing
30
R/W HIB
This bit is the host interrupt blocking enable bit (DMA config bit
must be set) to prevent applications from blocking NMI.
0 - Host interrupt blocking disabled
1 - Host interrupt blocking enabled
29
R/W VSB
This bit selects the capture address range for SoundBlaster access.
0 - Address range : 220xH - 22FxH
1 - Address range : 240xH - 24FxH
28:27 R/W VMPU[1:0]
These bits select the capture address range for the Base Register.
00 - Address range : 320xH - 327xH
01 - Address range : 330xH - 337xH
10 - Address range : 340xH - 347xH
11 - Address range : 350xH - 357xH
26:25 R/W VCDC[1:0]
These bits select the capture address range for the CODEC.
00 - Address range : 530xH - 537xH
01 - Undefined
10 - Address range : E80xH - E87xH
11 - Address range : F40xH - F47xH
24
R/W FIRQ
This bit is used to force an interrupt.
0 - Do not force an interrupt
1 - Force an interrupt
23
R/W SDMACAP
This bit enables event capture for the Slave DMA Controller. The
decoded address range for this event is C0xH - DFxH.
0 - Disables event capture
1 - Enables event capture
22
R/W SPICAP
This bit enables event capture for the Slave Interrupt Controller.
The decoded address range for this event is A0xH - A1xH.
0 - Disables event capture
1 - Enables event capture
21
R/W MDMACAP
This bit enables event capture for the Master DMA Controller. The
decoded address range for this event is 0xH - FxH.
0 - Disables event capture
1 - Enables event capture
20
R/W MPICAP
This bit enables event capture for the Master Interrupt Controller.
The decoded address range for this event is 20xH - 21xH.
0 - Disables event capture
1 - Enables event capture
19
R/W ADCAP
This bit enables event capture for the ADLIB registers . The
decoded address range for this event is 388xH - 38BxH.
0 - Disables event capture
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18
R/W
SBCAP
17
R/W
CDCCAP
16
R/W
BACAP
15:11
10:8
R
R
ONE
E2, E1, E0
7:3
R
A[4:0]
2
R
W/R
1
0
R
R/W
ZERO
INT#
1 - Enables event capture
This bit enables event capture for the SoundBlaster registers. The
decoded address range for this event is selected by the VSB control
bit.
0 - Disables event capture
1 - Enables event capture
This bit enables event capture for the CODEC. The decoded address
range for this event is selected by the VCDC[1:0] control bits.
0 - Disables event capture
1 - Enables event capture
This bit enables event capture for the SoundScape Base Address
register. The decoded address range for this event is selected by the
VMPU[1:0] control bits.
0 - Disables event capture
1 - Enables event capture
These bits will always read back as ones
These three bits are the event number of the captured event. The
event number corresponds to the enable bit which allowed the
interrupt. Their decoding is shown below:
000 - SoundScape Base Address
001 - CODEC
010 - SoundBlaster Registers
011 - ADLIB Registers
100 - Master Interrupt Controller
101 - Master DMA Controller
110 - Slave Interrupt Controller
111 - Slave DMA Controller
These bits are the least significant I/O address bits during the event
captured.
This bit indicates whether the event captured was a read or write
operation.
0 - Event captured was a Read
1 - Event captured was a Write
This bit always reads back as a zero.
This bit is the interrupt flag for LEGACY events. A write to this bit
(0 or 1) resets the interrupt flag.
0 - Interrupt did occur
1 - Interrupt did not occur
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7.7.
Serial Interface
There is one 16 bit control register and three 32 bit control/status registers in the serial block. The 16 bit
control register can be read or written. The three 32 bit control/status registers can be read or written but
only the lower 16 bits can actually be written. The upper 16 bits of these registers provides the status of the
internal sample counter.
Serial Interface Control Register
Addressable as byte, word, longword
Power on reset value FF800000H
Bit(s) R/W Name
31:23 R/W ONES
22
R/W DAC_TEST
21:19
R/W
P2_END_INC[2:0]
18:16
R/W
P2_ST_INC[2:0]
15
R/W
R1_LOOP_SEL
14
R/W
P2_LOOP_SEL
13
R/W
P1_LOOP_SEL
12
R/W
P2_PAUSE
11
R/W
P1_PAUSE
Address 20H
Direct Mapped
Function
These bits always read back as ones. They are not writable.
This bit is used for testing purposes. It will select the I2S lrclk input
signal as the source for the playback and record channels. It is used
for test vector generation purposes only.
0 - DAC test mode disabled.
1 - DAC test mode enabled.
These bits are the binary offset value that will be added to the
sample address counter at the end of the loop. This value is used
only if the DAC2 channel is in loop mode; it is not used in stop
mode. If loop mode is selected this value must be greater than zero
otherwise the channel will not function correctly. This minimum
value will be one if 8 bit mode is selected and two if 16 bit mode is
selected.
These bits are the binary offset value that will be added to the
sample address counter when the channel is started/restarted. This
value can be zero and will allow the sample fetch to start on any
byte boundary. For 16 bit data this value must be an even number.
This bit selects loop/stop mode for the ADC channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps recording
1 - Stop mode ; interrupt set (if enabled) , stops recording
This bit selects loop/stop mode for the DAC2 channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps playing
1 - Stop mode ; interrupt set (if enabled) , plays last sample
This bit selects loop/stop mode for the DAC1 channel. This bit
determines what action the channel will perform when the sample
count reaches zero.
0 - Loop mode ; interrupt set (if enabled) but keeps playing
1 - Stop mode ; interrupt set (if enabled) , plays last sample
This bit selects pause mode for the DAC2 playback channel. When
in pause mode the channel will playback the last sample.
0 - Play mode ; normal playback mode or removes channel
from pause mode on next sample after bit is
cleared
1 - Pause mode ; plays last sample continuously on next sample
after the pause bit has been set
This bit selects pause mode for the DAC1 playback channel. When
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10
R/W
R1_INT_EN
9
R/W
P2_INTR_EN
8
R/W
P1_INTR_EN
7
R/W
P1_SCT_RLD
6
R/W
P2_DAC_SEN
5:4
R/W
R1_S_EB :
R1_S_MB
3:2
R/W
P2_S_EB :
P2_S_MB
1:0
R/W
P1_S_EB :
P1_S_MB
in pause mode the channel will playback the last sample.
0 - Play mode ; normal playback mode or removes channel
from pause mode on next sample after bit is
cleared
1 - Pause mode ; plays last sample continuously on next sample
after the pause bit has been set
This bit is the interrupt enable bit for the ADC channel. To clear the
interrupt this bit must be set to zero and then set to one to enable the
next interrupt.
0 - ADC interrupt disabled
1 - ADC interrupt enabled
This bit is the interrupt enable bit for the DAC2 channel. To clear
the interrupt this bit must be set to zero and then set to one to enable
the next interrupt.
0 - DAC2 interrupt disabled
1 - DAC2 interrupt enabled
This bit is the interrupt enable bit for the DAC1 channel. To clear
the interrupt this bit must be set to zero and then set to one to enable
the next interrupt.
0 - DAC1 interrupt disabled
1 - DAC1 interrupt enabled
This bit when set high will force the sample counter for DAC1 to be
reloaded with the sample count register value on the next rising
edge of the DAC1 left/right clock. This bit can be returned low on
the following instruction. It does not have to be held high for more
than 1 microsecond. This control bit is rising edge triggered.
This bit when set high will enable the DAC2 to continue playback
when it is in the stopped condition and the DAC2 channel has been
disabled. Without this bit set if the DAC2 channel is disabled it will
begin to playback zeros.
0 - DAC2 plays back zeros when disabled
1 - DAC2 plays back last sample when disabled and in stop mode
These two bits select the data format for the ADC channel. For eight
bit data modes the msb is always inverted before it is written out to
the buffer. For mono modes only the left channel data is recorded.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
11 - Sixteen bit - Stereo mode
These two bits select the data format for the DAC2 channel. For
eight bit data modes the msb is always inverted after it is read from
the buffer. For mono modes the left channel data is duplicated for
both the left and right channels.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
11 - Sixteen bit - Stereo mode
These two bits select the data format for the DAC1 channel. For
eight bit data modes the msb is always inverted after it is read from
the buffer. For mono modes the left channel data is duplicated for
both the left and right channels.
00 - Eight bit - Mono mode
01 - Eight bit - Stereo mode
10 - Sixteen bit - Mono mode
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11 - Sixteen bit - Stereo mode
DAC1 Channel Sample Count Register
Addressable as word, longword
Power on reset value 00000000H
Bit(s) R/W Name
31:16 R
CURR_SAMP_CT
15:0
R/W
SAMP_CT
Direct Mapped
Function
These bits are the current value of the internal sample counter for
the DAC1 playback channel. The number of samples that have been
played is samp_ct - curr_samp_ct.
These bits are the number of samples minus one that the DAC1
channel will playback.
DAC2 Channel Sample Count Register
Addressable as word, longword
Power on reset value 00000000H
Bit(s) R/W Name
31:16 R
CURR_SAMP_CT
15:0
R/W
SAMP_CT
15:0
R/W
SAMP_CT
Address 28H
Direct Mapped
Function
These bits are the current value of the internal sample counter for
the DAC2 playback channel. The number of samples that have been
played is samp_ct - curr_samp_ct.
These bits are the number of samples minus one that the DAC2
channel will playback.
ADC Channel Sample Count Register
Addressable as word, longword
Power on reset value 00000000H
Bit(s) R/W Name
31:16 R
CURR_SAMP_CT
Address 24H
Address 2CH
Direct Mapped
Function
These bits are the current value of the internal sample counter for
the ADC record channel. The number of samples that have been
played is samp_ct - curr_samp_ct.
These bits are the number of samples minus one that the ADC
channel will record.
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7.8.
Host Interface - Memory
The top 64 bytes of memory are actually used as register storage for the CCB block and also as the FIFO
for the UART block. The CCB registers are located in the lower 32 bytes of this block and require six
longwords. These registers control filling the circular buffers for the two playback channels and the record
channel. Each channel requires 2 longwords. The UART FIFO is located in the upper 32 bytes of this block
and requires all eight longwords but uses only 9 bits of each longword.
DAC1 Frame Register 1
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:0
R/W PCI ADDRESS
Address 30H
Memory Page 1100b
Direct Mapped
Function
This longword is the physical PCI address of DAC1 sample buffer
in system memory
DAC1 Frame Register 2
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:16 R/W Current Count
15:0
R/W
Buffer Size
Address 34H
Memory Page 1100b
Direct Mapped
Function
This 16 bit counter indicates the number of longwords that have
been transferred.
This 16 bit value indicates the number of longwords in a buffer
minus one.
DAC2 Frame Register 1
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:0
R/W PCI ADDRESS
Address 38H
Memory Page 1100b
Direct Mapped
Function
This longword is the physical PCI address of DAC2 sample buffer
in system memory
DAC2 Frame Register 2
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:16 R/W Current Count
15:0
R/W
Buffer Size
Address 3CH
Memory Page 1100b
Direct Mapped
Function
This 16 bit counter indicates the number of longwords that have
been transferred.
This 16 bit value indicates the number of longwords in a buffer
minus one.
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ADC Frame Register 1
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:0
R/W PCI ADDRESS
Address 30H
Memory Page 1101b
Direct Mapped
Function
This longword is the physical PCI address of ADC sample buffer in
system memory
ADC Frame Register 2
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:16 R/W Current Count
15:0
R/W
Buffer Size
UART FIFO Register
Addressable as longword
Power on reset value xxxxxxxxH
Bit(s) R/W Name
31:9
R/W OPEN
8
R/W BYTE VALID
7:0
R/W
UART BYTE
Address 34H
Memory Page 1101b
Direct Mapped
Function
This 16 bit counter indicates the number of longwords that have
been transferred.
This 16 bit value indicates the number of longwords in a buffer
minus one.
Address 30, 34, 38, 3CH
Memory Pages 1110, 1111b
Direct Mapped
Function
These bits are not used.
This bit indicates whether the UART byte contains valid data.
0 - UART byte not valid
1 - UART byte valid
This byte is a byte the has been received by the UART block
through the MIDI interface.
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8.
POWER MANAGEMENT
All power management of the system is under software control. The AC97 CODEC and AudioPCI 97 can
be powered down separately. Neither chip loses register information when powered down.
The AudioPCI 97 can be power managed by shutting down various sub-systems. The following blocks can
be individually powered down: Joystick, UART, and Serial Interface. Although these blocks can be
individually disabled this will not save an appreciable amount of power. AudioPCI 97 can also individually
internally shut down the PCI clock and the Crystal input clock. The PCI clock when shut down will still be
active to the PCI and Interrupt/Chip Select modules. The Crystal clock when shut down will be shut down
for all internal modules as well as the output connection to the AC97 CODEC.
During operation, the AudioPCI 97 ASIC will have a typical power dissipation of 150mW. In power down,
the AudioPCI 97 ASIC will have a typical power dissipation of 15mW.
8.1.
CODEC Power Management
The AC97 CODEC’s are powered down by setting bit 1 (of control bits 7 - 0) in control register 16 (hex) to
a zero. The AC97 CODEC control registers are written through the CODEC Interface block at address 14
(hex). For details refer to the AC97 specification and also the CODEC Interface section (7.5) of this
specification.
8.2.
AUDIOPCI Power Management
As mentioned above, the Joystick, UART, and Serial Interface modules of the AudioPCI 97 chip can be
individually powered down. The remaining modules will be in a powered up condition. The AudioPCI 97
modules are powered down by setting bits 6 - 2 (of control bits 31 - 0) to zero. The AudioPCI 97 control
register is located in the IRQ and Chip Select Block at address 00 (hex). For details refer to the IRQ and
Chip Select Block section (7.1) of this specification. Note that the Serial Interface actually has three
separate enable bits, one for each of the playback channels and one for the record channel.
Although these blocks can be individually disabled this will not save an appreciable amount of power.
AudioPCI 97 can also individually internally shut down the PCI clock and the Crystal input clock. The PCI
clock when shut down will still be active to the PCI and Interrupt/Chip Select modules. The Crystal clock
when shut down will be shut down for all internal modules as well as the output connection to the AC97
CODEC.
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9.
PCI BUS Description and Signals
AudioPCI 97 is designed to adhere to the PCI Local Bus Specification Revision 2.2, as such it complies
with all requirements for bus master capability. It is a 32 bit device and does not currently support the
optional 64 bit bus modes. Of the optional pins described in the PCI specification, AudioPCI 97 only uses
Interrupts.
Although the Sample buffer space is referred to as cache, it is not the system memory cache described in the
PCI specification. This cache is a local sound memory cache and is not part of the directly accessible
system memory. Note: The “#” symbol indicates a low active signal.
9.1.
Parity
AudioPCI 97 implements the PAR signal. This signal is an even parity check described in the PCI
specification. AudioPCI 97 will generate PAR whenever it drives AD[31:0]. Although AudioPCI will
generate PAR , it will not generate the Bus Error condition signals PERR# and SERR# due to parity errors
on data received. This exception is allowed in the PCI Specification section 3.8.2.
9.2.
LOCK#
AudioPCI 97 does not support PCI bus lock functions.
9.3.
Bus Speed
Since AudioPCI 97 uses a high speed intermediate buffer to transfer data to and from the PCI bus, it runs at
the standard 33 MHz. Rate. However, it is believed that the memory speed on the PCI bus may limit the
transaction rate by inserting one wait state. All latency calculations are based on this assumption.
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10.
PIN DESCRIPTION
10.1. PCI Interface
The PCI Interface follows the information presented on the PCI Local Bus Specification Revision 2.2. For
a more complete description of each of the PCI signal please refer to the PCI specification.
CLK
Clock: A 33MHz input signal from the PCI bus. This is the master timing control for all
PCI transfers.
RST#
Reset: The device will essentially be in sleep mode after reset.
AD[31:0]
The Address/Data multiplexed signals of the PCI Bus.
C/BE#[3:0]
Bus Command and Byte Enables. Defines the type of transfer that will take place.
FRAME#
Cycle Frame. Driven by the current bus master, this signal indicates the beginning of a
transfer. When FRAME# is deasserted, the transaction is in the final phase.
IRDY#
Initiator Ready. This signal indicates that the initiating agent (the bus master) is able to
accept the data phase of the transaction. Normally used to create wait states by the
master.
TRDY#
Target Ready. Driven by the target (the selected device), this signal indicates that the
target is ready for the data transaction. Generally used to generate wait states by the
target.
STOP#
Stop indicates the current target is requesting the master to stop the current transaction.
SERR#
System Error. This pin is an output only pin on the ES1371.
PAR
The Parity signal is even parity. The number of “1”s on AD[31:0],C/BE[3:0] and Par
equal an even number.
IDSEL
Initialization Device Select. This signal is used as a chip select during configuration read
and write transactions
DEVSEL#
Device Select. This signal, when actively driven, indicates that the driving device has
decoded its address as the target of the current transaction.
REQ#
Request indicates to the arbiter that AudioPCI 97 desires use of the bus.
GNT#
Grant. This signal indicates that control of the PCI Bus has been granted and AudioPCI
97 is now the bus master.
INTA#
AudioPCI 97 supplies interrupt support for all possible interrupt configurations. This is
done so that the greatest possible flexibility can be achieved during the configuration
process.
PME#
Power Management Enable. This signal is not implemented in the ES1371. It is an output
only and will be set high. It should be left as a no connect on a PC board.
10.2. AC97 CODEC Interface
SDATAOUT
SYNC
SDATAIN
BCLK
Serial Data to AC97 CODEC
SYNC output to AC97 CODEC
Serial Data from AC97 CODEC
Bit Clock from AC97 CODEC
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10.3. Miscellaneous
JYSTK[7:0]
MIDI_OUT
MIDI_IN
XTALI/O
XTALOBUF
GPIO[3:0]
I2S_LRCLKIN
I2S_BCLKIN
I2S_SERIN
Joystick and Button inputs
Serial output for MIDI compatible communications
Serial input for MIDI compatible communications
Crystal input and output
Crystal output buffered (for connection to AC97 CODEC)
General purpose input/output port. These pins have internal pullups.
External source I2S left/right clock input. No internal pullup/pulldown.
External source I2S bit clock input. No internal pullup/pulldown.
External Source I2S serial data input. No internal pullup/pulldown.
10.4. Power Supplies
VDD
VSS
Digital Supply Voltage (+5v)
Digital Ground pins
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ENSONIQ
AC97
ES1371
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
IDSEL
AD23
AD22
AD21
VSS
AD20
AD19
AD18
AD17
VSS
VDD
AD16
CBE2#
FRAME#
IRDY#
VSS
TRDY#
DEVSEL#
STOP#
SERR#
PAR
CBE1#
AD15
VDD
VSS
AD14
AD13
AD12
AD11
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VDD
CBE3#
AD24
AD25
AD26
VSS
AD27
AD28
AD29
AD30
VSS
AD31
PME#
REQ#
GNT#
VDD
PCI_CLK
VSS
RST#
INTA#
PINOUT.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
AD10
AD9
AD8
CBE0#
VSS
VDD
AD7
AD6
AD5
AD4
VSS
AD3
AD2
AD1
AD0
VSS
I2S_SERIN
I2S_BCLKIN
VDD
11.
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VSS
JYSTK0
JYSTK1
JYSTK2
JYSTK3
VSS
VDD
JYSTK4
JYSTK5
JYSTK6
JYSTK7
MIDI_OUT
MIDI_IN
VSS
XTALO
XTALI
VSS
XTALOBUF
VDD
SDATAOUT
BCLK
SDATAIN
SYNC
VSS
GPIO3
GPIO2
GPIO1
GPIO0
I2S_LRCLKIN
VSS
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12.
TIMING.
AudioPCI 97 is being designed to conform to the PCI Local Bus Specification Revision 2.2. Since
AudioPCI 97 has a high speed intermediate 8 LWORD RAM buffer, the design target is to have no wait
states on the data transfers. This level of performance is currently being evaluated.
For detailed information on the PCI timing for AudioPCI 97 please refer to section 3.3 Bus Transactions in
the PCI Specification.
The timing information for the signals from the AudioPCI 97 to the AC97 CODEC can be found in the
Audio Codec ‘97 Component Specification.
13.
DC Characteristics
The DC characteristics for AudioPCI 97 conform to the DC specification for the PCI bus.
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14.
Mechanical Information
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ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997
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A
B
51
81
C D
G
31
1
F
E
H
J
N
L
M
K
O
QFP 100
Plastic Package
100 Pin Flat Pack
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
A
23.65
24.15
0.931
0.951
B
19.90
20.10
0.783
0.791
C
13.90
14.10
0.547
0.555
D
17.65
18.15
0.695
0.715
E
0.65
0.65
0.026
0.026
F
0.20
0.30
0.008
0.012
G
0.45
0.55
0.018
0.022
H
0.20
0.40
0.008
0.016
J
1.95
1.95
0.077
0.077
-10 to 0 degree's
K
L
0.15
0.15
0.006
0.006
M
2.57
2.87
0.101
0.113
N
0.10
0.40
0.004
0.016
O
0.65
0.95
0.026
0.037
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15.
APPENDIX
15.1. Bus Latency
Since each audio channel has a 64 byte buffer, the Latency requirement for the PCI bus can be
calculated as follows:
For 8 bit audio: 32 Samples (one half buffer) @ 44.1 kHz. = 725µsec.
For 16 bit audio: 16 Samples @ 44.1 kHz. = 363 µsec.
Therefore, once a Bus Request is made, AudioPCI 97 needs to have the PCI bus grant in 363 µsec. for 16
bit samples. In most game environments the sound effects are 8 bit and the high latency figure is
acceptable. If more than one channel needs servicing, this does not impact the latency calculation because
once the PCI Bus is granted it can be held until all channels are serviced. Since AudioPCI 97 uses 8 Long
Word burst transfers, each channel is filled with one burst transfer and AudioPCI 97 can service all three
with just 24 transfers.
15.2. Bus Bandwidth
The Bus bandwidth required by AudioPCI is very low. If all three channels are running at 44.1 kHz the
total bandwidth is:
44.1 kHz × 2 (stereo) × 3 (channels) × 2 (bytes) = 529 KBytes/sec.
This represents less than 0.5% of the available PCI Bus bandwidth.
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