SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 D D D description These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the ’ABT2241 and ’ABT2244A, these devices provide combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. These devices feature high fan-out and improved fan-in. 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54ABT2240A . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 2OE D SN54ABT2240A . . . J OR W PACKAGE SN74ABT2240A . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) 2Y4 1A1 1OE VCC D Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 D These devices are organized as two 4-bit line drivers with separate OE inputs. When OE is low, the devices pass inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT2240A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT2240A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 FUNCTION TABLE (each buffer) INPUTS OUTPUT Y OE A L H L L L H H X Z logic symbol† 1OE 1A1 1A2 1A3 1A4 1 2OE EN 2 1 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 EN 9 1 13 7 15 5 17 3 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 POST OFFICE BOX 655303 19 11 9 13 7 15 5 17 3 • DALLAS, TEXAS 75265 2Y1 2Y2 2Y3 2Y4 2Y1 2Y2 2Y3 2Y4 SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 schematic of Y outputs VCC Output GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 recommended operating conditions (see Note 3) SN54ABT2240A VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate High-level input voltage SN74ABT2240A MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled 0 V V 0.8 VCC –24 UNIT VCC –32 V V mA 12 12 mA 5 5 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V –1.2 MAX MIN –1.2 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 12 mA 2* VCC = 5.5 V, VCC = 5.5 V, VI = VCC or GND VO = 2.7 V IOZL Ioff VCC = 5.5 V, VCC = 0, VO = 0.5 V VI or VO ≤ 4.5 V ICEX VCC = 5.5 V, VO = 5.5 V Outputs high IO‡ VCC = 5.5 V, ICC 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND Data inputs VO = 2.5 V Outputs high V 2 0.8 0.8 0.8 V mV ±1 ±1 ±1 µA 10* 10 10 µA –10* –10 –10 µA ±100 µA 50 µA –180 mA ±100 50 –50 UNIT V 100 Control inputs –100 –180 50 –50 –180 –50 1 250 250 250 µA Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 µA 1.5 1.5 1.5 0.05 0.05 0.05 1.5 1.5 1.5 VCC = 5.5 V, Outputs enabled One input at 3.4 V,, Other inputs at Outputs disabled VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V POST OFFICE BOX 655303 mA 4 pF 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 MAX –1.2 2.5 II IOZH Co MIN SN74ABT2240A 2.5 VCC = 4.5 V, Ci SN54ABT2240A 2.5 VOL Vhys ∆ICC§ TA = 25°C MIN TYP† MAX • DALLAS, TEXAS 75265 SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT2240A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y TYP MIN MAX UNIT MAX 1 3 4 1 5 2.1 4.8 5.8 2.1 6.3 1.5 3.7 4.7 1.5 6.1 1.7 6.5 7.6 1.7 8.8 1.8 3.8 6.4 1.5 6.8 1 4.7 5.8 1 6.9 ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT2240A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 5 V, TA = 25°C MIN MAX MIN TYP MAX 1 3 4.1 1 4.8 2.1 4.1 5.1 2.1 5.4 1.1 3.1 4.7 1.1 5.2 1.7 4.5 6.4 1.7 6.8 1.8 3.4 5.7 1.8 6.4 1.9 3.6 6 1.9 6.2 UNIT ns ns ns 5 SN54ABT2240A, SN74ABT2240A OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS232E – JANUARY 1991 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH 1.5 V 1.5 V VOL tPHL 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH VOH Output 3V Output Control tPHL VOH Output 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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