TI SN74ABTH16244DGG

SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
SN54ABTH16244 . . . WD PACKAGE
SN74ABTH16244 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
description
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The ’ABTH16244 devices are 16-bit buffers and
line drivers designed specifically to improve both
the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices can be
used as four 4-bit buffers, two 8-bit buffers, or one
16-bit buffer. These devices provide true outputs
and symmetrical active-low output-enable (OE)
inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH16244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16244 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic symbol†
1OE
2OE
1
EN1
48
25
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
24
EN2
EN3
EN4
47
1
1
46
3
44
5
43
6
41
40
1
2
8
9
38
11
37
12
36
13
35
1
3
14
33
16
32
17
30
1
4
19
29
20
27
22
26
23
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
2
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1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
recommended operating conditions (see Note 3)
SN54ABTH16244
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABTH16244
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
0
V
V
0.8
VCC
–24
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
Vhys
II
VCC = 5.5 V,
5V
VCC = 4
4.5
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
IO‡
VCC = 5.5 V,
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
MIN
–1.2
MAX
SN74ABTH16244
MIN
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
VI = VCC or GND
VI = 0.8 V
VI = 2 V
VO = 2.7 V
0.55
100
–40
–40
–40
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
10
10
–10
–10
±100
50
–100
Outputs disabled
Ci
±1
100
Outputs low
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
±1
100
Outputs high
POST OFFICE BOX 655303
V
mV
±1
–50
V
V
0.55
0.55*
VO = 0.5 V
VI or VO ≤ 4.5 V
VO = 2.5 V
Outputs high
UNIT
2
0.55
–180
50
–50
–180
–50
µA
µA
10
µA
–10
µA
±100
µA
50
µA
–180
mA
3
3
3
32
32
32
3
3
3
1.5
1.5
1.5
mA
mA
3
pF
8
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
4
MAX
–1.2
2.5
∆ICC§
Co
SN54ABTH16244
100
II(hold)
I(h ld)
ICEX
TA = 25°C
MIN TYP†
MAX
• DALLAS, TEXAS 75265
SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABTH16244
SN74ABTH16244
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1
2.3
3.2
0.7
3.6
1
3.5
1
2.6
3.7
0.5
4.2
1
4.1
1
3
3.8
0.7
4.9
1
4.8
1
3.2
4
0.9
5.3
1
4.8
1
3.6
4.4
0.7
5.3
1
4.8
1
2.9
3.7
1
4.6
1
4.1
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UNIT
ns
ns
ns
5
SN54ABTH16244, SN74ABTH16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS677D – SEPTEMBER 1996 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
Input
1.5 V
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright  2000, Texas Instruments Incorporated