White Electronic Designs WED3C7410E16M-400BX
RISC Microprocessor Multichip Package *PRELIMINARY
OVERVIEW
The WED3C7410E16M-400BX is offered in Commercial (0°C
to +70°C), industrial (-40°C to +85°C) and military (-55°C
to +125°C) temperature ranges and is well suited for embedded applications such as missiles, aerospace, flight
computers, fire control systems and rugged critical systems.
The WEDC 7410E/SSRAM multichip package is targeted for
high performance, space sensitive, low power systems and
supports the following power management features: doze,
nap, sleep and dynamic power management.
*This data sheet describes a product that is developmental, is not qualified or
characterized and is subject to change without notice.
The WED3C7410E16M-400BX multichip package consists
of:
• 7410E AltiVec RISC processor
FEATURES
• Dedicated 2MB SSRAM L2 cache, configured as
256Kx72
n Footprint compatible with WED3C7558M-XBX and
WED3C750A8M-200BX
• 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
• Maximum Core frequency = 400MHz @ 1.8V
n Implementation of Altivec technology instruction set
• Maximum L2 Cache frequency = 200MHz
n Optional, high-bandwidth MPX bus interface
• Maximum 60x Bus frequency = 100MHz
FIG. 1 MULTI-CHIP PACKAGE DIAGRAM
AltiVec is a trademark of Motorola Inc.
October 2002 Rev. 5
1
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2
128-Bit
SSRAM
64- 32-Bit L2 Data Bus
32-Bit
+
L2PMCR
L2CR
L2 Tags
64-Bit Data Bus
32-Bit Address Bus
L2 Data
Transaction
Queue
L2 Controller
..
Interger
Unit 2
Interger
Unit 1
+ x
Reservation
Station
GPR File
6 Rename
Buffers
Vector
Touch
Queue
..
L2 Castout
L2 Miss
32-Bit
PA
Data
Transaction
Queue
Bus Interface Unit
32-Bit
System
Register
Unit
Reservation
Station
Dispatch Unit
IBAT
Array
DBAT
Array
64-Bit
..
Instruction
Reload Buffer
Instruction
Reload Table
Data Reload Data Reload
Table
Buffer
64-Bit
32-Kbyte
I Cache
..
FPSCR
+ x
Floating-Point
Unit
Reservation
Station
32-Kbyte
I Cache
Tags
128-Bit
(4 Instructions)
FPR File
6 Rename
Buffers
Tags
Memory Subsystem
L1
Complete
Stores Operations
(EA Calculation)
Load Fold
Finished
Queue
Stores
+
Load/Store Unit
Reservation
Station (2 Entry)
128-Entry
DTLB
SRs
(Original)
Data MMU
CTR
LR
EA
128-Entry
DTLB
BHT
(512 Entry)
BTIC
(64 Entry)
Reservation
Station
128-Bit
19-Bit L2 Address Bus
..
VR File
6 Rename
Buffers
Ability to complete up
to two instructions per clock
SSRAM
Completion Queue
(8 Entry)
Completion Unit
VSCR
Vector ALU
Vector
Permute
Unit
VSIU VCIU VFPU
Reservation
Station
Instruction Queue
(6 Word)
SRs
(Shadow)
Branch Processing Unit
FIG. 2
Reservation
Station
Additional Features
Time Base
Counter/Decrementer
Clock Muliplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
Fetcher
Instruction MMU
White Electronic Designs WED3C7410E16M-400BX
BLOCK DIAGRAM
White Electronic Designs WED3C7410E16M-400BX
FIG. 3
B LOCK DIAGRAM, L2 I NTERCONNECT
SSRAM 1
L2pin_DATA
DQa
L2pin_DATA
DQb
L2pin_DATA
DQc
L2pin_DATA
DQd
U1
DP0-3
L2DP0-3
FT
SBd
SBc
SBb
SBa
SW
ADSP
ADV
SE2
K
SGW
SE1
L2 CLK_OUT A
L2WE
L2CE
L2Vdd
ADSC
SE3
LBO
SA0-17
G
ZZ
µP
7410E
A0-17
SSRAM 2
SA0-17
SGW
SE1
K
L2CLK_OUT B
U2
L2Vdd
FT
SBd
SBc
SBb
SBa
SW
ADSP
ADV
L2pin_DATA
DQa
L2pin_DATA
DQb
L2pin_DATA
DQc
SE3
DQd
LBO
L2pin_DATA
SE2
ADSC
G
DP0-3
L2DP4-7
ZZ
L2ZZ
3
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White Electronic Designs WED3C7410E16M-400BX
FIG. 5
P IN ASSIGNMENTS
Ball assignments of the 255 CBGA package as viewed from the top surface.
Side profile of the CBGA package to indicate the direction of the top surface view.
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White Electronic Designs WED3C7410E16M-400BX
PACKAGE PINOUT LISTING
Signal Name
A[0-31]
Pin Number
C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14,
J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1
Active
High
I/O
I/O
AACK
ABB/AMONO (8)
L2
K4
Low
Low
Input
Output
AP[0-3]
ARTRY
C1, B4, B3, B2
J4
High
Low
I/O
I/O
AVDD
BG
A10
L1
—
Low
Input
Input
BR
BVSEL (4, 6)
B6
B1
Low
High
Output
Input
CHK (5, 6, 13)
CI
C6
E1
Low
Low
Input
I/O
CKSTP_IN
CKSTP_OUT
D8
A6
Low
Low
Input
Ouput
CLK_OUT
DBB/DMONO (8)
D7
J14
High
Low
Output
Output
DBG
DBWO/DTI[0]
N1
G4
Low
Low
Input
Input
DH[0-31]
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8,
N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4
High
I/O
DL[0-31]
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4
High
I/O
DP[0-7]
DRDY (5, 9, 12)
M2, L3, N2, L4, R1, P2, M4, R2
D5
High
Low
I/O
Output
DTI 1-2 (9, 11)
EMODE (10, 11)
G16, H15
C4
High
Low
Input
Input
GBL
GND
F1
C5, C12, E3, E6, E8, E9, E11, E14, F3, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12,
Low
—
I/O
—
HIT (5) (12)
J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12
A3
Low
Output
HRESET
INT
A7
B15
Low
Low
Input
Input
L1_TSTCLK (1)
L2_TSTCLK (1)
D11
D12
High
High
Input
Input
L2AVDD
L2VDD (5) (7)
L11
A2, B8, C3, D6, J16
—
—
L2OVDD
L2VSEL (3, 6)
E10, E12, M12, G12, G14, K12, K14
B5
LSSD_MODE (1)
MCP
1.8V (7)
2.5V (7) 3.3V (7)
1.8V
1.8V
GND
HRESET OVDD
GND
GND
GND
Input
Input
1.8V
3.3V
1.8V
3.3V
1.8V
3.3V
—
High
Input
Input
*—
2.5V
N/A
HRESET N/A
B10
C13
Low
Low
Input
Input
NC (No-connect)
OVDD (2)
B7, C8
C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10
—
—
—
Input
PLL_CFG[0-3]
QACK
A8, B9, A9, D9
D3
High
Low
Input
Input
QREQ
RSRV
J3
D1
Low
Low
Output
Output
SHD0-1 (5) (14)
SMI
A4, A5
A16
Low
Low
I/O
Input
SRESET
B14
Low
Input
5
1.8V
3.3V
1.8V
2.5V
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3.3V
White Electronic Designs WED3C7410E16M-400BX
PACKAGE PINOUT L ISTING (CONTINUED )
Signal Name
Active
I/O
SYSCLK
C9
Pin Number
—
Input
TA
H14
Low
Input
TBEN
C2
High
Input
TBST
A14
Low
Output
TCK
C11
High
Input
TDI (6)
A11
High
Input
TDO
A12
High
Output
TEA
H13
Low
Input
TMS (6)
B11
High
Input
TRST (6)
C10
Low
Input
TS
J13
Low
I/O
TSIZ[0-2]
A13, D10, B12
High
Output
TT[0-4]
B13, A15, B16, C14, C15
High
I/O
VDD (2)
F6, F8, F9, F11, G7, G10, H4, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9
—
Input
WT
D2
Low
I/O
1.8V (7)
2.5V (7)
1.8V
1.8V
NOTES:
1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
3. To allow future L2 cache I/O interface voltage changes.
4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL to HRESET (Selects 2.5V Interface) or to GND (Selects 1.8V
Interface) or to OVDD (Selects 3.3V Interface).
5. Uses one of 9 existing no-connects in WEDC’s WED3C755A8M-300BX.
6. Internal pull up on die.
7. OVdd supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies
power to the L2 cache I/O interface (L2ADDR (0-18], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals; L2AVDD supplies
power to the SSRAM core memory; and Vdd supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and
L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL pin
configuration and the voltage supplied. For actual recommended value of Vin or supply voltages see Recommended Operating Conditions.
8. Output only for 7410, was I/O for 750/755.
9. Enhanced mode only.
10. Deasserted (pulled high) at HRESET for 60x bus mode.
11. Reuses 750/755 DRTRY, DBIS, and TLBISYNC pins (DTI1, DTI2, and EMODE respectively).
12. Unused output in 60x bus mode.
13. Connect to HRESET to trigger post power-on-reset (por) internal memory test.
14. Ignored in 60x bus mode.
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3.3V (7)
1.8V
White Electronic Designs WED3C7410E16M-400BX
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Notes
Core supply voltage
Vdd
-0.3 to 2.1
V
(4)
PLL supply voltage
AVdd
-0.3 to 2.1
V
(4)
L2 DLL supply voltage
L2AVDD
-0.3 to 2.1
V
(4)
60x bus supply voltage
OVdd
-0.3 to 3.465
V
(3)
L2 bus supply voltage
L2OVdd
-0.3 to 2.6
V
(3)
L2 supply voltage
Input supply
L2Vdd
-0.3 to 4.6
V
(5)
Processor Bus
Vin
-0.3 to 0Vdd +0.2
V
(2)
L2 bus
Vin
-0.3 to L20Vdd +0.2
V
(2)
JTAG Signals
Vin
-0.3 to OVdd +0.2
V
(2)
Tstg
-55 to 150
°C
Storage temperature range
NOTES:
1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage
to the device.
2. Caution: Vin must not exceed OVdd by more than 0.2V at any time including during power-on reset.
3. Caution: OVdd/L2OVDD must not exceed Vdd/AVdd/L2AVdd by more than 2.0 V at any time including during power-on reset.
4. Caution: Vdd/AVdd/L2AVDD must not exceed L2OVdd/OVdd by more than 0.4 V at any time including during power-on reset.
5. L2OVdd should never exceed L2Vdd
RECOMMENDED OPERATING CONDITIONS
Characteristic
Core supply voltage
PLL supply voltage
L2 DLL supply voltage
Memory core supply voltage
Processor bus supply voltage
L2 bus supply voltage
Input Voltage
Symbol
Recommended
Value
Unit
Vdd
1.8v ± 100mV
V
AVdd
1.8v ± 100mV
V
L2AVdd
1.8v ± 100mV
V
L2Vdd
3.3v ± 165mV
V
BVSEL = 0
OVdd
1.8± 100mV
V
BVSEL = HRESET
OVdd
2.5v ± 100mV
V
BVSEL = HRESET or BVSEL=1
OVdd
3.3v ± 165 mV
V
L2VSEL = HRESET or 1
L20Vdd
2.5v ± 100 mV
V
Processor bus and
JTAG Signals
Vin
GND to OVdd
V
NOTE:
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed
7
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White Electronic Designs WED3C7410E16M-400BX
POWER CONSUMPTION
VDD =AVDD=1.8±0.1V VDC, L2VDD =3.3V ±5% VDC, GND=0 VDC , 0≤
≤ TJ <105°C
Processor (CPU) FFrequency/L2
requency/L2 FFrequency
requency
400 MHz/200MHz
Full-on Mode
Unit
Notes
Typical
5.7
W
1, 3
Maximum
13.5
W
1, 2
Doze Mode
Maximum
5.3
W
1, 2
Nap Mode
Maximum
2.25
W
1, 2
Sleep Mode
Maximum
2.20
W
1, 2
Sleep Mode–PLL and DLL Disabled
Maximum
2.0
W
1, 2
NOTES:
1. These values apply for all valid system bus and L2 bus ratios. The values do not include OVdd; AVdd and L2AVdd suppling power. OVdd power is
system dependent, but is typically <10% of Vdd power. Worst case power consumption, for AVdd=15mW and L2AVdd=15mW.
2. Maximum power is measured at Vdd=1.9 V while running an entirely cache-resident, contrived sequence of instructions which keep the execution
units maximally busy.
3. Typical power is an average value measured at Vdd=AVdd=L2AVdd=1.8V, OVddd=L2OVdd=2.5V in a system, executing typical applications and
benchmark sequences.
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure and
operate the L2 cache. It is cleared by hard reset or power-on reset.
FIG . 5 L2 CACHE CONTROL R EGISTER (L2CR)
L2WT
L2PE
L2DO
L2CTL
L2TS
L2DF
L2SL
L2BYP
L2FA
L2CLKSTP
L2HWF L2IO
L2DRO
L2IP
L2E
0
L2SIZ
1
2
3
L2CLK
4
L2RAM
6
7
L21
L2OH
0000000
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
The L2CR bits are described in Table 1.
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30
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TABLE 1: L2CR BIT SETTINGS
Bit
Name
Function
0
L2E
L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache unit receives. Before
enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the L2 DLL must stabilize. All other L2CR bits must
be set appropriately. The L2 cache may need to be invalidated globally.
1
L2PE
L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When disabled, generated
parity is always zeros. L2 Parity is supported by WEDC’s WED3C7410E16M-400BX, but is dependent on application.
2–3
L2SIZ
L2 size—Should be set according to the size of the private memory setting. Total SRAM space is 2M bytes (256Kx72). See L2
cache/private memory configurations table in Motorola User’s Manual.
4–6
L2CLK
L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock frequency that the
L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is stopped and the on-chip DLL for the L2
interface is disabled. For nonzero values, the processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock
ratio is chosen, the DLL must stabilize before the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower
than the clock frequency of the 60x bus interface.
000
001
010
011
100
101
110
111
7–8
L2RAM
L2 clock and DLL disabled
÷1
÷ 1.5
÷ 3.5
÷ 2
÷ 2.5
÷3
÷4
L2 RAM type—Configures the L2 RAM interface for the type of synchronous SRAMs used:
• Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out
The 7410 does not burst data into the L2 cache, it generates an address for each access.
10: Pipelined (register-register) synchronous burst SRAM - Setting for WED3C7410E16M-400BX
9
L2DO
L2 data only. Setting this bit enablesÚdata-only operation in the L2 cache. When this bit is set, only transactions from the L1 data
cache can be cached in the L2 cache. L1 instruction cache operations will be serviced for instruction addresses already in the L2
cache; however, the L2 cache will not be reloaded for L1 instruction cache misses. Note that setting both L2DO and L2IO effectively
locks the L2 cache.
10
L2I
L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must not be set while the L2
cache is enabled. See
Motorola’s User manual for L2 Invalidation procedure.
11
L2CTL
L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode) signal for cache RAMs.
Sleep mode is supported by the WED3C7410E16M-400BX
WED3C7410E16M-400BX. While L2CTL is asserted, L2ZZ asserts automatically when the device
enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. This bit should not be set when the
device is in nap mode and snooping is to be performed through deassertion of QACK.
12
L2WT
L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all writes to the L2 cache also
write through to the system bus. For these writes, the L2 cache entry is always marked as clean (value unmodified) rather than dirty
(value modified). This bit must never be asserted after the L2 cache has been enabled as previously-modified lines can get remarked
as clean (value unmodified) during normal operation.
13
L2TS
L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from dcbf and dcbst instructions to be
written only into the L2 cache and marked valid, rather than being written only to the system bus and marked invalid in the L2 cache
dcbf instruction sequence to be used with the L1 cache enabled to easily initialize the L2 cache
in case of hit. This bit allows a dcb
dcbz/dcbf
with any address and data information. This bit also keeps dcbz instructions from being broadcast on the system and single-beat
cacheable store misses in the L2 from being written to the system bus.
14–15
L2OH
L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2 data RAMs.
01: 0.8ns Hold Time - Setting for WED3C7410E16M-400BX
9
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TABLE 1: L2CR BIT SETTINGS
Bit
Name
Function
16
L2SL
L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the delay through the DLL to
accommodate slower L2 RAM bus frequencies.
17
L2DF
18
L2BYP
19
L2FA
0: Setting for WED3C7410E16M-400BX because L2 RAM interface is operated above 100 MHz.
L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.
0: Setting for WED3C7410E16M-400BX because late-write SRAMs are not used.
L2 DLL bypass is reserved.
0: Setting for WED3C7410E16M-400BX
L2 flush assist (for software flush). When this bit is negated, all lines castout from the dL1 which have a state of CDMRSV=01xxx1
(i.e. C-bit negated), will not allocate in the L2 if they miss. Asserting this bit forces every castout from the dL1 to allocate an entry in the
L2 if that castout misses in the L2 regardless of the state of the C-bit. The L2FA bit must be set and the L2IO bit must be cleared in order to
use the software flush algorithm.
20
L2HWF
L2 hardware flush. When the processor detects the value of L2HWF set to 1, the L2 will begin a hardware flush. The flush will be done by
starting with low cache indices and increment these indices for way 0 of the cache, one index at a time until the maximum index value
is obtained. Then, the index will be cleared to zero and the same process is repeated for way 1 of the cache. For each index and way of
the cache, the processor will generate a castout operation to the system bus for all modified 32-byte sectors. At the end of the hardware
flush, all lines in the L2 tag will be invalidated. During the flush, all memory activity from the icache and dcache are blocked from accessing
the L2 until the flush is complete. Snoops, however, are fully serviced by the L2 during the flush. When the L2 tags have been fully flushed
of all valid entries, this bit will be reset to b’0" by hardware. When this bit is cleared, it does not necessarily guarantee that all lines form
the L2 have been written completely to the system interface. L2 copybacks can stll be queued in the bus interface unit. Below is the code
which must be run to use L2 Hardware Flush. When the final sync completes, all modified lines in the L2 will have been written to the system
address bus.
Disable interrupts
dssall
sync
set L2HWF
sync
21
L2IO
L2 Instruction-Only. Setting this bit enales instruction-only operation in the L2 cache. For this operation, only transactions from the L1
instruction cache are allowed to be reloaded in the L2 cache. Data addresses already in the cache will still hit for the L1 data cache. When
both L2DO and L2IO are asserted, the L2 cache is effectively locked.
22
L2CLKSTP
L2 Clock Stop. Setting this bit enables the automatic stopping of the L2CLK_OUT signals for cache rams that support this function. While
L2CLKSTP is set, the L2CLK_OUT signals will automatically be stopped when WED3C7410E16M-400BX enters nap or sleep mode, and
automatically restarted when WED3C7410E16M-400BX exits nap or sleep.
23
L2DRO
L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a checkstop for the processor.
A potential rollover condition occurs when the DLL is selecting the last tap of the delay line, and thus may risk rolling over to the first tap with
one adjustment while in the process of keeping synchronized. Such a condition is improper operation for the DLL, and, while this condition is
not expected, it allows detection for added security. This bit can be set when the DLL is first enabled (set with the L2CLK bits) to detect
rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E bit) after the DLL has achieved its initial lock.
24–30
-
Reserved
31
L2IP
L2 global invalidate in progress (read only)—See the Motorola user’s manual for L2 Invalidation procedure.
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White Electronic Designs WED3C7410E16M-400BX
PLL POWER SUPPLY FILTERING
The AVdd and L2AVdd power signals are provided on
The circuit should be placed as close as possible to the
the WED3C7410E16M-400BX to provide power to the
AVdd pin to minimize noise coupled from nearby
clock generation phase-locked loop and L2 cache
circuits. An identical but separate circuit should be
delay-locked loop respectively. To ensure stability of
placed as close as possible to the L2AVdd pin. It is
the internal clock, the power supplied to the AVdd
often possible to route directly from the capacitors to
input signal should be filtered of any noise in the
the AVdd pin, which is on the periphery of the 255 BGA
500kHz to 10 MHz resonant frequency range of the
footprint, without the inductance of vias. The L2AVdd
PLL. A circuit similar to the one shown in Figure 6
pin may be more difficult to route but is proportionately
using surface mount capacitors with minimum Effective
less critical.
Series Inductance (ESL) is recommended. Multiple
small capacitors of equal value are recommended over
a single large value capacitor.
FIG. 6 POWER SUPPLY F ILTER CIRCUIT
10 Ω
AVdd (or L2AVdd)
Vdd
2.2 µF
2.2 µF
Low ESL surface mount capacitors
GND
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs WED3C7410E16M-400BX
PACKAGE DESCRIPTION
Package Outline
21x25mm
Interconnects
255 (16x16 ball array less one)
Pitch
1.27mm
Maximum module height
3.90mm
Ball diameter
0.8mm
PACKAGE DIMENSIONS 255 BALL GRID ARRAY
TOP VIEW
BOTTOM VIEW
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2.20 (0.087)
MAX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NOTES:
1. Dimensions in millimeters and paranthetically in inches.
2. A1 corner is designated with a ball missing the array.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
12
White Electronic Designs WED3C7410E16M-400BX
ORDERING INFORMATION
WED 3 C 7410E 16M 400 B X
DEVICE GR
ADE:
GRADE:
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PA CK
A GE TYPE:
CKA
B = 255 Ceramic Ball Grid Array
CORE FREQUENC
Y (MHz)
FREQUENCY
L2 C
A CHE DENSITY
CA
DENSITY::
16Mbits = 256K x 72 SSRAM
P owerPC
:
owerPC
Type 7410E
C = MUL
TICHIP PPA
A CK
A GE
MULTICHIP
CKA
3 = PPowerPC
owerPC
owerPC
WHITE ELECTRONIC DESIGNS CORP
CORP..
PowerPC is a trademark of International Business Machine Corp.
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com