E ADVANCE INFORMATION A28F400BR-T/B 4-MBIT (256K X 16, 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY Automotive n n n n n n n n n Intel SmartVoltage Technology 5V or 12V Program/Erase 5V Read Operation Very High Performance Read 80 ns Max. Access Time, 40 ns Max. Output Enable Time n Low Power Consumption Maximum 60 mA Read Current at 5V n n x8/x16-Selectable Input/Output Bus High Performance 16- or 32-bit CPUs n Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks One 96-KB Main Block Three 128-KB Main Blocks Top or Bottom Boot Locations Hardware-Protection for Boot Block Software EEPROM Emulation with Parameter Blocks Automotive Temperature Operation –40°C to +125°C n n n Automated Word/Byte Program and Block Erase Industry-Standard Command User Interface Status Registers Erase Suspend Capability SRAM-Compatible Write Interface Automatic Power Savings Feature 1 mA Typical I CC Active Current in Static Operation Reset/Deep Power-Down Input 0.2 µA ICCTypical Provides Reset for Boot Operations Hardware Data Protection Feature Write Lockout during Power Transitions Industry-Standard Surface Mount Packaging 44-Lead PSOP: JEDEC ROM Compatible ETOX™ IV Flash Technology Extended Cycling Capability 30,000 Block Erase Cycles for Parameter Blocks 1,000 Block Erase Cycles for Main Blocks December 1996 Order Number: 290538-005 Information in this document is provided in connection with Intel products. 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Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493 E A28F400BR-T/B CONTENTS PAGE 1.0 PRODUCT FAMILY OVERVIEW .................... 5 1.1 New Features in the SmartVoltage Products ..................................................... 5 1.2 Main Features.............................................. 5 1.3 Applications ................................................. 6 1.4 Pinouts......................................................... 6 1.5 Pin Descriptions........................................... 8 2.0 PRODUCT DESCRIPTION.............................. 9 2.1 Memory Blocking Organization .................... 9 2.1.1 Boot Block............................................. 9 2.1.2 Parameter Blocks................................ 10 2.1.3 Main Blocks......................................... 10 3.0 PRODUCT FAMILY PRINCIPLES OF OPERATION ................................................ 10 3.1 Bus Operations .......................................... 12 3.2 Read Operations........................................ 12 3.2.1 Read Array.......................................... 12 3.2.2 Intelligent Identifiers ............................ 12 3.3 Write Operations........................................ 12 3.3.1 Command User Interface .................... 12 3.3.2 Status Register ................................... 15 3.3.3 Program Mode .................................... 15 3.3.4 Erase Mode......................................... 17 ADVANCE INFORMATION PAGE 3.4 Boot Block Locking ....................................20 3.4.1 VPP = VIL for Complete Protection .......20 3.4.2 WP# = VIL for Boot Block Locking .......21 3.4.3 RP# = VHH or WP# = VIH for Boot Block Unlocking..................................21 3.5 Power Consumption...................................21 3.5.1 Active Power .......................................21 3.5.2 Automatic Power Savings....................21 3.5.3 Standby Power ....................................21 3.5.4 Deep Power-Down Mode.....................21 3.6 Power-Up Operation...................................22 3.6.1 RP# Connected To System Reset .......22 3.7 Power Supply Decoupling ..........................22 3.7.1 VPP Trace on Printed Circuit Boards....22 3.7.2 VCC, VPP and RP# Transitions .............22 4.0 ABSOLUTE MAXIMUM RATINGS................23 5.0 OPERATING CONDITIONS ..........................23 5.1 VCC Voltage ...............................................23 5.2 DC Characteristics .....................................23 5.3 AC Characteristics .....................................28 APPENDIX A: Ordering Information .................35 APPENDIX B: Additional Information...............36 3 E A28F400BR-T/B REVISION HISTORY Number 4 Description -001 Initial release of datasheet -002 Changed RP# AC Characteristics Changed VLKO to 3.5V -003 Changed definition of t5VPH in Section 5.1 Changed ICCS, ICCD and VLKO specifications Added Table 11, I/O capacitance Added rise and fall time limits to Figure 7 Changed tPHEL from a Max timing to a Min -004 Increased maximum program/erase cycles for parameter blocks to 30,000 Corrected flowcharts in Figures 4 and 5 Reformated Section 5.1 Increased IIL to ± 5 µa Removed Table 15. Erase and Program Timings. Added new Table 15. Reset Timings, and Figure 13 Reset Waveforms -005 tWHAX Spec changed from 10 ns to 0 ns Minor changes throughout document ADVANCE INFORMATION E 1.0 PRODUCT FAMILY OVERVIEW This datasheet contains the specifications for the automotive version of the 28F400BR family of boot block flash memory devices. This device continues to offer the same functionality as earlier “BX” devices but adds the capability of performing program and erase operations with a 5V or 12V VPP. The A28F400BR automatically senses which voltage is applied to the VPP pin and adjusts its operation accordingly. 1.1 New Features in the SmartVoltage Products The new SmartVoltage boot block flash memory family offers identical operation as the current BX/BL 12V program products, except for the differences listed below. All other functions are equivalent to current products, including signatures, write commands, and pinouts. • WP# pin has replaced a DU pin. See Table 1 for details. • 5V program/erase operation has been added that uses proven program and erase techniques with 5V ± 10% applied to VPP. If you are designing with existing BX 12V VPP boot block products today, you should provide the capability in your board design to upgrade to these new SmartVoltage products. Follow these guidelines to ensure compatibility: 1. Connect WP# (DU on existing products) to a control signal, VCC or GND. 2. If adding a switch on VPP for write protection, switch to GND for complete write protection. 3. Allow for connecting 5V to VPP instead of 12V, if desired. 1.2 Main Features Intel’s SmartVoltage technology provides the most flexible voltage solution in the industry. SmartVoltage provides two discrete voltage supply pins, VCC for read operation, and VPP for program and erase operation. Discrete supply pins allow ADVANCE INFORMATION A28F400BR-T/B system designers to use the optimal voltage levels for their design. For program and erase operations, 5V VPP operation eliminates the need for in system voltage converters, while 12V VPP operation provides faster program and erase for situations where 12V is available, such as manufacturing or designs where 12V is already available. The 28F400 boot block flash memory family is a very high-performance, 4-Mbit (4,194,304 bit) flash memory family organized as either 256 Kwords (262,144 words) of 16 bits each or 512 Kbytes (524,288 bytes) of 8 bits each. Separately erasable blocks, including a hardwarelockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and three blocks of 131,072 bytes) define the boot block flash family architecture. See Figure 3 for memory maps. Each parameter block can be independently erased and programmed 30,000 times. Each main block can be erased 1,000 times. The boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.4 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation. Program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the CUI. Data writes are performed in word or byte increments. Each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. 5 E A28F400BR-T/B The 4-Mbit SmartVoltage boot block flash memory family is also designed with an Automatic Power Savings (APS) feature which minimizes system battery current drain, allowing for very low power designs. To provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memory’s circuitry off. This mode is controlled by the RP# pin and its usage is discussed in Section 3.5, along with other power consumption issues. Additionally, the RP# pin provides protection against unwanted command writes due to invalid system bus conditions that may occur during system reset and power-up/down sequences. Also, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system components, the flash memory could remain in a nonread mode, such as erase. Consequently, the system Reset pin should be tied to RP# to reset the memory to normal read mode upon activation of the Reset pin. The byte-wide or word-wide input/output is controlled by the BYTE# pin. See Table 1 for a detailed description of BYTE# operations, especially the usage of the DQ15/A-1 pin. The 28F400 products are available in a ROM/EPROM-compatible pinout and housed in the 44-lead PSOP (Plastic Small Outline) package. Refer to the DC Characteristics Table, Section 5.2 for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 5.3, for read, program and erase performance specifications. 1.3 The reliability of such a field upgrade is enhanced by a hardware-protected 16-Kbyte boot block. If the protection methods are implemented in the circuit design, the boot block will be unchangeable. Locating the boot-strap code in this area assures a fail-safe recovery from an update operation that failed to complete correctly. The two 8-Kbyte parameter blocks allow modification of control algorithms to reflect changes in the process or device being controlled. A variety of software algorithms allow these two blocks to behave like a standard EEPROM. Intel’s boot block architecture provides a flexible voltage solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM; the parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing RAM requirements. 1.4 Pinouts Intel’s SmartVoltage boot block architecture provides upgrade paths in every package pinout to the 8-Mbit density. The 28F400 44-lead PSOP pinout follows the industry-standard ROM/EPROM pinout, as shown in Figure 2. Applications The 4-Mbit boot block flash memory family combines high-density, low-power, highperformance, cost-effective flash memories with blocking and hardware protection capabilities. Their flexibility and versatility reduce costs throughout the product life cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. 6 When the product is in the end-user’s hands, and updates or feature enhancements become necessary or mandatory, flash memory eliminates the need to replace an assembly. The update can be performed as part of routine maintenance operation by relatively unsophisticated technicians. Pinouts for the corresponding 2-Mbit and 8-Mbit components are also provided for convenient reference. 4-Mbit pinouts are given on the chip illustration in the center, with 2-Mbit and 8-Mbit pinouts going outward from the center. ADVANCE INFORMATION E A28F400BR-T/B 5V GPIO RESET# 5V VPP A[1:18] i386™ EX Microprocessor BYTE# WP# A[0:17] CE# CS# RD# PLD Intel 28F400-T OE# GPIO WR# WE# D[0:15] DQ[0:15] GPIO RESET# PWRGOOD RP# 0538-01 Figure 1. 28F400BX Interface to Intel386™ Microprocessor 28F800 28F200 VPP A 18 A 17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# WP# NC A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ 0 DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 DQ 0 DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 V PP VPP WP# A 17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ 0 DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AB28F400 44 Lead PSOP 0.525" x 1.110" TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC 28F200 28F800 RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC 0538_02 NOTE: Pin 2 is DU for BX 12V VPP Versions. Figure 2. 44-Lead PSOP Lead Configuration for x8/x16 28F400 Is Compatible with 2 and 8 Mbit. ADVANCE INFORMATION 7 E A28F400BR-T/B 1.5 Pin Descriptions Table 1. 28F400 Pin Descriptions Symbol Type Name and Function A0–A17 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. A9 INPUT ADDRESS INPUT: When A9 is at V HH the signature mode is accessed. During this mode, A0 decodes between the manufacturer and device IDs. When BYTE# is at a logic low, only the lower byte of the signatures are read. DQ15/A-1 is a don’t care in the signature mode when BYTE# is low. DQ0–DQ7 INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched during the Write cycle. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DQ8–DQ15 INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched during the Write cycle. Outputs array data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7. CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# input stages. OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (V IL, VIH, and VHH) to control two different functions: reset/deep power-down mode and boot block unlocking. It is backwards-compatible with the 28F400BX/BL. When RP# is at logic low, the device is in reset/deep power-down mode, which puts the outputs at High-Z, resets the Write State Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device defaults to the read array mode. When RP# is at VHH, the boot block is unlocked and can be programmed or erased. This overrides any control from the WP# input. 8 ADVANCE INFORMATION E Symbol WP# A28F400BR-T/B Table 1. 28F400 Pin Descriptions (Continued) Type INPUT Name and Function WRITE PROTECT: Provides a method for unlocking the boot block in a system without a 12V supply. When WP# is at logic low, the boot block is locked, preventing program and erase operations to the boot block. If a program or erase operation is attempted on the boot block when WP# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the Status Register to indicate the operation failed. When WP# is at logic high, the boot block is unlocked and can be programmed or erased. NOTE: This feature is overridden and the boot block unlocked when RP# is at VHH. See Section 3.4 for details on write protection. BYTE# INPUT BYTE# ENABLE: Controls whether the device operates in the byte-wide (x8) mode or the word (x16) mode. The BYTE# input must be controlled at CMOS levels to meet the CMOS current specification in the standby mode. When BYTE# is at logic low, the byte-wide mode is enabled. A 19-bit address is applied on A–1 to A17, and 8 bits of data is read and written on DQ0–DQ7. When BYTE# is at logic high, the word-wide mode is enable. An 18-bit address is applied on A0 to A17 and 16 bits of data is read and written on DQ0–DQ15. VCC DEVICE POWER SUPPLY: 5.0V ± 10% VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must be applied to this pin. When V PP < VPPLK all blocks are locked and protected against Program and Erase commands. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating. 2.0 2.1 PRODUCT DESCRIPTION Memory Blocking Organization This product family features an asymmetricallyblocked architecture enhancing system memory integration. Each block can be erased independently. The block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. For the address locations of the blocks, see the memory maps in Figure 3. ADVANCE INFORMATION 2.1.1 ONE 16-KB BOOT BLOCK The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontrollerbased system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to accommodate different microprocessor protocols for boot code location. This boot block features hardware controllable write protection to protect the crucial microprocessor boot code from accidental erasure. The protection of the boot block is controlled using a combination of the VPP, RP#, and WP# pins, as is detailed in Table 8. 9 E A28F400BR-T/B 2.1.2 TWO 8-KB PARAMETER BLOCKS The boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the byterewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel’s AP-604, Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM. Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable. 2.1.3 ONE 96-KB + THREE 128-KB MAIN BLOCKS After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each 4-Mbit device contains one 96-Kbyte (98,304 byte) block and three 128-Kbyte (131,072 byte) blocks. See the memory maps for each device for more information. 3.0 PRODUCT FAMILY PRINCIPLES OF OPERATION Flash memory augments EPROM functionality with in-circuit electrical program and erase. The boot block flash family utilizes a Command User 3FFFFH 3E000H 3DFFFH 3D000H 3CFFFH 3C000H 3BFFFH 16-Kbyte BOOT BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility. When VPP < VPPLK, the device will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI or through the standard EPROM A9 high voltage access (VID) for PROM programming equipment. The same EPROM read, standby and output disable functions are available when 5V or 12V is applied to the VPP pin. In addition, 5V or 12V on VPP allows program and erase of the device. All functions associated with altering memory contents: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI. The purpose of the Write State Machine (WSM) is to completely automate the program and erasure of the device. The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register. The CUI will handle the WE# interface to the data and address latches, as well as system software requests for status while the WSM is in operation. 3FFFFH 128-Kbyte MAIN BLOCK 30000H 2FFFFH 96-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 128-Kbyte MAIN BLOCK 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 30000H 2FFFFH 20000H 1FFFFH 10000H 0FFFFH 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 96-Kbyte MAIN BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 16-Kbyte BOOT BLOCK 00000H 00000H 28F400-B 28F400-T 0538-03 Figure 3. 28F400-T/B Memory Maps 10 ADVANCE INFORMATION E A28F400BR-T/B Table 2. Bus Operations for Word-Wide Mode (BYTE# = VIH) Mode Read Notes RP# CE# OE# WE# A9 A0 VPP DQ0–15 1,2,3 VIH VIL VIL VIH X X X DOUT VIH VIL VIH VIH X X X High Z Output Disable Standby VIH VIH X X X X X High Z Deep Power-Down 9 VIL X X X X X X High Z Intelligent Identifier (Mfr.) 4 VIH VIL VIL VIH VID VIL X 0089 H 4,5 VIH VIL VIL VIH VID VIH X See Table 4 6,7,8 VIH VIL VIH VIL X X X DIN Intelligent Identifier (Device) Write Table 3. Bus Operations for Byte-Wide Mode (BYTE# = VIL) Mode Notes RP# CE# OE# WE# A9 A0 A-1 VPP DQ0–7 DQ8–14 1,2,3 VIH VIL VIL VIH X X X X DOUT High Z Output Disable VIH VIL VIH VIH X X X X High Z High Z Standby VIH VIH X X X X X X High Z High Z Read Deep PowerDown 9 VIL X X X X X X X High Z High Z Intelligent Identifier (Mfr.) 4 VIH VIL VIL VIH VID VIL X X 89H High Z 4,5 VIH VIL VIL VIH VID VIH X X See Table 4 High Z 6,7,8 VIH VIL VIH VIL X X X X DIN High Z Intelligent Identifier (Device) Write NOTES: 1. Refer to DC Characteristics. 2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP. 3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages. 4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A17 = X, A1–A18 = X. 5. See Table 4 of device IDs. 6. Refer to Table 5 for valid DIN during a write operation. 7. Command writes for Block Erase or Word/Byte Program are only executed when VPP = VPPH1 or VPPH2. 8. To program or erase the boot block, hold RP# at VHH or WP# at VIH. 9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified. ADVANCE INFORMATION 11 E A28F400BR-T/B 3.1 Bus Operations Flash memory reads, programs and erases insystem via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized in Tables 2 and 3. 3.2 Read Operations The boot block flash device has three user read modes: array, intelligent identifier, and status register. Status register read mode will be discussed, in detail, in Section 3.3.2. 3.2.1 READ ARRAY When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. When the device is in the read array mode, five control signals must be controlled to obtain data at the outputs. • WE# must be logic high (VIH) • CE# must be logic low (VIL) • OE must be logic low (V IL) • RP# must be logic high (VIH) • BYTE# must be logic high or logic low. In addition, the address of the desired location must be applied to the address pins. Refer to Figures 10 and 11 for the exact sequence and timing of these signals. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to the CUI before reads can take place. 3.2.1.1 Output Control With OE# at logic-high level (VIH), the output from the device is disabled and data Input/Output pins (DQ[0:15] or DQ[0:7]) are tri-stated. 12 3.2.1.2 Input Control With WE# at logic-high level (VIH), input to the device is disabled. 3.2.2 INTELLIGENT IDENTIFIERS The intelligent identifiers of the SmartVoltage boot block components are identical to the boot block products that operate only at 12V VPP. The manufacturer and device codes are read via the CUI or by taking the A9 pin to VID. Writing 90H to the CUI places the device into intelligent identifier read mode. In this mode, A0 = 0 outputs the manufacturer’s identification code and A0 = 1 outputs the device code. When BYTE# is at a logic low, only the lower byte of the above signatures is read and DQ15/A-1 is a “don’t care” during intelligent identifier mode. See the table below for product signatures. A Read Array command must be written to the memory to return to the read array mode. Table 4. Intelligent Identifier Table Product Mfr. ID Device ID -T -B (Top Boot) (Bottom Boot) 28F400 3.3 3.3.1 0089 H 4470 H 4471 H WRITE OPERATIONS COMMAND USER INTERFACE (CUI) The Command User Interface (CUI) serves as the interface between the microprocessor and the internal chip controller. Commands are written to the CUI using standard microprocessor write timings. The available commands are Read Array, Read Intelligent Identifier, Read Status Register, Clear Status Register, Program and Erase (summarized in Tables 5 and 6). For Read commands, the CUI points the read path at either the array, the intelligent identifier, or the Status Register depending on the command received. For Program or Erase commands, the CUI informs the Write State Machine (WSM) that a program or erase has been requested. During the execution of a Program command, the WSM will control the programming sequences and the CUI will only respond to status reads. During an erase cycle, the ADVANCE INFORMATION E A28F400BR-T/B CUI will respond to status reads and erase suspend. After the WSM has completed its task, it will set the WSM Status bit to a “1,” which will also allow the CUI to respond to its full command set. Note that after the WSM has returned control to the CUI, the CUI will stay in the current command state until it receives another command. Table 5. Command Set Codes and Corresponding Device Mode Command Codes Device Mode 00 Invalid Reserved 10 Alternate Program Set-Up 20 Erase Set-Up 40 Program Set-Up 50 Clear Status Register 70 Read Status Register 90 Intelligent Identifier B0 Erase Suspend D0 Erase Resume/Erase Confirm FF Read Array Read Array (FFH) This single write cycle command points the read path at the array. If the host CPU performs a CE#/OE#-controlled Read immediately following a two-write sequence that started the WSM, then the device will output Status Register contents. If the Read Array command is given after the Erase Setup command, the device will reset to read the array. A two Read Array command sequence (FFH) is required to reset to Read Array after the Program Setup command. Intelligent Identifier (90H) After this command is executed, the CUI points the output path to the intelligent identifier circuits. Only intelligent identifier values at addresses 0 and 1 can be read (only address A0 is used in this mode, all other address inputs are ignored). Read Status Register (70H) This is one of the two commands that is executable while the WSM is operating. After this command is written, a read of the device will output the contents of the Status Register, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. 3.3.1.1 Command Function Description Device operations are selected by writing specific commands into the CUI. Table 5 defines the available commands. Invalid/Reserved These are unassigned commands and should not be used. Intel reserves the right to redefine these codes for future functions. ADVANCE INFORMATION Clear Status Register (50H) The WSM can only set the Program Status and Erase Status bits in the Status Register to “1,” it cannot clear them to “0.” Two reasons exist for operating the Status Register in this fashion. The first is synchronization. Since the WSM does not know when the host CPU has read the Status Register, it would not know when to clear the status bits. Second, if the CPU is programming a string of bytes, it may be more efficient to query the Status Register after programming the string. Thus, if any errors exist while programming the string, the Status Register will return the accumulated error status. 13 E A28F400BR-T/B Table 6. Command Bus Definitions Notes Command Read Array Intelligent Identifier Read Status Register First Bus Cycle Second Bus Cycle 8 Oper Addr Data 1 Write X FFH 2,4 Write X 3 Write Clear Status Register Oper Addr Data 90H Read IA IID X 70H Read X SRD Write X 50H Word/Byte Program 6,7 Write PA 40H Write PA PD Alternate Word/Byte Program 6,7 Write PA 10H Write PA PD Block Erase/Confirm 5 Write BA 20H Write BA D0H Write X B0H Write X D0H Erase Suspend/Resume ADDRESS BA = Block Address IA = Identifier Address PA = Program Address X= Don’t Care DATA SRD = Status Register Data IID = Identifier Data PD = Program Data NOTES: 1. 2. 3. 4. 5. 6. 7. 8. Bus operations are defined in Tables 2 and 3. IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code. SRD = Data read from Status Register. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. BA = Address within the block being erased. PA = Address to be programmed. PD = Data to be programmed at location WD. Either 40H or 10H commands is valid. When writing commands to the device, the upper data bus [DQ8–DQ15] = X (28F400 only) which is either VCC or VSS, to minimize current draw. Program Setup (40H or 10H) This command simply sets the CUI into a state such that the next write will load the Address and Data registers. After this command is executed, the outputs default to the Status Register. A two Read Array command sequence (FFH) is required to reset to Read Array after the Program Setup command. Program The second write after the Program Setup command, will latch addresses and data. Also, the CUI initiates the WSM to begin execution of the 14 program algorithm. The device outputs Status Register data when OE# is enabled. A Read Array command is required after programming, to read array data. Erase Setup (20H) Prepares the CUI for the Erase Confirm command. No other action is taken. If the next command is not an Erase Confirm command, then the CUI will set both the Program Status and Erase Status bits of the Status Register to a “1,” place the device into the Read Status Register state, and wait for another command. ADVANCE INFORMATION E A28F400BR-T/B Erase Confirm (D0H) the CUI. A Read Array command must be written to the CUI to return to the read array mode. If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at the same time closing the address and data latches, and respond only to the Read Status Register and Erase Suspend commands. While the WSM is executing, the device will output Status Register data when OE# is toggled low. Status Register data can only be updated by toggling either OE# or CE# low. The Status Register bits are output on DQ[0:7], whether the device is in the byte-wide (x8) or wordwide (x16) mode. In the word-wide mode the upper byte, DQ[8:15], is set to 00H during a Read Status command. In the byte-wide mode, DQ[8:14] are tristated and DQ15/A-1 retains the low order address function. Erase Suspend (B0H) This command is only valid while the WSM is executing an erase operation, and therefore will only be responded to during an erase operation. After this command has been executed, the CUI will set an output that directs the WSM to suspend erase operations, and then respond only to Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend state, it will set an output into the CUI which allows the CUI to respond to the Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will also set the WSM Status bit to a “1.” The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip, if it is made active. During a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and clear the WSM Status Bit to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect under any other conditions. 3.3.2 STATUS REGISTER The device contains a Status Register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status command to the CUI. After writing this command, all subsequent read operations output data from the Status Register until another command is written to ADVANCE INFORMATION Important: The contents of the Status Register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the Status Register change while reading the Status Register. CE# or OE# must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident from the Status Register. When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. 3.3.2.1 Clearing the Status Register The WSM sets status bits “3” through “7” to “1,” and clears bits “6” and “7” to “0,” but cannot clear status bits “3” through “5” to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The Status Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. To clear the Status Register, the Clear Status Register command is written to the CUI. Then, any other command may be issued to the CUI. Note, again, that before a read cycle can be initiated, a Read Array command must be written to the CUI to specify whether the read data is to come from the Memory Array, Status Register, or Intelligent Identifier. 3.3.3 PROGRAM MODE Programming is executed using a two-write sequence. The Program Setup command is written to the CUI followed by a second write which 15 E A28F400BR-T/B specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to: If the user attempts to program “1”s, there will be no change of the memory cell content and no error occurs. 1. Program the desired bits of the addressed memory word or byte. Similar to erasure, the Status Register indicates whether programming is complete. While the program sequence is executing, bit 7 of the Status Register is a “0.” The Status Register can be polled by toggling either CE# or OE# to determine when the program sequence is complete. Only the Read Status Register command is valid while programming is active. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte or word being changed to a “0.” Table 7. Status Register Bit Definition WSMS ESS ES DWS VPPS R R R 7 6 5 4 3 2 1 0 NOTES: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy Write State Machine bit must first be checked to determine Byte/Word program or Block Erase completion, before the Program or Erase Status bits are checked for success. SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an Erase Resume command is issued. SR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase When this bit is set to “1,” WSM has applied the maximum number of erase pulses to the block and is still unable to successfully verify block erasure. SR.4 = PROGRAM STATUS 1 = Error in Byte/Word Program 0 = Successful Byte/Word Program When this bit is set to “1,” WSM has attempted but failed to program a byte or word. SR.3 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPLK and VPPH. SR.2–SR.0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register. 16 ADVANCE INFORMATION E When programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. If bit 3 is set to a “1,” then VPP was not within acceptable limits, and the WSM did not execute the programming sequence. If the program operation fails, Bit 4 of the Status Register will be set within 3.3 ms, as determined by the time-out of the WSM. The Status Register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given the Read Array command. 3.3.4 ERASE MODE Erasure of a single block is initiated by writing the Erase Setup and Erase Confirm commands to the CUI, along with the addresses identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” The WSM will execute a sequence of internally timed events to: 1. Program all bits within the block to “0.” 2. Verify that all bits within the block are sufficiently programmed to “0.” 3. Erase all bits within the block. 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the Status Register is a “0.” When the Status Register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erase operation was unsuccessful, bit 5 of the Status Register will be set to a “1,” indicating an Erase Failure. If VPP was not within ADVANCE INFORMATION A28F400BR-T/B acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, bit 5 of the Status Register is set to a “1” to indicate an Erase Failure, and bit 3 is set to a “1” to identify that VPP supply voltage was not within acceptable limits. The Status Register should be cleared before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given the Read Array command. 3.3.4.1 Suspending and Resuming Erase Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from another block of the memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a pre-determined point in the erase algorithm. The Status Register must then be read to determine if the erase operation has been suspended. At this point, a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended. The only other valid command at this time is the Erase Resume command or Read Status Register command. During erase suspend mode, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. To resume the erase operation, the chip must be enabled by taking CE# to VIL, then issuing the Erase Resume command. When the Erase Resume command is given, the WSM will continue with the erase sequence and complete erasing the block. As with the end of a standard erase operation, the Status Register must be read, cleared, and the next instruction issued in order to continue. 17 E A28F400BR-T/B Start Bus Operation Write 40H, Word/Byte Address Command Write Setup Program Data = 40H Addr = Word/Byte to Program Write Program Data = Data to Program Addr = Location to Program Write Word/Byte Data/Address Read Status Register Data Toggle CE# or OE# to Update SRD. Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy NO SR.7 = 1 ? Comments Repeat for subsequent word/byte program operations. SR Full Status Check can be done after each word/byte program, or after a sequence of word/byte programs. Write FFH after the last program operation to reset device to read array mode. YES Full Status Check if Desired Word/Byte Program Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) SR.3= 1 1 SR.4 = 0 Word/Byte Program Successful Word/Byte Program Error Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 1 = Word/Byte Program Error VPP Range Error 0 Command SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register command, in cases where multiple bytes are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0538_04 Figure 4. Automated Word/Byte Programming Flowchart 18 ADVANCE INFORMATION E A28F400BR-T/B Start Bus Operation Write 20H, Block Address Command Write Erase Setup Data = 20H Addr = Within Block to be Erased Write Erase Confirm Data = D0H Addr = Within Block to be Erased Write D0H and Block Address Read Read Status Register Suspend Erase Loop Status Register Data Toggle CE# or OE# to Update Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy NO 0 SR.7 = Suspend Erase Comments YES Repeat for subsequent block erasures. Full Status Check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to reset device to read array mode. 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) SR.3 = 1 Command Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error VPP Range Error 0 1 SR.4,5 = Comments Command Sequence Error 0 1 SR.5 = Block Erase Error 0 SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erase before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Block Erase Successful 0538_05 Figure 5. Automated Block Erase Flowchart ADVANCE INFORMATION 19 E A28F400BR-T/B Start Bus Operation Write Write B0H Command Erase Suspend Read Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Erase Suspended 0 = Erase Completed 0 1 Write CSR.6 = 0 Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update SRD Addr = X Read Status Register SR.7 = Comments Read Array Erase Completed Read Data = FFH Addr = X Read array data from block other than the one being erased. 1 Write Write FFH Erase Resume Data = D0H Addr = X Read Array Data Done Reading NO YES Write D0H Write FFH Erase Resumed Read Array Data 0538_06 Figure 6. Erase Suspend/Resume Flowchart 3.4 Boot Block Locking The boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blocks are programmed and erased independently as necessary. Only the boot block can be locked independently from the other blocks. 20 3.4.1 VPP = VIL FOR COMPLETE PROTECTION For complete write protection of all blocks in the flash device, the VPP programming voltage can be held low. When VPP is below VPPLK, any program or erase operation will result in a error in the Status Register. ADVANCE INFORMATION E 3.4.2 A28F400BR-T/B WP# = VIL FOR BOOT BLOCK LOCKING When WP# = VIL, the boot block is locked and any program or erase operation will result in an error in the Status Register. All other blocks remain unlocked in this condition and can be programmed or erased normally. Note that this feature is overridden and the boot block unlocked when RP# = VHH. 3.4.3 RP# = VHH OR WP# = VIH FOR BOOT BLOCK UNLOCKING Two methods can be used to unlock the boot block: 1. WP# = VIH 2. RP# = VHH If both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. The Truth Table, Table 8, clearly defines the write protection methods. Table 8. Write Protection Truth Table for SmartVoltage Boot Block Family VPP RP# WP# VIL X X All Blocks Locked ≥ VPPLK VIL X All Blocks Locked (Reset) ≥ VPPLK VHH X All Blocks Unlocked ≥ VPPLK VIH VIL Boot Block Locked ≥ VPPLK VIH VIH All Blocks Unlocked 3.5 Write Protection Provided Power Consumption Reduction Control (PRC) circuitry which allows the device to put itself into a low current state when it is not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical ICC current is less than 1 mA. The device stays in this static state with outputs valid until a new location is read. 3.5.3 STANDBY POWER With CE# at logic-high level (VIH), and the CUI in read mode, the memory is placed in standby mode. The standby operation disables much of the device’s circuitry and substantially reduces device power consumption. The outputs (DQ[0:15] or DQ[0:7]) are placed in a high-impedance state independent of the status of the OE# signal. When CE# is at logic-high level during erase or program functions, the devices will continue to perform the erase or program function and consume erase or program active power until erase or program is completed. 3.5.4 DEEP POWER-DOWN MODE The SmartVoltage boot block family supports a low typical ICC in deep power-down mode. The device has an RP# pin which places the device in the deep power-down mode. When RP# is at a logic-low (GND ± 0.2V), all circuits are turned off in order to save power. (Note: BYTE# pin must be at CMOS levels to achieve the most deep power-down current savings.) During read modes, the RP# pin going low deselects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of tPHQV. (See the AC Characteristics table for specification numbers.) With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode. Refer to the DC Characteristics table for ICC current values. During erase or program modes, RP# low will abort either erase or program operation. The contents of the memory are no longer valid, as the data has been corrupted by the RP# function. As in the read mode above, all internal circuitry is turned off to achieve the power savings. 3.5.2 RP# transitions to VIL, or turning power off to the device will clear the Status Register. 3.5.1 ACTIVE POWER AUTOMATIC POWER SAVINGS (APS) Automatic Power Savings (APS) is a low-power feature during active mode of operation. The boot block flash memory family incorporates Power ADVANCE INFORMATION 21 E A28F400BR-T/B 3.6 Power-Up Operation The device is designed to offer protection against accidental block erasure or programming during power transitions. Upon power-up, the device is indifferent as to which power supply, VPP or VCC, powers-up first. Power supply sequencing is not required. A system designer must guard against spurious programming for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally, the device is disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power up/down, invalid bus conditions that may occur can be masked. This feature provides yet another level of memory protection. 3.6.1 RP# CONNECTED TO SYSTEM RESET The use of RP# during system reset is important with automated program/erase devices. When the system comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during program/erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3.7 Power Supply Decoupling Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Active current levels (I CCR) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 VPP TRACE ON PRINTED CIRCUIT BOARDS Writing to flash memories while they reside in the target system, requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to the VCC power supply trace. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 3.7.2 VCC, VPP AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after VCC transitions above VLKO (Lockout voltage), is read array mode. After any word/byte program or block erase operation is complete, and even after VPP transitions down to VPPLK, the CUI must be reset to read array mode via the Read Array command when accesses to the flash memory are desired. 22 ADVANCE INFORMATION E 4.0 A28F400BR-T/B ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read ...........................–40°C to +125°C During Block Erase and Word/Byte Program .........–40°C to +125°C Temperature Under Bias ........–40°C to +125°C Storage Temperature....................–65°C to +125°C Voltage on Any Pin (except VCC, VPP, A9 and RP#) with Respect to GND..............–2.0V to +7.0V(1) Voltage on Pin RP# or Pin A9 with Respect to GND......... –2.0V to +13.5V(1,2) VPP Program Voltage with Respect to GND during Block Erase and Word/Byte Program .... –2.0V to +14.0V(1,2) VCC Supply Voltage with Respect to GND..............–2.0V to +7.0V(1) Output Short Circuit Current ................... 100 mA (3) 5.0 NOTICE: This datasheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. NOTES: 1. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. Maximum DC voltage on RP# or A9 may overshoot to 13.5V for periods <20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. OPERATING CONDITIONS Table 9. Temperature and VCC Operating Conditions Min Max Units TA Symbol Operating Temperature –40 +125 °C VCC VCC Supply Voltage (10%) 4.50 5.50 Volts 5.1 Parameter Notes Applying VCC Voltages If the VCC ramp rate is greater than 0.01 V/µs, a delay of 2 µs is required before any device operation can be initiated. This includes array or status read, command writes and program or erase operations. The 2 µs are measure beginning from the time VCC reaches VCCMIN (4.5V). This delay is not tied to the operation of the reset input. It is recommended that the device be held in reset (RP# = GND) while VCC is less than V CCMIN. If the VCC ramp rate is less than 0.01 V/µs, no delay is required once VCC has reached VCCMIN. ADVANCE INFORMATION 23 E A28F400BR-T/B 5.2 DC Characteristics Table 10. DC Characteristics: Automotive Temperature Operation Symbol Parameter Notes Min Typ Max Unit Test Conditions IIL Input Load Current 1 ± 5.0 µA VCC = VCCMax VIN = VCC or GND ILO Output Leakage Current 1 ± 10 µA VCC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 0.8 2.5 mA VCC = VCC Max CE# = RP# = BYTE# = VIH 70 250 µA VCC = VCC Max CE# = RP# = WP# = VCC ± 0.2V 1 0.2 105 µA 1,5,6 50 65 mA VCC = VCC Max VIN = VCC or GND RP# = GND ± 0.2V CMOS VCC = VCC Max CE = VIL f = 10 MHz (5V) 5 MHz (3.3V) IOUT = 0 mA Inputs = GND ± 0.2V or VCC ± 0.2V 55 70 mA TTL VCC = VCC Max CE# = VIL f = 10 MHz IOUT = 0 mA mA VPP = VPPH1 (at 5V) ICCD VCC Deep Power-Down Current ICCR VCC Read Current for Word or Byte 1,3 Inputs = VIL or VIH ICCW VCC Program Current for Word or Byte 1,4 25 50 Program in Progress 20 45 mA VPP = VPPH2 (at 12V) Program in Progress 24 ADVANCE INFORMATION E A28F400BR-T/B Table 10. DC Characteristics: Automotive Temperature Operation (Continued) Symbol ICCE Parameter VCC Erase Current Notes Min 1,4 Typ Max Unit Test Conditions 22 45 mA VPP = VPPH1 (at 5V) Block Erase in Progress 18 40 mA VPP = VPPH2 (at 12V) Block Erase in Progress 1,2 5 12.0 mA CE# = VIH Block Erase Suspend VPP = VPPH1 (at 5V) VPP Standby Current 1 ±5 ± 15 µA VPP ≤ VCC IPPD VPP Deep Power-Down Current 1 0.2 10 µA RP# = GND ± 0.2V IPPR VPP Read Current 1 50 200 µA VPP >VCC IPPW VPP Program Current for Word or Byte 1 13 30 mA VPP = VPPH VPP = VPPH1 (at 5V) Program in Progress 8 25 mA VPP = VPPH VPP = VPPH2 (at 12V) Program in Progress 15 25 mA VPP = VPPH VPP = VPPH1 (at 5V) Block Erase in Progress 10 20 mA VPP = VPPH VPP = VPPH2 (at 12V) Block Erase in Progress 50 200 µA VPP = VPPH Block Erase Suspend in Progress RP# = VHH VPP = 12V ICCES VCC Erase Suspend Current IPPS IPPE VPP Erase Current 1 IPPES VPP Erase Suspend Current IRP# RP# Boot Block Unlock Current 1,4 500 µA IID A9 Intelligent Identifier Current 1,4 500 µA VID A9 Intelligent Identifier Voltage 11.4 12.6 V VIL Input Low Voltage –0.5 0.8 V ADVANCE INFORMATION 1 A9 = VID 25 E A28F400BR-T/B Table 10. DC Characteristics: Automotive Temperature Operation (Continued) Symbol Parameter VIH Input High Voltage VOL Output Low Voltage (TTL) VOH1 Output High Voltage (TTL) VOH2 Output High Voltage (CMOS) VPPLK VPP Lock-Out Voltage VPPH1 Notes Min 2.0 3 Typ Max Unit VCC ± 0.5V V 0.45 V 2.4 V VCC – 0.4V V Test Conditions VCC = VCC Min VPP = 12V IOL = 5.8 mA VCC = VCC Min IOH = –1.5 mA VCC = VCC Min IOH = –100 µA 0.0 1.5 V Complete Write Protection VPP (Program/Erase Operations) 4.5 5.5 V VPP at 5V VPPH2 VPP (Program/Erase Operations) 11.4 12.6 V VPP at 12V VLKO VCC Program/Erase Lock Voltage 2.0 VHH RP# Unlock Voltage 11.4 V 12.6 V Boot Block Program/Erase VPP = 12V Table 11. Capacitance (TA - 25°C, f = 1 MHz) Symbol Parameter Note Typ Max Unit Conditions CIN Input Capacitance 4 6 8 pF VIN = 0V COUT Output Capacitance 4 10 12 pF VOUT = 0V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = +25°C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device de-selected. If the devices is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases and word/byte program operations are inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation. 6. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH. 26 ADVANCE INFORMATION E A28F400BR-T/B 2.4 2.0 INPUT 2.0 OUTPUT TEST POINTS 0.8 0.45 0.8 0538-08 NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) ≤ 10 ns. Figure 7. 7V Inputs and Measurement Points VCC 585 DEVICE UNDER TEST OUT CL 394 0538-09 NOTE: CL = 100 pF, includes Jig Capacitance Figure 8. 5V Standard Test Configuration ADVANCE INFORMATION 27 E A28F400BR-T/B 5.3 AC Characteristics Table 12. AC Characteristics: Read Only Operations(1) (Automotive Temperature) Symbol Parameter Note Min Max 80 Unit tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV CE# to Output Delay tPHQV RP# to Output Delay tGLQV OE# to Output Delay 2 tELQX CE# to Output in Low Z 3 tEHQZ CE# to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# to Output in High Z 3 tOH Output Hold from Address CE#, or OE# Change Whichever Occurs First 3 tELFL CE# Low to BYTE High or Low 3 5 ns tAVFL Address to BYTE# High or Low 3 5 ns tFLQV BYTE# to Output Delay 3,4 80 ns BYTE# Low to Output in High Z 3 30 ns 2 ns 80 ns 80 ns 550 ns 40 ns 0 ns 30 0 ns ns 30 0 ns ns tELFH tFHQV tFLQZ NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE. 3. Sampled, but not 100% tested. 4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A–1 becomes valid. 5. See 5V Standard Test Configuration. (Figure 9) 28 ADVANCE INFORMATION E A28F400BR-T/B CE# (E) Data Valid Device and Address Selection VIH ADDRESSES (A) VIL Standby Address Stable t AVAV VIH VIL t EHQZ VIH OE# (G) VIL t GHQZ VIH WE# (W) VIL t GLQX VOH DATA (D/Q) VOL RP#(P) t GLQV t ELQX High Z t OH t ELQV High Z Valid Output t AVQV VIH t PHQV VIL 0538_10 Figure 9. AC Waveforms for Read Operations VIH ADDRESSES (A) VIL CE# Standby Address Stable t AVAV VIH VIL OE# Data Valid Device Address Selection t EHQZ t AVFL VIH t ELFL VIL BYTE# t GHQZ VIH VIL VOH DATA (D/Q) t GLQV t ELQV t GLQX High Z t ELQX Data Output on DQ0-DQ7 (DQ0-DQ7) VOL DATA (D/Q) VOH High Z VOL (DQ15-A1) Data Output on DQ0-DQ7 High Z t AVQV t FLQZ High Z High Z Data Output on DQ8-DQ14 (DQ8-DQ14) VOH t OH t AVQV Data Output on DQ15 Address Input High Z VOL 0538_11 Figure 10. BYTE# Timing Diagram for Both Read and Write Operations with V CC at 5V ADVANCE INFORMATION 29 E A28F400BR-T/B Table 13. AC Characteristics: WE#–Controlled Write Operations(1) (Automotive Temperature) Symbol Parameter Notes Min Max Unit tAVAV Write Cycle Time 80 ns tPHWL RP# High Recovery to WE# Going Low 450 ns tELWL CE# Setup to WE# Going Low 0 ns tPHHWH Boot Block Lock Setup to WE# Going High 6,8 100 ns tVPWH VPP Setup to WE# Going High 5,8 100 ns tAVWH Address Setup to WE# Going High 3 60 ns tDVWH Data Setup to WE# Going High 4 60 ns tWLWH WE# Pulse Width 60 ns tWHDX Data Hold Time from WE# High 4 0 ns tWHAX Address Hold Time from WE# High 3 0 ns tWHEH CE# Hold Time from WE# High 10 ns tWHWL WE# Pulse Width High 20 ns tWHQV1 Duration of Word/Byte Program Operation 2,5 7 µs tWHQV2 Duration of Erase Operation (Boot) 2,5,6 0.4 s tWHQV3 Duration of Erase Operation (Parameter) 2,5 0.4 s tWHQV4 Duration of Erase Operation (Main) 2,5 0.7 s tQWL VPP Hold from Valid SRD 5,8 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 ns tPHBR Boot-Block Relock Delay 7,8 100 ns NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. Refer to command definition table for valid AIN. 4. Refer to command definition table for valid DIN. 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 =1) 6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful relocking of the boot block. 8. Sampled, but not 100% tested. 9. VPP at 5.0V. 10. VPP at 12.0V. 11. See 5V Standard Test Configuration. 30 ADVANCE INFORMATION E A28F400BR-T/B 1 VIH 2 3 AIN ADDRESSES (A) VIL VIH t AVAV 4 5 6 AIN tAVWH t WHAX CE# (E) VIL OE# (G) VIH t ELWL tWHEH VIL t WHWL VIH t WHQV1,2,3,4 WE# (W) VIL VIH DATA (D/Q) High Z VIL 6.5V RP# (P) VHH t WLWH t DVWH t WHDX DIN t PHWL DIN Valid SRD DIN t PHHWH tQVPH t VPWH t QVVL VIH VIL VIH WP# VIL VPPH 2 VPPH1 V (V) V PP PPLK VIL 0538_12 NOTES: 1. VCC Power-Up and Standby. 2. Write Program or Erase Setup Command. 3. Write Valid Address and Data (Program) or Erase Confirm Command. 4. Automated Program or Erase Delay. 5. Read Status Register Data. 6. Write Read Array Command. Figure 11. AC Waveforms for Write Operations (WE#-Controlled Writes) ADVANCE INFORMATION 31 A28F400BR-T/B Table 14. AC Characteristics: CE#–Controlled Write Operations (1,12) Symbol Parameter Notes Min Max E Unit tAVAV Write Cycle Time 80 ns tPHEL RP# High Recovery to CE# Going Low 450 ns tWLEL WE# Setup to CE# Going Low 0 ns tPHHEH Boot Block Lock Setup to CE# Going High 6,8 100 ns tVPEH VPP Setup to CE# Going High 5,8 100 ns tAVEH Address Setup to CE# Going High 60 ns tDVEH Data Setup to CE# Going High 3 60 ns tELEH CE# Pulse Width 4 60 ns tEHDX Data Hold Time from CE# High 0 ns tEHAX Address Hold Time from CE# High 4 10 ns tEHWH WE# Hold Time from CE# High 3 10 ns tEHEL CE# Pulse Width High 20 ns tEHQV1 Duration of Word/Byte Program Operation tEHQV2 Duration of Erase Operation (Boot) tEHQV3 2,5 7 µs 2,5,6 0.4 s Duration of Erase Operation (Parameter) 2,5 0.4 s tEHQV4 Duration of Erase Operation (Main) 2,5 0.7 s tQWL VPP Hold from Valid SRD 5,8 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 ns tPHBR Boot-Block Relock Delay 7,8 100 ns NOTES: See WE# Controlled Write Operations for notes 1 through 11. 12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform. 32 ADVANCE INFORMATION E A28F400BR-T/B 1 VIH 2 3 AIN ADDRESSES (A) VIL VIH 4 5 6 AIN t AVAV t AVEH t EHAX WE# (E) VIL OE# (G) VIH t WLEL tEHWH VIL t VIH t EHQV1,2,3,4 EHEL CE# (W) VIL VIH DATA (D/Q) High Z VIL 6.5V RP# (P) t ELEH t DVEH t EHDX DIN t PHWL VHH Valid SRD DIN DIN tPHHEH tQVPH t VPEH t QVVL VIH VIL VIH WP# VIL VPPH 2 VPPH1 V (V) V PP PPLK VIL 0538_13 NOTES: 1. VCC Power-Up and Standby. 2. Write Program or Erase Setup Command. 3. Write Valid Address and Data (Program) or Erase Confirm Command. 4. Automated Program or Erase Delay. 5. Read Status Register Data. 6. Write Read Array Command. Figure 12. Alternate AC Waveforms for Write and Erase Operations (CE#-Controlled Writes) Table 15. AC Characteristics: Reset Timings(1) Symbol Parameter tPLPH Reset Pulse Duration tPLQZ RP# Low to Output in High Z Notes Min Max 60 Unit ns 60 ns NOTE: Refer to Figure 13 for waveform. ADVANCE INFORMATION 33 E A28F400BR-T/B t PLPH V IH RP# (P) VIL t PLQZ V IH DATA (D/Q) VIL 0538_15 Figure 13. Reset Waveforms 34 ADVANCE INFORMATION E A28F400BR-T/B APPENDIX A ORDERING INFORMATION AB 2 8 F 4 0 0 BR - T 8 0 Operating Temperature A = Automotive Temp Access Speed (ns) Package B = PSOP T = Top Boot B = Bottom Boot Product line designator for all Intel Flash products Voltage Options (VPP ) R = (5 or 12) Density / Organization X00 = x8/x16 Selectable(X = 2, 4, 8) Architecture B = Boot Block 0538_14 VALID COMBINATIONS: AB28F400BR-T80 AB28F400BR-B80 ADVANCE INFORMATION 35 A28F400BR-T/B APPENDIX B ADDITIONAL INFORMATION(1,2) Order Number E Document 292130 AB-57 Boot Block Architecture for Safe Firmware Updates 292154 AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family 292098 AP-363 Extended Flash BIOS Concepts for Portable Computers 292148 AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM 290448 28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet 290449 28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet 290450 28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet 290451 28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. 36 ADVANCE INFORMATION