SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 • • • • • DW OR N PACKAGE (TOP VIEW) Contains Eight D-Type Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs CE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK description The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The SN74F377A features a latched clock enable (CE) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if CE is low. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the CE input. The SN74F377A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS CE CLK D OUTPUT Q H X X Q0 L ↑ H H L ↑ L L X L X Q0 Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 logic symbol† CE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 G1 1C2 2 2D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 11 CLK CE 1D 1 3 1D 2 1Q C1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 recommended operating conditions VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current Low-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX 4.5 5 5.5 2 UNIT V V Input clamp current 0.8 V – 18 mA –1 mA 20 mA 70 °C 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VCC = 4.5 V, VCC = 4.75 V, IOH = – 1 mA IOH = – 1 mA VOL II VCC = 4.5 V, VCC = 0, IOL = 20 mA VI = 7 V IIH IIL VCC = 5.5 V, VCC = 5.5 V, VI = 2.7 V VI = 0.5 V IOS‡ ICCH VCC = 5.5 V, VCC = 5.5 V, VO = 0 See Note 2 MIN TYP† 2.5 3.4 MAX V 2.7 0.3 – 60 UNIT 0.5 V 0.1 mA 20 µA – 0.6 mA – 150 mA 72 mA 55 ICCL VCC = 5.5 V, See Note 3 70 90 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTES: 2. ICCH is measured after applying a momentary ground, then 4.5 V, to the clock input with all data inputs at 4.5 V and the enable input at GND. 3. ICCL is measured after applying a momentary ground, then 4.5 V, to the clock input with all data and enable inputs at GND. timing requirements VCC = 5 V, TA = 25°C MIN MAX MIN MAX 110 0 110 fclock tw Clock frequency 0 Pulse duration 4 tsu Setup time before CLK↑ ↑ Data high or low th Hold time after CLK↑ VCC = 4.5 V to 5.5 V, TA = MIN to MAX§ 5 2 2 2.5 2.5 CE low 4 4.5 Data high or low 1 1 CE high or low 0 0 CE high UNIT MHz ns ns ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 switching characteristics (see Note 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C MIN TYP 110 125 VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX † MAX MIN 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 110 4 6.5 8.5 4 CLK Any Q tPHL 4 7 9 4 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 4: Load circuit and waveforms are shown in Section 1. UNIT MHz 10 10.5 ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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