SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 SN54F109 . . . J PACKAGE SN74F109 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and trying J high. They also can perform as D-type flip-flops if J and K are tied together. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q 1J 1CLR NC SN54F109 . . . FK PACKAGE (TOP VIEW) 1K 1CLK NC 1PRE 1Q 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2K NC 2CLK 2PRE 1Q GND NC 2Q 2Q The SN54F109 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C. VCC 2CLR • NC – No internal connection FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q L H X X X H Q L H L X X X H H† H L L X X X L H† H H ↑ L L L H H ↑ H L H H ↑ L H Q0 Q0 H H ↑ H H H L Toggle H H L X X Q0 Q0 † The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when PRE or CLR returns to its inactive (high) level. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 logic symbol† 1PRE 1J 1CLK 5 S 2 4 2J 2CLK 2K 2CLR 7 1K 1K 2PRE 1Q C1 3 1CLR 6 1J 1 1Q R 11 14 10 2Q 12 9 13 2Q 15 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range: SN54F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions SN54F109 VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL TA Operating free-air temperature 2–2 High-level input voltage SN74F109 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V 0.8 0.8 V – 18 – 18 mA High-level output current –1 –1 mA Low-level output current 20 20 mA 70 °C Input clamp current – 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH J, K, CLK IIL PRE or CLR SN54F109 TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = – 18 mA IOH = – 1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = – 1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5 5.5 5V V, VI = 0 0.5 5V MIN SN74F109 TYP† MAX MIN – 1.2 2.5 3.4 – 1.2 2.5 3.4 0.5 V V 2.7 0.3 UNIT 0.5 V 0.1 0.3 0.1 mA 20 20 µA – 0.6 – 0.6 – 1.8 – 1.8 IOS‡ VCC = 5.5 V, VO = 0 – 60 –150 – 60 ICC VCC = 5.5 V, See Note 2 11.7 17 11.7 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with J, K, CLK, and PRE grounded then with J, K, CLK, and CLR grounded. mA –150 mA 17 mA timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C SN54F109 SN74F109 UNIT ′F74 fclock tw tsu Clock frequency Pulse duration Setup time, time data before CLK↑ Setup time, inactive-state before CLK↑§ th Hold time time, data after CLK↑ MIN MAX MIN MAX MIN MAX 0 100 0 70 0 90 CLK high, PRE or CLR low 4 4 4 CLK low 5 5 5 High 3 3 3 Low 3 3 3 PRE or CLR to CLK 2 2 2 High 1 1 1 Low 1 1 1 MHz ns ns ns § Inactive-state setup time is also referred to as recovery time. switching characteristics (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX¶ ′F109 fmax tPLH MIN TYP 100 150 MAX UNIT SN54F109 SN74F109 MIN MIN MAX 70 MAX 90 MHz 3 4.9 7 3 9 3 8 3.6 5.8 8 3.6 10.5 3.6 9.2 2.4 4.8 7 2.4 9 2.4 8 tPHL 2.7 6.6 9 2.7 11.5 2.7 ¶ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. 10.5 tPHL tPLH CLK Q or Q PRE or CLR Q or Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 2–3 SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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