ETC 24C64

Turbo IC, Inc.
24C64
CMOS I²C 2-WIRE BUS
64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
8K X 8 BIT EEPROM
FEATURES :
• Extended Power Supply Voltage
Single Vcc for Read and Programming
(Vcc = 2.7 V to 5.5 V)
• Low Power (Isb = 2µa @ 5.5 V)
• Extended I²C Bus, 2-Wire Serial Interface
• Support Byte Write and Page Write (32 Bytes)
• Automatic Page write Operation (maximum 10 ms)
Internal Control Timer
Internal Data Latches for 32 Bytes
• Hardware Data Protection by Write Protect Pin
• High Reliability CMOS Technology with EEPROM Cell
Endurance : 1,000,000 Cycles
Data Retention : 100 Years
DESCRIPTION:
The Turbo IC 24C64 is a serial 64K EEPROM fabricated
with Turbo’s proprietary, high reliability, high performance
CMOS technology. It’s 64K of memory is organized as 8,192
x 8 bits. The memory is configured as 256 pages with each
page containing 32 bytes. This device offers significant advantages in low power and low voltage applications.
The Turbo IC 24C64 uses the extended I²C addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a
flexible byte write and a faster 32-byte page write. The data
in the upper quadrant of memory can be protected by a
write protect pin.
The Turbo IC 24C64 is assembled in either a 8-pin PDIP or
8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are
device address input pins which are hardwired by the user.
Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA)
pin used for bidirectional transfer of data. Pin #6 is the serial
clock (SCL) input pin. Pin #7 is the write protect (WP) input
pin, and Pin #8 is the power supply (Vcc) pin.
PIN DESCRIPTION
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
8 pin SOIC
All data is serially transmitted in bytes (8 bits) on the SDA
bus. To access the Turbo IC 24C64 (slave) for a read or
write operation, the controller (master) issues a start condition by pulling SDA from high to low while SCL is high. The
master then issues the device address byte which consists
of 1010 (A2) (A1) (A0) (R/W). The 4 most significant bits
(1010) are a device type code signifying an EEPROM device. The A[2:0] bits represent the input levels on the 3 device address input pins. The read/write bit determines
whether to do a read or write operation. After each byte is
transmitted, the receiver has to provide an acknowledge by
pulling the SDA bus low on the ninth clock cycle. The acknowledge is a handshake signal to the transmitter indicating a successful data transmission.
8 pin PDIP
PIN DESCRIPTION
DEVICE ADDRESSES (A2-A0)
The address inputs are used to define the 3 least
significant bits of the 7-bit device address code 1010 (A2) (A1) (A0). These pins can be connected either high or low. A maximum of eight
Turbo IC 24C64 can be connected in parallel,
each with a unique device address. When these
pins are left unconnected, the device addresses
are interpreted as zero.
WRITE PROTECT (WP)
When the write protect input is connected to Vcc,
the upper quadrant of memory (1800-1FFFH) is
protected against write operations. For normal
write operation, the write protect pin should be
grounded. When this pin is left unconnected, WP
is interpreted as zero.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data
in and out of the Turbo IC 24C64. The pin is an
open1
drain output. A pullup resistor must be connected
from SDA to Vcc.
SERIAL CLOCK (SCL)
The SCL input synchronizes the data on the SDA
bus. It is used in conjunction with SDA to define
the start and stop conditions. It is also used in
conjunction with SDA to transfer data to and from
the Turbo IC 24C64.
Turbo IC, Inc.
24C64
DESCRIPTION (Continued)
For a write operation, the master issues a start condition,
device address byte, 2 memory address bytes, and then up
to 32 data bytes. The Turbo IC 24C64 acknowledges after
each byte transmission. To terminate the transmission, the
master issues a stop condition by pulling SDA from low to
high while SCL is high.
For a read operation, the master issues a start condition and
a device address byte. The Turbo IC 24C64 acknowledges,
and then transmits a data byte, which is accessed from the
EEPROM memory. The master acknowledges, indicating that
it requires more data bytes. The Turbo IC 24C64 transmits
more data bytes, with the memory address counter automatically incrementing for each data byte, until the master
does not acknowledge, indicating that it is terminating the
transmission. The master then issues a stop condition.
DEVICE OPERATION:
BIDIRECTIONAL BUS PROTOCOL:
The Turbo IC 24C64 follows the extended I²C bus protocol.
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a receiver. The device controlling the transfer is the master and
the device being controlled is the slave. The master always
initiates the data transfers, and provides the clock for both
transmit and receive operations. The Turbo IC 24C64 acts as
a slave device in all applications. Either the master or the
slave can take control of the SDA bus, depending on the
requirement of the protocol.
ACKNOWLEDGE:
All data is serially transmitted in bytes (8 bits) on the SDA
bus. The acknowledge protocol is used as a handshake signal to indicate successful transmission of a byte of data. The
bus transmitter, either the master or the slave (Turbo IC
24C64), releases the bus after sending a byte of data on the
SDA bus. The receiver pulls the SDA bus low during the ninth
clock cycle to acknowledge the successful transmission of a
byte of data. If the SDA is not pulled low during the ninth
clock cycle, the Turbo IC 24C64 terminates the data transmission and goes into standby mode.
START/STOP CONDITION AND DATA TRANSITIONS:
While SCL clock is high, a high to low transition on the SDA
bus is recognized as a START condition which precedes any
read or write operation. While SCL clock is high, a low to
high transition on the SDA bus is recognized as a STOP condition which terminates the communication and places the
Turbo IC 24C64 into standby mode. All other data transitions
on the SDA bus must occur while SCL clock is low to ensure
proper operation.
For the write operation, the Turbo IC 24C64 acknowledges
after the device address byte, acknowledges after each
memory address byte, and acknowledges after each subsequent data byte.
For the read operation, the Turbo IC 24C64 acknowledges
after the device address byte. Then the Turbo IC 24C64 transmits each subsequent data byte, and the master acknowledges after each data byte transfer, indicating that it requires
more data bytes. The Turbo IC 24C64 monitors the SDA bus
for the acknowledge. To terminate the transmission, the master does not acknowledge, and then sends a stop condition.
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
STOP
CONDITION
tWC
START
CONDITION
Note: The write cycle time tWC is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
2
Turbo IC, Inc.
24C64
Data Valid
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Start and Stop Definition
SDA
SCL
STOP
START
Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
3
Turbo IC, Inc.
24C64
address counter is automatically incremented by one. The
stop condition starts the internal EEPROM write cycle only if
the stop condition occurs in the clock cycle immediately following the acknowledge (10th clock cycle). All inputs are disabled until the completion of the write cycle. If the WP pin is
high (1) and the memory address is within the upper quadrant (1800-1FFFH) of memory, then the stop condition does
not start the internal write cycle, and the Turbo IC 24C64 is
immediately ready for the next command.
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to access the selected Turbo IC 24C64 for a read or write operation. The A[2:0] bits must match with the address input pins
of the selected Turbo IC 24C64. If there is a match, the selected Turbo IC 24C64 acknowledges during the ninth clock
cycle by pulling the SDA bus low. If there is no match, the
Turbo IC 24C64 does not acknowledge during the ninth clock
cycle and goes into standby mode. The (R/W) bit is a high (1)
for read and low (0) for write.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C64, the completion of the write cycle can be detected
by polling acknowledge. The master starts acknowledge polling by issuing a start condition, then followed by the device
address byte 1010 (A2) (A1) (A0) 0. If the internal write cycle
is finished, the Turbo IC 24C64 acknowledges by pulling the
SDA bus low. If the internal write cycle is still ongoing, the
Turbo IC 24C64 does not acknowledge because it’s inputs
are disabled. Therefore, the device will not respond to any
command. By using polling acknowledge, the system delay
for write operations can be reduced. Otherwise, the system
needs to wait for the maximum internal write cycle time, tWC,
given in the spec.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C64 latches the
SDA bus signal on the rising edge of the SCL clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C64 serially shifts
the data onto the SDA bus on the falling edge of the SCL
clock.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
memory address bytes. The memory address bytes can only
be sent as part of a write operation. The most significant
address byte XXX (B12) (B11) (B10) (B9) (B8) is sent first,
where X represents “don’t care”. Then the least significant
address byte (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) is sent
last.
POWER ON RESET:
The Turbo IC 24C64 has a Power On Reset circuit (POR) to
prevent data corruption and accidental write operations during power up. On power up, the internal reset signal is on
and the Turbo IC 24C64 will not respond to any command
until the VCC voltage has reached the POR threshold value.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, followed by one data byte, followed by an acknowledge, then a
stop condition. After each byte transfer, the Turbo IC 24C64
acknowledges the successful data transmission by pulling
the SDA bus low. The stop condition starts the internal
EEPROM write cycle, and all inputs are disabled until the
completion of the write cycle. If the WP pin is high (1) and the
memory address is within the upper quadrant (1800-1FFFH)
of memory, then the stop condition does not start the internal write cycle and the Turbo IC 24C64 is immediately ready
for the next command.
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, followed by up to 32 data bytes, followed by an acknowledge,
then a stop condition. After each byte transfer, the Turbo
IC24C64 acknowledges the successful data transmission by
pulling SDA low. After each data byte transfer, the memory
4
Turbo IC, Inc.
24C64
Device Address
1
0
1
0
A2
A1
A0
MSB
R/W
LSB
Byte Write
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
SDA LINE
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
S
T
O
P
DATA
* * *
M
S
B
M
S
B
L RA
S / C
B WK
A
C
K
L A
S C
B K
A
C
K
Page Write
S
T
A
R
T
W
R
I
T
FIRST
SECOND
E WORD ADDRESS (n) WORD ADDRESS (n)
DEVICE
ADDRESS
SDA LINE
DATA (n)
* * *
M
S
B
L RA
S / C
B WK
M
S
B
A
C
K
L A
S C
B K
* = Don't care bits
5
A
C
K
//
//
S
T
O
P
DATA (n + x)
A
C
K
Turbo IC, Inc.
24C64
CURRENT ADDRESS READ:
The internal memory address counter of the Turbo IC 24C64
contains the last memory address accessed during the previous read or write operation, incremented by one. To start
the current address read operation, the master issues a start
condition, followed by the device address byte 1010 (A2) (A1)
(A0) 1. The Turbo IC 24C64 responds with an acknowledge
by pulling the SDA bus low, and then serially shifts out the
data byte accessed from memory at the location corresponding to the memory address counter. The master does not
acknowledge, then sends a stop condition to terminate the
read operation. It is noted that the memory address counter
is incremented by one after the data byte is shifted out.
an acknowledge by pulling the SDA bus low, and then serially shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.
SEQUENTIAL READ:
The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C64 serially shifts out the first data byte, the master acknowledges
by pulling the SDA bus low, indicating that it requires additional data bytes. After the data byte is shifted out, the Turbo
IC 24C64 increments the memory address counter by one.
Then the Turbo IC 24C64 shifts out the next data byte. The
sequential reads continues for as long as the master keeps
acknowledging. When the memory address counter is at the
last memory location, the counter will ‘roll-over’ when
incremented by one to the first location in memory (address
zero). The master terminates the sequential read operation
by not acknowledging, then sends a stop condition.
RANDOM ADDRESS READ:
The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed by the 2 memory address bytes. Following the acknowledge from the Turbo IC
24C64, the master starts the current read operation by issuing a start condition, followed by the device address byte
1010 (A2) (A1) (A0) 1. The Turbo IC 24C64 responds with
Current Address Read
S
T
A
R
T
R
E
A
D
DEVICE
ADDRESS
S
T
O
P
DATA
SDA LINE
M
S
B
L RA
S / C
B WK
M
S
B
N
O
A
C
K
Random Read
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
WORD
ADDRESS N
DEVICE
ADDRESS
//
R
E
A
D
S
T
O
P
DATA n
SDA LINE
M
S
B
L RA
S / C
B WK
//
A
C
K
DUMMY WRITE
6
A
C
K
N
O
A
C
K
Turbo IC, Inc.
24C64
Sequential Read
S
T
A
R
T
R
E
A
D
DEVICE
ADDRESS
DATA n
DATA n + 2
DATA n +1
S
T
O
P
DATA n + 3
SDA LINE
M
S
B
L RA
S / C
B WK
A
C
K
A
C
K
N
O
A
C
K
A
C
K
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TEMPERATURE
Storage:
Under Bias:
Temperature Range:
Commercial:
Vcc Supply Voltage:
2.7 to 5.5 Volts
Endurance:
Data Retention:
1,000,000 Cycles/Byte (Typical)
100 Years
-65° C to 150° C
-55° C to 125° C
ALL INPUT OR OUTPUT VOLTAGES
with respect to Vss
+6 V to -0.3 V
0° C to 70° C
* “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
Symbol
Parameter
Condition
Min
Max
Units
I cc1
I cc2
I sb
Active Vcc Current
Active Vcc Current
Standby Current
0.4
Ili
Ilo
Vil
Vih
Vol2
Vol1
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low
Output Low
READ at 100 KHZ
WRITE at 100 KHZ
Vcc = 2.7 v
Vcc = 5.5 v
Vin=Vcc Max
1
3
0.5
2.0
3
3
mA
mA
uA
uA
uA
uA
V
V
V
V
-1.0
Vcc=3.0v Iol=2.1 mA
Vcc=2.7v Iol=-0.15 mA
7
Vcc+0.5
0.4
0.25
Turbo IC, Inc.
24C64
Bus Timing
t
t
F
HIGH
t
LOW
SCL
t
R
t
LOW
t
HD.DAT
t
HD.STA
t
SU.STA
t
SU.DAT
t
SU.STO
SDA IN
t
AA
t
t
BUF
DH
SDA OUT
A.C. CHARACTERISTICS
Symbol
Parameter
2.7 volt
Min
SCL
T
tLOW
tHIGH
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWC
SCL Clock Frequency
Noise Suppression Time (1)
Clock Low Period
Clock High Period
SCL Low to SDA Data Out
Bus Free to New Start (1)
Start Hold Time
Start Setup Time
Data-in Hold Time
Data-in Set-up Time
SCL and SDA Rise Time (1)
SCL and SDA Fall Time (1)
Stop Setup Time
Data-out Hold Time
Write Cycle Time
4.7
4.0
0.1
4.7
4.0
4.7
0
200
5.5 volt
Max
100
100
4.5
Min
1.2
0.6
0.1
1.2
0.6
0.6
0
100
1.0
300
4.7
100
Max
400
100
0.9
0.3
300
0.6
50
10
10
Units
kHZ
ns
us
us
us
us
us
us
us
ns
us
ns
us
ns
ms
Note: 1 This parameter is characterized and not 100% tested.
TURBO IC PRODUCTS AND DOCUMENTS
1.
2.
3.
4.
All documents are subject to change without notice. Please contact Turbo IC for the latest
revision of documents.
Turbo IC does not assume any responsibility for any damage to the user that may result from
accidents or operation under abnormal conditions.
Turbo IC does not assume any responsibility for the use of any circuitry other than what
embodied in a Turbo IC product. No other circuits, patents, licenses are implied.
Turbo IC products are not authorized for use in life support systems or other critical systems
where component failure may endanger life. System designers should design with error
detection and correction, redundancy and backup features.
Part Numbers & Order Information
TU24C64CP3
Revision C
8K X 8
Serial
EEPROM
Package
P -PDIP
S -SOIC
Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: 408-392-0208
See us at www.turbo-ic.com
Voltage
3 - 2.7 to 5.5 V
2 - 2.2 to 5.5 V
Fax: 408-392-0207
Rev. 5.0 - 11/27/02