STMICROELECTRONICS M34D32WBNT1

M34D64
M34D32
64/32 Kbit Serial I²C Bus EEPROM
With Hardware Write Control on Top Quarter of Memory
PRELIMINARY DATA
■
Compatible with I2C Extended Addressing
■
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■
Single Supply Voltage:
8
– 4.5V to 5.5V for M34Dxx
– 2.5V to 5.5V for M34Dxx-W
– 1.8V to 3.6V for M34Dxx-R
■
1
Hardware Write Control of the top quarter of
memory
■
BYTE and PAGE WRITE (up to 32 Bytes)
■
RANDOM and SEQUENTIAL READ Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Behavior
■
More than 1 Million Erase/Write Cycles
■
More than 40 Year Data Retention
DESCRIPTION
These electrically erasable programmable
memory (EEPROM) devices are fabricated with
STMicroelectronics’ High Endurance, CMOS
technology. This guarantees an endurance
typically well above one million Erase/Write
cycles, with a data retention of 40 years. The
memories are organized as 8192x8 bits (M34D64)
and 4096x8 bits (M34D32), and operate down to
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
3
E0-E2
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
SCL
Serial Clock
WC
WC
Write Control
VCC
Supply Voltage
VSS
Ground
SDA
M34D64
M34D32
VSS
AI02850
May 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/15
M34D64, M34D32
2.5 V (for the -W version of each device), and
down to 1.8 V (for the -R version of each device).
The M34D64 and M34D32 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: V CC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the V CC voltage has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any
command. In the same way, when V CC drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
Figure 2A. DIP Connections
M34D64
M34D32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02851
Figure 2B. SO Connections
M34D64
M34D32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02852
Table 2. Absolute Maximum Ratings 1
Symbol
Value
Unit
Ambient Operating Temperature
-40 to 125
°C
TSTG
Storage Temperature
-65 to 150
°C
TLEAD
Lead Temperature during Soldering
260
215
°C
TA
Parameter
PSDIP8: 10 sec
SO8: 40 sec
VIO
Input or Output range
-0.6 to 6.5
V
VCC
Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
4000
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)
2/15
M34D64, M34D32
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
RL
12
SDA
MASTER
8
fc = 100kHz
4
CBUS
SCL
fc = 400kHz
CBUS
0
10
1000
100
CBUS (pF)
AI01665
valid VCC must be applied before applying any
logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to VCC. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pullup resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to V CC. (Figure 3 indicates how the value of
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied to V CC or VSS to
establish the device select code.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable
(WC=VIL) or disable (WC=VIH) write instructions to
the top quarter of the memory area. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
DEVICE OPERATION
The memory device supports the I2C protocol.
This is summarized in Figure 5, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
Figure 4. Memory Map of Write Control Areas
1FFh
Write Controlled
Area
180h
100h
FFh
C0h
Write Controlled
Area
80h
80h
40h
00h
000h
M34D64
M34D32
AI03114
3/15
M34D64, M34D32
Figure 5. I2C Bus Protocol
SCL
SDA
START
CONDITION
SCL
1
SDA
MSB
SDA
INPUT
2
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all
communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously
monitors
(except
during
a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
4/15
state.
A
STOP
condition
terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9th
clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
M34D64, M34D32
Table 3. Device Select Code 1
Device Type Identifier
Device Select Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
Note: 1. The most significant bit, b7, is sent first.
transition, and the data must change only when
the SCL line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I 2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the
memory only responds if the Chip Select Code is
the same as the pattern applied to its Chip Enable
pins.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9 th bit time. If the memory does not
match the Device Select Code, it deselects itself
from the bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
Table 4. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Note: 1. b15 to b13 are Don’t Care on the M34D64 series.
b15 to b12 are Don’t Care on the M34D32 series.
Table 5. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
significant Byte (Table 5). Bits b15 to b0 form the
address of the byte in memory. Bits b15 to b13 are
treated as a Don’t Care bit on the M34D64
memory. Bits b15 to b12 are treated as Don’t Care
bits on the M34D32 memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory
responds to each address byte with an
acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the contents of the top quarter of
the memory.
Table 6. Operating Modes
Mode
Current Address Read
RW bit
WC 1
Bytes
1
X
1
0
X
Random Address Read
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
1
reSTART, Device Select, RW = ‘1’
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
START, Device Select, RW = ‘0’
Page Write
0
VIL
≤ 32
START, Device Select, RW = ‘0’
Similar to Current or Random Address Read
Note: 1. X = VIH or VIL.
5/15
M34D64, M34D32
Figure 6. Write Mode Sequences
ACK
BYTE ADDR
START
DEV SEL
ACK
BYTE ADDR
DATA IN
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
ACK
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
BYTE ADDR
ACK
R/W
ACK
PAGE WRITE
ACK
STOP
DEV SEL
START
BYTE WRITE
ACK
AI02853
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the location is not
modified. The master terminates the transfer by
generating a STOP condition.
Page Write
The Page Write mode allows up to 32 bytes to be
written in a single write cycle, provided that they
are all located in the same “row” in the memory:
that is the most significant memory address bits
(b12-b5 for the M34D64 and b11-b5 for the
M34D32) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
The master sends from one up to 32 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
6/15
contents of the addressed memory location are
not modified. After each byte is transferred, the
internal byte address counter (the 5 least
significant bits only) is incremented. The transfer is
terminated by the master generating a STOP
condition.
When the master generates a STOP condition
immediately after the Ack bit (in the “10 th bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not
trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (tw) is shown in Table 9,
but the typical time is shorter. To make use of this,
M34D64, M34D32
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by M24xxx
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847
an Ack polling sequence can be used by the
master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to 1. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
7/15
M34D64, M34D32
Figure 8. Read Mode Sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
NO ACK
DATA OUT N
R/W
ACK
ACK
BYTE ADDR
R/W
ACK
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
DEV SEL *
DATA OUT
R/W
ACK
DATA OUT 1
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
shown in Figure 8, without acknowledging the byte
output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
8/15
After the last memory address, the address
counter ‘rolls-over’ and the memory continues to
output data from the start of the memory block.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its standby state.
M34D64, M34D32
Table 7. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C;
(TA = 0 to 70 °C or –20 to 85 °C;
Symbol
VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)
VCC = 1.8 to 3.6 V 1)
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA)
0 V ≤ VIN ≤ VCC
±2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
2
mA
-W series:
VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
1
mA
-R series:
VCC =1.8V, fc=100kHz (rise/fall time < 30ns)
0.81
mA
ICC
Supply Current
ICC1
Supply Current (Stand-by)
VIN = VSS or VCC , VCC = 5 V
10
µA
ICC2
Supply Current (Stand-by)
VIN = VSS or VCC , VCC = 2.5 V
2
µA
ICC3
Supply Current (Stand-by)
VIN = VSS or VCC , VCC = 1.8 V
11
µA
VIL
Input Low Voltage
(E0-E2, SCL, SDA)
–0.3
0.3 VCC
V
VIH
Input High Voltage
(E0-E2, SCL, SDA)
0.7VCC
VCC+1
V
VILW
Input Low Voltage (WC)
–0.3
0.5
V
VIHW
Input High Voltage (WC)
0.7VCC
VCC+1
V
IOL = 3 mA, VCC = 5 V
0.4
V
VOL
Output Low
Voltage
-W series:
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
-R series:
IOL = 0.15 mA, VCC = 1.8 V
0.21
V
Note: 1. This is preliminary data.
Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
300
kΩ
ZWCL
WC Input Impedance
VIN < VILW
50
ZWCH
WC Input Impedance
VIN > VIHW
500
tNS
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch
kΩ
50
ns
Note: 1. Sampled only, not 100% tested.
9/15
M34D64, M34D32
Table 9. AC Characteristics
M34D64 / M34D32
Symbol
Alt.
VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V
TA=0 to 70°C or TA=0 to 70°C or TA=0 to 70°C or Unit
–40 to 85°C
–40 to 85°C
–20 to 85°C4
Parameter
Min
Max
Min
Max
Min
Max
tCH1CH2
tR
Clock Rise Time
300
300
1000
ns
tCL1CL2
300
300
300
ns
tF
Clock Fall Time
2
tR
SDA Rise Time
20
300
20
300
20
1000
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
20
300
20
300
ns
Clock High to Input Transition
600
600
4700
ns
Clock Pulse Width High
600
600
4000
ns
Input Low to Clock Low (START)
600
600
4000
ns
0
0
0
µs
tDH1DH2
tCHDX
1
tSU:STA
tCHCL
tHIGH
tDLCL
tHD:STA
tCLDX
tHD:DAT Clock Low to Input Transition
tCLCH
tLOW
Clock Pulse Width Low
1.3
1.3
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock
Transition
100
100
250
ns
tCHDH
tSU:STO Clock High to Input High (STOP)
600
600
4000
ns
1.3
4.7
µs
tDHDL
tBUF
Input High to Input Low (Bus
Free)
1.3
tCLQV 3
tAA
Clock Low to Data Out Valid
200
tCLQX
tDH
Data Out Hold Time After Clock
Low
200
fC
fSCL
Clock Frequency
400
400
100
kHz
tWR
Write Time
10
10
10
ms
tW
Note: 1.
2.
3.
4.
200
900
200
200
3500
200
ns
ns
For a reSTART condition, or following a write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
This is preliminary data.
Table 10. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
10/15
900
≤ 50 ns
Figure 9. AC Testing Input Output Waveforms
0.8VCC
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
M34D64, M34D32
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
tCHDH
SDA IN
tCHDX
START
CONDITION
tCLDX
tDHDL
SDA
INPUT
SDA
CHANGE
STOP &
BUS FREE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
STOP
CONDITION
tCHDX
WRITE CYCLE
START
CONDITION
AI00795B
11/15
M34D64, M34D32
Table 11. Ordering Information Scheme
Example:
M34D64
– W
MN
1
T
Memory Capacity
64
64 Kbit (8K x 8)
32
32 Kbit (4K x 8)
Option
T
Tape and Reel Packing
Operating Voltage
blank 4.5 V to 5.5 V
W
2.5 V to 5.5 V
R2
1.8 V to 3.6 V
Package
BN
PSDIP8 (0.25 mm frame)
MN
SO8 (150 mil width)
Temperature Range
11
0 °C to 70 °C
6
–40 °C to 85 °C
5
–20 °C to 85 °C
Note: 1. Temperature range available only on request.
2. The -R version (V CC range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
12/15
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
M34D64, M34D32
Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Symb.
Typ.
Min.
Max.
A
3.90
A1
Min.
Max.
5.90
0.154
0.232
0.49
–
0.019
–
A2
3.30
5.30
0.130
0.209
B
0.36
0.56
0.014
0.022
B1
1.15
1.65
0.045
0.065
C
0.20
0.36
0.008
0.014
D
9.20
9.90
0.362
0.390
–
–
–
–
6.00
6.70
0.236
0.264
–
–
–
–
7.80
–
0.307
–
E
7.62
E1
e1
2.54
eA
eB
Typ.
0.300
0.100
10.00
L
3.00
N
8
0.394
3.80
0.118
0.150
8
Figure 11. PSDIP8 (BN)
A2
A1
B
A
L
e1
eA
eB
B1
D
C
N
E1
E
1
PSDIP-a
Note: 1. Drawing is not to scale.
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M34D64, M34D32
Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
1.27
Typ.
0.050
8
CP
0.10
0.004
Figure 12. SO8 narrow (MN)
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
SO-a
Note: 1. Drawing is not to scale.
14/15
α
L
M34D64, M34D32
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