APPLICATION NOTE A VA I L A B L E AN61 Preliminary Information Recommended System Management Alternative: X5563 X25128 128K 16K x 8 Bit SPI Serial EEPROM with Block Lock™ Protection FEATURES DESCRIPTION • 2MHz clock rate • SPI modes (0,0 & 1,1) • 16K X 8 bits —32-byte page mode • Low Power CMOS —<1µA standby current —<5mA active current • 2.7V To 5.5V power supply • Block lock protection —Protect 1/4, 1/2 or all of EEPROM array • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Write enable latch —Write protect pin • Self-timed write cycle —5ms write cycle time (typical) • High reliability —Endurance: 1 million cycles —Data retention: 100 years —ESD protection: 2000V on all pins • Packages —8-Lead XBGA —14-lead SOIC The X25128 is a CMOS 131,072-bit serial EEPROM, internally organized as 16K x 8. The X25128 features a Serial Peripheral Interface (SPI) and software protocol, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25128 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25128 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25128 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25128 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. BLOCK DIAGRAM Status Register Write Protect Logic X Decode Logic 16K Byte Array 128 SO SI SCK CS HOLD Command Decode and Control Logic 16 X 256 128 16 X 256 256 32 X 256 WP Write Control and Timing Logic 32 8 Y Decode Data Register REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 1 of 14 X25128 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. brought low while SCK is Low. To resume communication, HOLD is brought high, again while SCK is low. If the pause feature is not used, HOLD should be held high at all times. PIN CONFIGURATION Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. 8-Lead XBGA: Top View HOLD 1 8 SO VCC 2 7 CS SI 3 6 VSS SCK 4 5 WP Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. 14-Lead SOIC CS 1 14 VCC SO 2 13 HOLD NC 3 4 12 X25128 11 NC NC NC 5 10 NC WP VSS 6 7 9 8 Chip Select (CS) It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. When CS is high, the X25128 is deselected and the SO output pin is at high impedance; unless an internal write operation is underway, the X25128 will be in the standby power mode. CS low enables the X25128, placing it in the active power mode. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller (without resetting the serial sequence). To pause, HOLD must be REV 1.1 9/8/00 SCK SI PIN NAMES Write Protect (WP) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25128 status register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes operate normally. WP going low while CS is still low will interrupt a write to the X25128 status register. If the internal write cycle has already been initiated, WP going low will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25128 in a system with WP pin grounded, and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. NC Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input NC No Connect PRINCIPLES OF OPERATION The X25128 is a 8K x 8 EEPROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25128 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be low and the HOLD and WP inputs must be high during the entire operation. The WP input is “Don’t Care” if WPEN is set “0”. www.xicor.com Characteristics subject to change without notice. 2 of 14 X25128 Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. Data input is sampled on the first rising edge of SCK after CS goes low. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25128 into a “PAUSE” condition. After releasing HOLD, the X25128 will resume operation from the point when HOLD was first asserted. The Write-In-Process (WIP) bit indicates whether the X25128 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”. Write Enable Latch The X25128 contains a “write enable” latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-on condition and after the completion of a byte, page, or status register write cycle. The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When set to a “1”, the latch is set, when set to a “0”, the latch is reset. The Block Protect (BP0 and BP1) bits are nonvolatile and allows the user to select one of four levels of protection. The X25128 is divided into four 32,768-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below. Status Register Bits BP1 BP0 Array Addresses Protected 0 0 None 0 1 $3000–$3FFF 1 0 $2000–$3FFF 1 1 $0000–$3FFF Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 6 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL WIP Table 1. Instruction Set Instruction Name Instruction Format* WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register Note: Operation READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address (1 to 32-bytes) *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 3 of 14 X25128 Write-Protect Enable The Write-Protect-Enable (WPEN) is available for the X25128 as a nonvolatile enable bit for the WP pin. WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is low, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the status register, including the block protect bits, the WPEN bit itself, and the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. Note: Since the WPEN bit is write protected, it cannot be changed back to a “0” as long as the WP pin is held low. Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the EEPROM array, CS is first pulled low to select the device. The 8-bit read instruction is transmitted to the X25128, followed by the 16-bit address of which the last 14 are used. After the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($3FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued REV 1.1 9/8/00 indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array operation sequence illustrated in Figure 1. To read the status register, the CS line is first pulled low to select the device, followed by the 8-bit instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. The read status register sequence is illustrated in Figure 2. Write Sequence Prior to any attempt to write data into the X25128, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken low, then the WREN instruction is clocked into the X25128. After all eight bits of the instruction are transmitted, CS must then be taken high. If the user continues the write operation without taking CS high (after issuing the WREN instruction), the write operation will be ignored. To write data to the EEPROM memory array, the user issues the write instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go low and remain low for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25128. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought high after bit 0 of data byte N is clocked in. If it is brought high at any other time the write operation will not be completed. Refer to www.xicor.com Characteristics subject to change without notice. 4 of 14 X25128 Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going high are valid. Operational Notes The X25128 powers-up in the following state: – The device is in the low power standby state. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. This sequence is shown in Figure 6. – A high to low transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. While the write is in progress, following a status register or EEPROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. – The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: Hold Operation The HOLD input should be high (at VIH) under normal operation. If a data transfer is to be interrupted, HOLD can be pulled low to suspend the transfer until it can be resumed. The only restriction is the SCK input must be low when HOLD is first pulled low, and SCK must also be low when HOLD is released. – The “write enable” latch is reset upon power-up. – A WREN instruction must be issued to set the “write enable” latch. – CS must come high at the proper clock count in order to start a write cycle. The HOLD input may be tied high either directly to VCC or tied to VCC through a resistor. Figure 1. Read EEPROM Array Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 SCK Instruction 16 Bit Address 15 14 13 SI 3 2 1 0 Data Out High Impedance 7 SO 6 5 4 3 2 1 0 MSB REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 5 of 14 X25128 Figure 2. Read Status Register Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK Instruction SI Data Out High Impedance 7 SO 6 5 4 3 2 1 0 MSB Figure 3. Write Enable Latch Sequence CS 0 1 2 3 4 5 6 7 SCK SI High Impedance SO Figure 4. Byte Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 15 14 13 SI SO REV 1.1 9/8/00 16 Bit Address 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance www.xicor.com Characteristics subject to change without notice. 6 of 14 X25128 Figure 5. Page Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 20 21 22 23 24 25 26 27 28 29 30 31 10 SCK Instruction 16 Bit Address 15 14 13 SI 3 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 Data Byte N 2 1 0 6 5 4 3 2 1 0 Figure 6. Write Status Register Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction 7 SI SO REV 1.1 9/8/00 Data Byte 6 5 4 3 2 1 0 High Impedance www.xicor.com Characteristics subject to change without notice. 7 of 14 X25128 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................–65°C to +135°C Storage temperature .........................–65°C to +150°C Voltage on any pin with respect to VSS ......................................... –1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits X25128-2.7 2.5V to 5.5V Commercial 0°C +70°C Industrial –40°C +85°C D.C. OPERATING CHARACTERISTICS Limits Symbol Parameter Min. Max. Unit Test Conditions ICC VCC supply current (active) 5 mA SCK = VCC x 0.1/VCC x 0.9 @ 2 MHz, SO = Open, CS = VSS ISB VCC supply current (standby) 1 µA CS = VCC, VIN = VSS or VCC ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC (1) VlL Input LOW voltage –1 VCC x 0.3 V VIH(1) Input HIGH voltage VCC x 0.7 VCC + 0.5 V VOL1 Output LOW voltage 0.4 V VCC = 5V, IOL = 3mA VOH1 Output HIGH voltage V VCC = 5V, IOH = -1.6mA VOL2 Output LOW voltage V VCC = 3V, IOL = 1.5mA VOH2 Output HIGH voltage V VCC = 3V, IOH = -0.4mA VCC – 0.8 0.4 VCC – 0.3 POWER-UP TIMING Symbol (3) (3) tPUR tPUW Parameter Min. Max. Unit Power-up to read operation 1 ms Power-up to write operation 5 ms CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol (2) COUT CIN(2) Test Max. Unit Conditions Output capacitance (SO) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS, WP, HOLD) 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 8 of 14 X25128 A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC X 0.5 5V 3V 1.44KΩ 1.64KΩ Output 1.95KΩ Output 100pF 4.63KΩ 100pF A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Data Input Timing Symbol Parameter Min. Max. Unit 0 2 MHz fSCK Clock frequency tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 200 ns tSU Data setup time 50 ns tH Data hold time 50 ns (4) tRI Data in rise time 2 µs tFI(4) Data in fall time 2 µs tHD HOLD setup time 100 ns tCD HOLD hold time 100 ns tCS CS deselect time 2.0 µs (5) Write cycle time: VCC = 2.7V – 5.5V 10 ms (5) Write cycle time: VCC = 4.5V – 5.5V 5 ms tWC tWC REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 9 of 14 X25128 Data Output Timing Symbol Parameter Min. Max. Unit fSCK Clock frequency 2 MHz tDIS Output disable time 250 ns Output valid from clock LOW 200 ns tV tHO 0 Output hold time 0 ns (4) Output rise time 100 ns (4) Output fall time 100 ns (4) HOLD HIGH to output in low Z 100 ns (4) HOLD LOW to output in low Z 100 ns tRO tFO tLZ tHZ Notes: (4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC tLAG tWH SCK tV SO SI tHO MSB Out tDIS tWL MSB–1 Out LSB Out ADDR LSB IN Serial Input Timing tCS CS tLEAD tLAG SCK tSU SI SO REV 1.1 9/8/00 tH tRI MSB In tFI LSB In High Impedance www.xicor.com Characteristics subject to change without notice. 10 of 14 X25128 Hold Timing CS tHD tCD tCD tHD SCK tHZ tLZ SO SI HOLD SYMBOL TABLE WAVEFORM REV 1.1 9/8/00 INPUTS OUTPUTS Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance www.xicor.com Characteristics subject to change without notice. 11 of 14 X25128 PACKAGING INFORMATION 8-Lead XBGA PACKAGE Complete Part Number Top Mark X25128Z -2.7 XAAA X25128ZI -2.7 XACL 215±30 8-Lead XBGA X25128: Bottom View S0 7 CS 3 6 .238” VSS SCK 4 5 WP CS 1000±30 SI PIN 1 VCC VSS SI WP SCK 6046±30 VCC 2 8 6046±30 HOLD 1 HOLD S0 350±20 .078” 500±20 8-Lead XBGA: Top View 1200±30 430±50 1982±30 1833±30 215±30 350±20 ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch) ALL DIMENSIONS ARE TYPICAL VALUES REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 12 of 14 X25128 PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050"Typical 0.010 (0.25) 0.020 (0.50) X 45° 0.050"Typical 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030"Typical 14 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 13 of 14 X25128 Ordering Information X25128 P T -V VCC Range 2.7 = 2.7V to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S14 = 14-Lead SOIC Z = 8-Lead XBGA Part Mark Convention 8-Lead SOIC X5128 X XX Blank = 8-Lead SOIC P = 8-Lead PDIP 8-Lead XBGA PACKAGE Complete Part Number Top Mark X25128Z -2.7 XAAA X25128ZI -2.7 XACL F = 2.7 to 5.5V, 0 to +70°C G = 2.7 to 5.5V, -40 to +85°C LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1 9/8/00 www.xicor.com Characteristics subject to change without notice. 14 of 14