SCAS689 − FEBRUARY 2003
D Phase-Lock Loop Clock Driver for Double
D
D
D
D
D
D
D Enters Low-Power Mode When No CLK
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): ±50 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±35 ps
Distributes One Differential Clock Input to
10 Differential Outputs
D
D
D
D
D
Input Signal Is Applied or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior BGA Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
Meets/Exceeds the Latest DDR JEDEC
Spec JESD82−1
description
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, theoutputs switch in phase
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857B is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
TA
0°C to 85°C
TSSOP (DGG)
MicroStar Junior BGA (GQL)
CDCV857BDGG
CDCV857BGQL
−40°C to 85°C
CDCV857BIGG
—
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
GND
PWRDWN
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz
<20 MHz
Z
Z
Z
Z
Off
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments Incorporated.
Copyright 2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%
)$#!" # ! "&%##!" &% !*% !%" %+" "!$%!"
"!)) ,!- )$#! &#%"". )%" ! %#%""(- #($)%
!%"!. (( &%!%"
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCAS689 − FEBRUARY 2003
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2
Y5
GND
V DDQ
Y5
5
6
A
Y1
Y1
B
Y6
Y6
C
NC
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
D
NC
NC
GND
GND
NC
Y7
Y7
NC
E
F
NC
NC
G
NC
NC
H
NC
NC
PWRDN
VDDQ
FBIN
FBIN
VDDQ
FBOUT
VDDQ
AVDD
AGND
GND
Y3
Y3
POST OFFICE BOX 655303
FBOUT
GND
J
Y8
Y8
K
• DALLAS, TEXAS 75265
Y9
45
4
Y9
4
3
GND
46
2
V DDQ
47
3
1
GND
2
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
V DDQ
48
Y4
1
Y4
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
V DDQ
GND
DGG PACKAGE
(TOP VIEW)
Y0
Y0
MicroStar Junior (GQL) Package
(TOP VIEW)
SCAS689 − FEBRUARY 2003
functional block diagram
3
2
PWRDWN
AVDD
5
37
16
6
Power Down
and Test
Logic
10
9
20
19
22
23
46
47
CLK
CLK
FBIN
FBIN
13
44
14
36
43
PLL
39
35
40
29
30
27
26
32
33
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
3
SCAS689 − FEBRUARY 2003
Terminal Functions
TERMINAL
NAME
AGND
DGG
GQL
17
H1
AVDD
CLK, CLK
16
G2
13, 14
F1, F2
FBIN, FBIN
35, 36
FBOUT, FBOUT
32, 33
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
A3, A4,
C1, C2,
C5, C6,
H2, H5,
K3, K4
GND
PWRDWN
DESCRIPTION
Ground for 2.5-V analog supply
2.5-V Analog supply
I
Differential clock input
F5, F6
I
Feedback differential clock input
H6, G5
O
Feedback differential clock output
Ground
37
E6
VDDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
B3, B4,
E1, E2,
E5, G1,
G6, J3, J4
I
Output enable for Y and Y
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
A1, B2,
D1, J2,
K1, A6,
B5, D6,
J5, K6
O
Buffered output copies of input clock, CLK
Y[0:9]
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
A2, B1,
D2, J1,
K2, A5,
B6, D5,
J6, K5
O
Buffered output copies of input clock, CLK
2.5-V Supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.6°C/W
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
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SCAS689 − FEBRUARY 2003
recommended operating conditions (see Note 4)
MIN
VDDQ
AVDD
Supply voltage
TYP
MAX
2.3
2.7
V
VDDQ − 0.12
2.7
V
−0.3
VDDQ/2 – 0.18
0.7
V
CLK, CLK, FBIN, FBIN
Low-level input voltage, VIL
PWRDWN
CLK, CLK, FBIN, FBIN
High-level input voltage, VIH
PWRDWN
VDDQ/2 + 0.18
1.7
DC input signal voltage (see Note 5)
VDDQ + 0.3
VDDQ + 0.3
–0.3
Differential input signal voltage, VID (see Note 6)
dc
CLK, FBIN
0.36
ac
CLK, FBIN
0.7
Input differential pair cross voltage, VIX (see Note 7)
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2 – 0.2
VDDQ/2 + 0.2
−12
High-level output current, IOH
Low-level output current, IOL
Input slew rate, SR
Commercial
Operating free-air temperature, TA
UNIT
Industrial
V
V
V
V
mA
12
mA
1
4
V/ns
0
85
−40
85
°C
NOTES: 4. The unused inputs must be held high or low to prevent them from floating.
5. The dc input signal voltage specifies the allowable dc execution of the differential input.
6. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
7. The differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must
be crossing.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input voltage
All inputs
VOH
High-level output voltage
VOL
Low-level output voltage
VOD
Output voltage swing}
VOX
Output differential cross-voltagew
II
IOZ
Input current
High-impedance state output current
IDDPD
Power-down current on
VDDQ + AVDD
AIDD
Supply current on AVDD
VDDQ = 2.3 V, II = –18 mA
VDDQ = min to max, IOH = –1 mA
VDDQ = 2.3 V, IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
MIN
TYP†
UNIT
–1.2
V
VDDQ – 0.1
1.7
V
0.1
VDDQ = 2.3 V, IOL = 12 mA
Differential outputs are terminated
with 120 Ω /CL = 14 pF (See
Figure 3)
MAX
0.6
1.1
V
VDDQ – 0.4
V
VDDQ/2 – 0.15
VDDQ = 2.7 V, VI = 0 V to 2.7 V
VDDQ = 2.7 V, VO= VDDQ or GND
CLK and CLK = 0 MHz; PWRDWN
= Low; Σ of IDD and AIDD
fO = 170 MHz
fO = 200 MHz
VDDQ/2
VDDQ/2 + 0.15
±10
µA
±10
µA
20
100
µA
7
10
9
12
mA
CI
Input capacitance
VDDQ = 2.5 V, VI = VDDQ or GND
2
2.5
3.5
pF
† All typical values are at a respective nominal VDDQ.
‡ The differential output signal voltage specifies the differential voltage VTR − VCP, where VTR is the true output level and VCP is the
complementary output level.
§ The differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
The frequency range is 100 MHz to 200 MHz.
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5
SCAS689 − FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
TYP†
MAX
fO = 170 MHz
fO = 200 MHz
100
110
105
120
Differential outputs
terminated with
120 Ω/CL = 0 pF
fO = 170 MHz
200
240
fO = 200 MHz
210
250
Differential outputs
terminated with
120 Ω/CL = 14 pF
fO = 170 MHz
260
300
fO = 200 MHz
280
320
PARAMETER
TEST CONDITIONS
Without load
IDD
Dynamic current on VDDQ
MIN
UNIT
mA
∆C
Part-to-part input capacitance
variation
VDDQ = 2.5 V, VI = VDDQ or GND
1
pF
CI(∆)
Input capacitance difference between
CLK and CLKB, FBIN, and FBINB
VDDQ = 2.5 V, VI = VDDQ or GND
0.25
pF
3.5
pF
CO
Output capacitance
VDDQ = 2.5 V, VO = VDDQ or GND
† All typical values are at a respective nominal VDDQ.
2.5
3
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
60
200
MHz
40%
60%
Operating clock frequency
fCLK
Application clock frequency
Input clock duty cycle
Stabilization time{ (PLL mode)
Stabilization time} (Bypass mode)
10
µs
30
ns
† The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
switching characteristics
PARAMETER
tPLHw
tPHLw
tjit(per)W
TEST CONDITIONS
TYP
Low to high level propagation delay time
Test mode/CLK to any output
3.5
High-to low level propagation delay time
Test mode/CLK to any output
3.5
Jitter (period), See Figure 7
tjit(cc)W
Jitter (cycle-to-cycle), See Figure 4
tjit(hper)W
Half-period jitter, See Figure 8
tslr(o)
Output clock slew rate, See Figure 9
Static phase offset, See Figure 5
tsk(o)
Output skew, See Figure 6
ns
ns
60
ps
ps
100/133/167/200 MHz
−35
35
66 MHz
−75
75
100/133/167/200 MHz
−50
50
−100
100
−75
75
100/133/167/200 MHz
Load: 120 Ω/14 pF
100/133/167/200 MHz
1
2
–100
100
–50
50
Load: 120 Ω/14 pF
tr, tf
Output rise and fall times (20% − 80%)
Load: 120 Ω/14 pF
§ Refers to the transition of the noninverting output.
¶ This parameter is assured by design but can not be 100% production tested.
POST OFFICE BOX 655303
UNIT
−60
66 MHz
t(Ø)
MAX
66 MHz
66 MHz
6
MIN
• DALLAS, TEXAS 75265
70
600
ps
ps
V/ns
ps
100
ps
900
ps
SCAS689 − FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
VDD
VYx
R = 60 Ω
R = 60 Ω
VDD/2
VYx
CDCV857B
GND
Figure 1. IBIS Model Output Load
VDD/2
CDCV857B
C = 14 pF
R = 10 Ω
Z = 60 Ω
SCOPE
−VDD/2
Z = 50 Ω
R = 50 Ω
V(TT)
Z = 60 Ω
R = 10 Ω
Z = 50 Ω
C = 14 pF
R = 50 Ω
V(TT)
−VDD/2
V(TT) = GND
−VDD/2
Figure 2. Output Load Test Circuit
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7
SCAS689 − FEBRUARY 2003
VDD
CDCV857B
C = 14 pF
PROBE
GND
Z = 60 Ω
C = 1 pF
R = 120 Ω
R = 1 MΩ
V(TT)
Z = 60 Ω
C = 1 pF
C = 14 pF
R = 1 MΩ
V(TT)
GND
V(TT) = GND
GND
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n+1)
tjit(cc) = tc(n) − tc(n+1)
Figure 4. Cycle-to-Cycle Jitter
8
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SCAS689 − FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t( ) n
∑1
t ( ) n+1
n=N
t( ) =
t( ) n
N
(N > 1000 Samples)
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 6. Output Skew
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9
SCAS689 − FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per) = tcn −
1
fo
fO = Average input frequency measured at CLK/CLK
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_n+1)
t(hper_n)
1
fo
tjit(hper) = t(hper_n) − 1
2xfo
n = any half cycle
fO = Average input frequency measured at CLK/CLK
Figure 8. Half-Period Jitter
VOH, VIH
80%
Clock Inputs
and Outputs
80%
20%
20%
VOL, VIL
tr
t
slr(IńO)
V
* V 20%
+ 80%
t
r(IńO)
tf
t
slf(IńO)
V
* V 20%
+ 80%
t
f(IńO)
Figure 9. Input and Output Slew Rates
10
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCV857BDGG
ACTIVE
TSSOP
DGG
48
40
Pb-Free
(RoHS)
CU NIPDAU
CDCV857BDGGR
ACTIVE
TSSOP
DGG
48
2000
None
Call TI
Call TI
CDCV857BGQLR
ACTIVE
VFBGA
GQL
56
1000
None
Call TI
Level-2A-220C-4 WKS
CDCV857BIDGG
ACTIVE
TSSOP
DGG
48
40
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
CDCV857BIDGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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