SCAS688A − JUNE 2003 − REVISED JANUARY 2004 D 1.8-V Phase Lock Loop Clock Driver for D D D D D D D D D D D External Feedback Pins ( FBIN, FBIN ) are Double Data Rate ( DDR II ) Applications Spread Spectrum Clock Compatible Operating Frequency: 10 MHz to 400 MHz Low Current Consumption: <135 mA Low Jitter (Cycle-Cycle): ±30 ps Low Output Skew: 35 ps Low Period Jitter: ±20 ps Low Dynamic Phase Offset:: ±15 ps Low Static Phase Offset:: ±50 ps Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball µBGA (MicroStar Junior BGA, 0,65-mm pitch) and 40-Pin MLF D D D Used to Synchronize the Outputs to the Input Clocks Single-Ended Input and Single-Ended Output Modes Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300 Fail-Safe Inputs description The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C to 85°C. AVAILABLE OPTIONS TA 52-Ball BGA 40-Pin MLF −40°C to 85°C CDCU877ZQL (Pb-Free) CDCU877RTB −40°C to 85°C CDCU877AZQL (Pb-Free) CDCU877ARTB −40°C to 85°C CDCU877GQL −40°C to 85°C CDCU877AGQL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($ (#"! " !%$""! %$ )$ $! $*! !#$! !(( +, (#" %"$!!- ($! $"$!!', "'#($ $!- '' %$$! POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 1 2 3 4 Y6 Y5 Y5 GND Y0 GND Y0 Y1 MicroStar Junior (GQL) Package (TOP VIEW) 5 6 A Y1 GND B Y6 GND C NB Y2 GND Y2 VDDQ VDDQ CK VDDQ CK VDDQ AGND VDDQ VDDQ AVDD GND Y3 GND NB Y7 GND D Y7 OS E NB NB F NB NB VDDQ FBIN VDDQ FBIN OE G FBOUT VDDQ VDDQ NB H NB FBOUT GND J Y8 GND RTB PACKAGE (TOP VIEW) Y1 Y1 Y0 Y0 VDDQ Y5 Y5 Y6 Y6 VDDQ Y8 Y9 GND Y9 GND Y4 Y4 Y3 K 40 39 38 37 36 35 34 33 32 31 VDDQ Y2 Y2 CK CK VDDQ AGND AVDD VDDQ GND NC − No Connection NB − No Ball 1 30 2 29 3 28 4 27 5 GND 26 6 25 7 24 8 23 9 22 21 10 Y7 Y7 VDDQ FBIN FBIN FBOUT FBOUT VDDQ OE OS VDDQ Y9 Y9 Y8 Y8 VDDQ Y3 Y3 Y4 Y4 11 12 13 14 15 16 17 18 19 20 40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size, 0,5 mm Pitch, M0#220, Variation VJJD-2, E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 Table 1. Terminal Functions BGA MLF AGND NAME G1 7 AVDD CK H1 8 E1 4 I Clock input with a (10 kΩ to 100 kΩ) pulldown resistor CK F1 5 I Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor FBIN E6 27 I Feedback clock input FBIN F6 26 I Complementary feedback clock input FBOUT H6 24 O Feedback clock output FBOUT G6 25 O Complementary feedback clock output OE F5 22 I Output enable (asynchronous) I Output select (tied to GND or VDD) OS I/O DESCRIPTION Analog ground Analog power D5 21 GND B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 10 VDDQ D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 1, 6, 9, 15, 20, 23, 28, 31, 36 Y[0:9] A2, A1, D1, J1, K3, A5, A6, D6, J6, K4 38, 39, 3, 11, 14, 34, 33, 29, 19, 16 O Clock outputs Y[0:9] A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 37, 40, 2, 12, 13, 35, 32, 30, 18, 17 O Complementary clock outputs Ground Logic and output power Table 2. Function Table INPUTS OUTPUTS PLL AVDD OE OS CK CK Y Y FBOUT FBOUT GND H X L H L H L H Bypassed/ Off GND H X H L H L H L Bypassed/ Off GND L H L H LZ LZ L H Bypassed/ Off GND L L H L LZ Y7 Active LZ Y7 Active H L Bypassed/ Off 1.8 V Nominal L H L H LZ LZ L H On LZ Y7 Active H L On 1.8 V Nominal L L H L LZ Y7 Active 1.8 V Nominal H X L H L H L H On 1.8 V Nominal H X H L H L H L On 1.8 V Nominal X X L L LZ LZ LZ LZ Off X X X H H POST OFFICE BOX 655303 Reserved • DALLAS, TEXAS 75265 3 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 Figure 1. Logic Diagram (Positive Logic) 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDDQ or AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDDQ + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Output clamp voltage, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VDDQ or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed 2. This value is limited to 2.5 V maximum. recommended operating conditions MIN VDDQ Output supply voltage AVDD Supply voltage 1.7 See Note 1 VIL VIH Low-level input voltage (see Note 2) OE, OS High-level input voltage (see Note 2) CK, CK IOH IOL High-level output current (see Figure 2) VIX VI Input differential-pair cross voltage VID Input differential voltage (see Note 2 and Figure 9) TA NOM MAX UNIT 1.8 1.9 V 0.35 × VDDQ V VDDQ 0.65 × VDDQ Low-level output current (see Figure 2) V −9 mA 9 mA (VDDQ/2)−0.15 −0.3 (VDDQ/2)+0.15 VDDQ+0.3 V DC 0.3 0.6 VDDQ+0.4 VDDQ+0.4 V AC −40 85 °C Input voltage level Operating free-air temperature V V NOTES: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are ensured. 2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK VIH and VIL limits define the dc low and high levels for the logic detect state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range PARAMETER VIK Input (cl inputs) VOH High-level output voltage TEST CONDITIONS II = 18 mA Low-level output voltage IO(DL) VOD Low-level output current, disabled II IOH = −9 mA IOL = 100 µA 1.7 V IOL = 9 mA VO(DL) = 100 mV, OE = L 1.7 V CI(∆) I ) Change in input current UNIT −1.2 V VDDQ − 0.2 V 1.1 0.1 0.6 1.7 V 100 1.7 V 0.5 V OE, OS, FBIN, FBIN 1.9 V ±10 CK and CK = L 1.9 V 500 CK and CK = 270 MHz, All outputs are open (not connected to a PCB) 1.9 V 135 All outputs are loaded with 2 pF and 120-Ω termination resistor 1.9 V FBIN, FBIN CK, CK FBIN, FBIN V µA ±250 CK, CK Input capacitance MAX 1.9 V Supply current, dynamic (IDDQ + IADD) (see Note 2 for CPD calculation) CI TYP CK, CK IDD(LD) Supply current, static (IDDQ + IADD) IDD 1.7 V to 1.9 V Differential output voltage (see Note 1) Input current MIN 1.7 V IOH = −100 µA VOL AVDD, VDDQ µA µA mA 235 VI = VDD or GND VI = VDD or GND 1.8 V 2 3 1.8 V 2 3 VI = VDD or GND VI = VDD or GND 1.8 V 0.25 1.8 V 0.25 pF pF NOTES: 1. VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. 2. Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. timing requirements over recommended operating free-air temperature range PARAMETER TEST CONDITIONS fCK fCK Clock frequency (operating, see Notes 1 and 2) tDC tL Duty cycle, input clock Clock frequency (application, see Notes 1 and 3) Stabilization time (see Note 4) AVDD, VDD = 1.8 V ±0.1 V AVDD, VDD = 1.8 V ±0.1 V AVDD, VDD = 1.8 V ±0.1 V AVDD, VDD = 1.8 V ±0.1 V MIN TYP MAX UNIT 10 400 MHz 160 340 MHz 40% 60% 12 µs NOTES: 1. The PLL must be able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 1) AVDD, VDD = 1.8 V ±0.1 V PARAMETER ten tdis TEST CONDITIONS Enable time, OE to any Y/Y See Figure 11 Disable time, OE to any Y/Y See Figure 11 tjit(cc+) Cycle-to-cycle period jitter (see Note 8) tjit(cc−) 160 MHz to 190 MHz, see Figure 4 tjit(cc+) Cycle-to-cycle period jitter (see Note 8) tjit(cc−) 190 MHz to 340 MHz, see Figure 4 MIN TYP MAX UNIT 8 ns 8 ns 0 40 0 −40 0 30 0 −30 ps ps t(ϕ) Static phase offset time (see Note 2) t(ϕ)dyn Dynamic phase offset time See Figure 5 −50 50 ps See Figure 10 −15 15 ps tsk(o) Output clock skew See Figure 6 35 ps tjit(per) Period jitter (see Notes 3 and 8) 160 MHz to 190 MHz, see Figure 7 −30 30 ps 190 MHz to 340 MHz, see Figure 7 −20 20 ps 160 MHz to 190 MHz, see Figure 8 −115 115 ps 190 MHz to 250 MHz, see Figure 8 −70 70 ps 250 MHz to 300 MHz, see Figure 8 −40 40 ps 300 MHz to 340 MHz, see Figure 8 −60 60 ps Slew rate, OE See Figure 3 and Figure 9 0.5 Input clock skew rate See Figure 3 and Figure 9 1 2.5 4 V/ns Output clock slew rate (see Notes 4 and 5) See Figure 3 and Figure 9 1.5 2.5 3 V/ns tjit(hper) Half-period jitter (see Notes 3 and 8) SR VOX Output differential-pair cross voltage (see Note 6) V/ns See Figure 2, CDCU877 (VDDQ/2) − 0.1 (VDDQ/2) + 0.1 See Figure 2, CDCU877A (see Note 7) (0−85°C) (VDDQ/2) − 0.1 (VDDQ/2) + 0.1 SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth 30 33 0% −0.5% 2 V kHz MHz NOTES: 1. There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. 2. Phase static offset time does not include jitter. 3. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. 4. The output slew rate is determined from the IBIS model into the load shown in Figure 3. 5. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 6. Output differential-pair cross voltage specified at the DRAM clock input or the test load. 7. VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application. 8. This parameter is assured by design and characterization. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 Figure 2. Output Load Test Circuit 1 Figure 3. Output Load Test Circuit 2 Figure 4. Cycle-To-Cycle Period Jitter 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 Figure 5. Static Phase Offset Figure 6. Output Skew POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 Figure 7. Period Jitter Figure 8. Half-Period Jitter 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 80% 80% VID, VOD Clock Inputs and Outputs, OE 20% 20% tr(i), tr(o) slrr(i/o) = V80% V20% tr(i/o) tf(i) , tf(o) slrf(i/o) = V80% V20% tf(i/o) Figure 9. Input and Output Slew Rates Figure 10. Dynamic Phase Offset Figure 11. Time Delay Between OE and Clock Output (Y, Y) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 RECOMMENDED AVDD FILTERING Bead 0603 CARD VIA AV DD VDDQ 1 Ohm 4.7 uF 1206 0.1 uF 0603 2200 pF 0603 PLL GND AGN D CARD VIA See Notes 9, 10, and 11 Figure 12. Recommended AVDD Filtering NOTES: 9. Place the 2200-pF capacitor close to the PLL. 10. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). 11. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS688A − JUNE 2003 − REVISED JANUARY 2004 THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, Quad Flatpack No-Lead Packages, Texas Instruments Literature No. SCBA017. This document is available at www.ti.com. The exposed thermal pad dimensions for this package are shown in the following illustration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCU877AGQLR ACTIVE VFBGA GQL 52 1000 None Call TI Level-3-235C-168 HR CDCU877AGQLT ACTIVE VFBGA GQL 52 250 None Call TI Level-3-235C-168 HR CDCU877ARTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level-3-235C-168 HR CDCU877ARTBT ACTIVE QFN RTB 40 250 None CU SNPB Level-3-235C-168 HR CDCU877AZQLR ACTIVE VFBGA ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877AZQLT ACTIVE VFBGA ZQL 52 250 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877GQLR ACTIVE VFBGA GQL 52 1000 None Call TI Level-3-235C-168 HR CDCU877GQLT ACTIVE VFBGA GQL 52 250 None Call TI Level-3-235C-168 HR CDCU877RTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level-3-235C-168 HR CDCU877RTBT ACTIVE QFN RTB 40 250 None CU SNPB Level-3-235C-168 HR CDCU877ZQLR ACTIVE VFBGA ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU877ZQLT ACTIVE VFBGA ZQL 52 250 SNAGCU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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