SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE SN74173 . . . N PACKAGE SN74LS173A . . . D or N PACKAGE (TOP VIEW) M N 1Q 2Q 3Q 4Q CLK GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLR 1D 2D 3D 4D G2 G1 SN54LS173A . . . FK PACKAGE (TOP VIEW) 1Q 2Q NC 3Q 4Q CLR D 3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs N M NC V CC D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 1D 2D NC 3D 4D CLK GND NC G1 G2 9 10 11 12 13 The ’173 and ’LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The NC – No internal connection high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 FUNCTION TABLE INPUTS DATA ENABLE DATA D OUTPUT Q CLR CLK H X X X X L L L X X X Q0 L ↑ H X X Q0 L ↑ X H X Q0 L ↑ L L L L L ↑ L L H H G1 G2 When either M or N (or both) is (are) high, the output is disabled to the high-impedance state; however, sequential operation of the flip-flops is not affected. logic symbol† ’173 CLR M N G1 G2 CLK 1D 2D 3D 4D 15 1 R & 2 9 10 ’LS173A CLR M EN N & G1 C1 G2 7 14 13 CLK 1D 3 4 12 5 11 6 1Q 1D 2Q 2D 3Q 3D 4Q 4D 15 1 2 9 10 POST OFFICE BOX 655303 EN & C1 7 14 13 1D 3 4 12 5 11 6 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, N, and W packages. 2 R & • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 logic diagram (positive logic) Output Control M N 1D G1 Data Enable G2 2D 1 2 1D 14 C1 9 R 10 3 1Q 1D 13 C1 CLK 3D 4 R 7 2Q 1D 12 C1 5 R 4D 3Q 1D 11 C1 CLR R 15 6 4Q Pin numbers shown are for D, J, N, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 schematics of inputs and outputs ’173 ’LS173A Equivalent of Each Input Equivalent of Each Input VCC VCC 4 kΩ NOM 20 kΩ NOM Input Input Typical of All Outputs Typical of All Outputs VCC VCC 90 Ω NOM 100 Ω NOM Output Output absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage: ’173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V ’LS173A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 recommended operating conditions (see Note 3) SN54173 VCC IOH Supply voltage IOL TA Low-level output current SN74173 NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V –5.2 mA 16 mA 70 °C High-level output current –2 16 Operating free-air temperature UNIT MIN –55 125 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL TEST CONDITIONS† MIN SN54173 TYP‡ MAX 2 Low-level input voltage VCC = MIN, VCC = MIN, VIL = 0.8 V, II = –12 mA VIH = 2 V, IOH = MAX Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA IO( O(off) ff) Off-state ((high-impedance g state)) output current VCC = MAX,, VIH = 2 V VO = 2.4 V VO = 0.4 V II Input current at maximum input voltage VCC = MAX, VCC = MAX, VCC = MAX, IIH IIL High-level input current IOS ICC Short-circuit output current§ Low-level input current MIN SN74173 TYP‡ MAX 2 UNIT V 0.8 0.8 V –1.5 –1.5 V 2.4 2.4 V 0.4 0.4 V 150 40 –150 –40 VI = 5.5 V 1 1 VI = 2.4 V VI = 0.4 V 40 40 µA –1.6 –1.6 mA –70 mA VCC = MAX VCC = MAX, –30 –70 –30 µA mA Supply current See Note 4 50 72 50 72 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded; and CLK and M at 4.5 V. timing requirements over recommended operating conditions (unless otherwise noted) fclock tw Input clock frequency tsu Setup time th SN54173 SN74173 MIN MIN MAX 25 Pulse duration Hold time 20 20 Data enable (G1, G2) 17 17 Data 10 10 CLR (inactive state) 10 10 Data POST OFFICE BOX 655303 25 CLK or CLR Data enable (G1, G2) • DALLAS, TEXAS 75265 MAX 2 2 10 10 UNIT MHz ns ns ns 5 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1) PARAMETER 6 TEST CONDITIONS fmax Maximum clock frequency tPHL Propagation delay time, high-to-low-level output from clear input tPLH Propagation delay time, low-to-high-level output from clock input tPHL Propagation delay time, high-to-low-level output from clock input tPZH Output enable time to high level tPZL Output enable time to low level tPHZ Output disable time from high level tPLZ Output disable time from low level SN54173 MIN TYP 25 35 POST OFFICE BOX 655303 MIN TYP 25 35 MAX UNIT MHz 18 27 18 27 28 43 28 43 19 31 19 31 7 16 30 7 16 30 7 21 30 7 21 30 3 5 14 3 5 14 3 11 20 3 11 20 CL = 50 pF CL = 5 pF SN74173 MAX ns ns • DALLAS, TEXAS 75265 ns ns SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 recommended operating conditions SN54LS173A VCC IOH Supply voltage IOL TA Low-level output current SN74LS173A NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 V –2.6 mA 24 mA 70 °C High-level output current –1 12 Operating free-air temperature UNIT MIN –55 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low level output voltage Low-level TEST CONDITIONS† SN54LS173A TYP‡ MAX MIN 2 SN74LS173A TYP‡ MAX MIN 2 Low-level input voltage V 0.8 V –1.5 –1.5 V II = –18 mA VIH = 2 V, IOH = MAX VCC = MIN,, VIL = 0.8 V, IOL = 12 mA IOL = 24 mA 20 20 –20 –20 3.4 0.25 UNIT 0.7 VCC = MIN, VCC = MIN, VIL = VILmax, 2.4 UNIT 2.4 0.4 3.1 V 0.25 0.4 V 0.35 0.5 V IO( O(off) ff) Off-state ((high-impedance g state)) output current VCC = MAX,, VIH = 2 V VO = 2.7 V VO = 0.4 V II Input current at maximum input voltage VCC = MAX, VI = 7 V 0.1 0.1 mA VCC = MAX, VCC = MAX, VI = 2.7 V VI = 0.4 V 20 20 µA –0.4 mA –130 mA IIH IIL High-level input current IOS ICC Short-circuit output current§ Low-level input current Supply current VCC = MAX VCC = MAX, –0.4 –30 See Note 4 –130 19 –30 30 19 V 24 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded; and CLK and M at 4.5 V. timing requirements over recommended operating conditions (unless otherwise noted) SN54LS173A MIN fclock tw Input clock frequency tsu Setup time th MAX SN74LS173A MIN 30 Pulse duration Hold time POST OFFICE BOX 655303 25 CLK or CLR 25 25 Data enable (G1, G2) 35 35 Data 17 17 CLR (inactive state) 10 10 Data enable (G1, G2) 0 0 Data 3 3 • DALLAS, TEXAS 75265 MAX UNIT MHz ns ns ns 7 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2) PARAMETER 8 TEST CONDITIONS fmax Maximum clock frequency tPHL Propagation delay time, high-to-low-level output from clear input tPLH Propagation delay time, low-to-high-level output from clock input tPHL SN54LS173A MIN TYP 30 50 SN74LS173A MAX MIN TYP 30 50 MAX MHz 26 35 26 35 17 25 17 25 Propagation delay time, high-to-low-level output from clock input 22 30 22 30 tPZH Output enable time to high level 15 23 15 23 tPZL Output enable time to low level 18 27 18 27 tPHZ Output disable time from high level 11 20 11 20 tPLZ Output disable time from low level 11 17 11 17 CL = 45 pF CL = 5 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test Point VCC RL From Output Under Test CL (see Note A) 1.5 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 1 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) (see Note B) From Output Under Test CL (see Note A) RL From Output Under Test RL High-Level Pulse Test Point VCC 1.5 V 0V tw Low-Level Pulse 1.5 V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 3V 1.5 V 0V tPHL tPLH VOH 1.5 V 1.5 V 1.5 V 1.5 V VOL 1.5 V tPLZ ≈1.5 V 1.5 V VOL + 0.5 V VOL tPZH Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0V Waveform 1 (see Notes C and D) tPLH VOH 3V tPZL VOL tPHL Out-of-Phase Output (see Note D) 1.5 V 0V 1.5 V In-Phase Output (see Note D) 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th tsu tPHZ 1.5 V VOH VOH – 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point VCC VCC RL From Output Under Test (see Note B) From Output Under Test CL (see Note A) RL S1 (see Note B) From Output Under Test RL CL (see Note A) Test Point CL (see Note A) Test Point 5 kΩ S2 LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 1.3 V 3V Timing Input 1.3 V 1.3 V 0V tw Low-Level Pulse tsu 1.3 V 1.3 V 0V 1.3 V Output Control (low-level enabling) 1.3 V 0V tPHL tPLH VOH 1.3 V 1.3 V tPLH VOH 1.3 V 1.3 V VOL 3V 1.3 V tPLZ ≈1.5 V Waveform 1 S2 Open (see Notes C and D) 1.3 V VOL + 0.3 V VOL tPZH Waveform 2 S2 Closed (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0V tPZL VOL tPHL Out-of-Phase Output (see Note D) 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V In-Phase Output (see Note D) 3V Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th tPHZ 1.3 V VOH VOH – 0.3 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) JM38510/36101B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC JM38510/36101BEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC JM38510/36101BFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC JM38510/36101SEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC JM38510/36101SFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC SN54173J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SN54LS173AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SN74173N OBSOLETE PDIP N 16 TBD Call TI Call TI SN74LS173AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS173ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS173ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS173ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS173AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LS173ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LS173ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS173ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54173J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SNJ54173W OBSOLETE CFP W 16 TBD Call TI Call TI SNJ54LS173AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54LS173AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SNJ54LS173AW ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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