SN74CB3Q3305 www.ti.com SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 DUAL FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH Check for Samples: SN74CB3Q3305 FEATURES 1 • High-Bandwidth Data Path (up to 500 MHz) PW PACKAGE (TOP VIEW) For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008. • • • • • • • • • • • • • • • 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ω Typ) Rail-to-Rail Switching on Data I/O Ports – 0- to 5-V Switching With 3.3-V VCC – 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typ) Fast Switching Frequency (fOE = 20 MHz Max) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 0.25 mA Typ) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating 1OE 1A 1B GND 1 8 2 7 3 6 4 5 VCC 2OE 2B 2A DCU PACKAGE (TOP VIEW) 1OE 1 8 VCC 1A 2 7 2OE 1B 3 6 2B GND 4 5 2A DESCRIPTION/ORDERING INFORMATION The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q3305 is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated SN74CB3Q3305 SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 www.ti.com ORDERING INFORMATION TA –40°C to 85°C PACKAGE TSSOP – PW VSSOP – DCU (1) (2) (1) ORDERABLE PART NUMBER Tube SN74CB3Q3305PW Tape and reel SN74CB3Q3305PWR Tape and reel SN74CB3Q3305DCUR TOP-SIDE MARKING (2) BU305 GAR_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. The last character designates assembly/test site. DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Table 1. FUNCTION TABLE (EACH BUS SWITCH) INPUT OE INPUT/OUTPUT A FUNCTION H B A port = B port L Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 3 1A 1OE 1B SW 1 5 6 2A SW 2B 7 2OE SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) B A VCC Charge Pump EN(1) (1) EN is the internal enable signal applied to the switch. 2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX –0.5 4.6 UNIT V –0.5 7 V –0.5 7 VIN Control input voltage range (2) (3) VI/O Switch I/O voltage range (2) (3) (4) IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±64 mA II/O ON-state switch current (5) Continuous current through VCC or GND θJA Package thermal impedance (6) Tstg Storage temperature range (1) (2) (3) (4) (5) (6) ±100 –65 V mA 88 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) MIN MAX UNIT 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 5.5 V VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 85 °C V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74CB3Q3305 3 SN74CB3Q3305 SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 www.ti.com Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK Control inputs IIN IOZ (3) Ioff ICC TEST CONDITIONS VCC = 3.6 V, II = –18 mA VCC = 3.6 V, VIN = 0 to 5.5 V VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND VCC = 0, VO = 0 to 5.5 V, VI = 0 VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND ΔICC (4) Control inputs ICCD (5) A and B ports open, Per control VCC = 3.6 V, input Control input switching at 50% duty cycle Control inputs Cin MIN TYP (2) MAX UNIT –1.8 V ±1 μA ±1 μA 1 μA 0.7 mA 25 μA 0.25 VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND mA/ MHz 0.040 0.045 2.5 3.5 pF VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 Cio(OFF) VCC = 3.3 V, Switch OFF, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 3.5 5 pF Cio(ON) VCC = 3.3 V, Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 8 10.5 pF 3 8 3.5 9 3 6 3.5 8 ron VCC = 2.3 V, TYP at VCC = 2.5 V (6) VCC = 3 V (1) (2) (3) (4) (5) (6) VI = 0, IO = 30 mA VI = 1.7 V, IO = –15 mA VI = 0, IO = 30 mA VI = 2.4 V, IO = –15 mA Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2 ). Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER fOE (1) 4 TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V MAX MIN UNIT MAX OE A or B 10 20 A or B B or A 0.09 0.15 ns ten OE A or B 1 5 1 4.5 ns tdis OE A or B 1 4.5 1 5 ns tpd (1) (2) FROM (INPUT) (2) MHz Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 TYPICAL ron vs VI ron - ON-State Resistance - Ω 16 VCC = 3.3 V TA = 25°C IO = -15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI - V Figure 1. Typical ron vs VI TYPICAL ICC vs OE SWITCHING FREQUENCY 12 VCC = 3.3 V TA = 25°C A and B Ports Open 10 ICC − mA 8 6 4 One OE Switching 2 0 0 2 4 6 8 10 12 14 16 18 20 OE Switching Frequency − MHz Figure 2. Typical ICC vs OE Switching Frequency Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74CB3Q3305 5 SN74CB3Q3305 SCDS141B – OCTOBER 2003 – REVISED OCTOBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator VI S1 RL VO GND 50 Ω 50 Ω VG2 RL CL (see Note A) TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open tPHZ VOH VCC/2 VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74CB3Q3305 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CB3Q3305DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CB3Q3305DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CB3Q3305PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CB3Q3305DCUR US8 DCU 8 3000 180.0 9.2 2.25 3.35 1.05 4.0 8.0 Q3 SN74CB3Q3305PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CB3Q3305DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74CB3Q3305PWR TSSOP PW 8 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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