ETC CH7002D-V

CH7002D
Preliminary
CHRONTEL
Scalable VGA to NTSC/PAL Encoder
Features
General Description
• Fully integrated solution for PC to TV display
Chrontel’s CH7002 VGA to NTSC/PAL encoder is a standalone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
• TrueScale TM rendering engine supports underscan
operation for both 640x480 or 800x600 inputs †
• Advanced 3-line digital flicker filtering with
programmable algorithm selections †
• Fully programmable through I2C port or hardware
(pin-based) controls
• Wide range of VGA software drivers for full
synchronization and image positioning
This circuit integrates a digital NTSC/PAL encoder with 8bit ADC and DAC interfaces, a 3-line vertical filter, and lowjitter phase-locked loop to create outstanding quality video.
Through Chrontel’s TrueScale TM rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I2C port, to enable fully integrated system
solutions by using a TV as the primary display device.
• Auto-detection of TV presence
• Programmable power management features three
power-down modes
• Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
• Triple 8-bit ADC inputs and triple 8-bit DAC outputs
• On-chip reference generation and loop filter
• Offered in 44-pin PLCC package
PMODE
LEF
SC
ADDR
UP
DOWN
SD
RIGHT
† Patent number 5,781,241
RSET
I2C REGISTER & CONTROL
BLOCK
RSET
LINE
MEMORY
R
R
Y
ADC
G
G
ADC
COLOR
U
SPACE
CONVERTER
B
B
Y
LINE RENDERING ENGINE
V
DAC
Y
DAC
CVBS
DAC
C
OSC
CLKOUT
DIGITAL
U
NTSC/PAL
-SCALING
-DEFLICKERING
-SCAN CONVERSION
ENCODER
V
& FILTER
ADC
SYSTEM CLOCK
VREF
VREF1
PLL
TIMING & SYNC GENERATOR
VREF2
XCLK
H
V
XI
XO
Figure 1: Functional Block Diagram
201-0000-029 Rev 6.1, 8/2/99
1
AGND
RED
AGND
GREEN
AGND
BLUE
AVDD
VREF1
AGND
VREF2
AVDD
5
4
3
2
1
44
43
42
41
40
CH7002D
6
CHRONTEL
AVDD
7
39
AGND
DVDD
8
38
PMODE
UP
9
37
AVDD
DGND
10
36
ADDR/FF0
DOWN
11
35
V
LEFT
12
34
H
RIGHT
13
33
DVDD
DVDD
14
32
XCLK/SD3
CLKOUT
15
31
DGND
DGND
16
30
SC/DM2
XI
17
29
SD/DM1
22
23
24
25
26
27
28
C
CVBS
Y
VDD
RSET
AGND
RESET/DM0
20
NC
21
19
NC
GND
18
XO/FIN
CHRONTEL
CH7002
Figure 2: 44-pin PLCC
2
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CHRONTEL
CH7002D
Table 1. Pin Description
44-Pin
PLCC
Type
Symbol
Description
2, 4, 6, 27,
39,42
Power
AGND
Analog ground
These pins provide the ground reference for the analog section of CH7002,
and MUST be connected to the system ground to prevent latchup. Refer to
the Application Information section for information on proper supply
decoupling.
1, 3, 5
In
B, G, R
VGA Inputs
These pins should be terminated with 75 ohm resistors and isolated from
switching digital signals and video output pins. Refer to the Application
Information section for detailed technical guidance and alternative connection
techniques.
7, 37, 40,
44
Power
AVDD
Analog Supply Voltage
These pins supply the 5V power to the analog section of the CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
15
Out
CLKOUT
Clock Output
This pin defaults to 14.31818 MHz upon power-up and remains active at all
times (including power-down).
8, 14, 33
Power
DVDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
10, 16, 31
Power
DGND
Digital Ground
These pins provide the ground reference for the digital section of CH7002,
and MUST be connected to the system ground to prevent latchup. For
information on proper supply decoupling, refer to the Application Information
section.
17
In
XI
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached
between XI and XO/FIN. However, if an external CMOS clock is attached to
XO/FIN, XI should be connected to ground.
18
In
XO/FIN
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and
XI. An external CMOS compatible clock can be connected to XO/FIN as an
alternative.
25
Power
VDD
26
In
RSET
Reference Resistor
A 324 Ω resistor with short and wide traces should be attached between
RSET and ground. No other connections should be made to this pin.
21
Power
GND
DAC Ground
These pins provide the ground reference for CH7002’s internal DACs. For
information on proper supply decoupling, refer to the Application Information
section.
24
Out
Y
Luminance Output
A 75 Ω termination resistor with short traces should be attached between Y
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
23
Out
CVBS
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DAC Power Supply
These pins supply power to CH7002’s internal DACs. Refer to the Application
Information section for information on proper supply decoupling.
Composite Output
A 75 Ω termination resistor, with short traces, should be attached between
CVBS and ground for optimum performance. Use of additional filters is
discussed in the Application Information section.
3
CHRONTEL
CH7002D
Table 1. Pin Description (continued)
4
44-Pin
PLCC
Type
Symbol
Description
22
Out
C
Chrominance Output
A 75 Ω termination resistor, with short traces, should be attached between C
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
9, 11, 12,
13
In
UP,
DOWN,
LEFT,
RIGHT
Position Controls (low-to-high transition, internal pull-up)
UP, DOWN, LEFT, and RIGHT, allows the screen display position to be
moved incrementally, in each respective direction, for every toggle of this pin
to ground. An internal schmitt trigger minimizes switch bounce problems.
These pins may be connected directly to the power supply or ground.
28
In
RESET*/D
M0
Reset (active low) /Display Mode Select [0] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), the RESET*/DM0 pin becomes
RESET*. In this mode, when RESET* is held high (default), the chip is in
operating state, and when RESET* is pulled low, the entire chip is reset and
initialized to its power-up state.
When the PMODE pin is pulled low, this pin becomes DM0, which combined
with DM1 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in Application Information and Registers
and Programming sections.
29
In/Out
SD/DM1
Serial Data/Display Mode Select [1] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SD, the serial
data pin of the I2C interface port.
When the PMODE pin is pulled low, this pin becomes DM1, which combined
with DM0 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described under the programming section.
30
In
SC/DM2
Serial Clock/Display Mode Select [2] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SC, the serial
clock pin of the I2C interface port.
When the PMODE pin is pulled low, this pin becomes DM2, which combined
with DM0 and DM1, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in the Registers and Programming and
Application Information sections.
32
In
XCLK/SD3
External Clock/Sample Delay (bit 3) (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes XCLK or
external clock, which accepts an external pixel clock input.
When the PMODE pin is pulled low, this pin becomes SD3 or Sample Delay,
the function corresponding to bit 3 of the Sample Delay register, which
provides the following selection:
SD3
Sample Delay Selected
1
20 ns nominal delay
0
0 delay (default)
This pin-programming is “mux-ed” with the Sample Delay register (bit 3). All
related modes are described in the Registers and Programming section.
35
In
V
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The capacitive
loading on this pin should be kept to a minimum.
34
In
H
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should be kept to a minimum. Refer to the
Application Information section for PC Board layout considerations.
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CHRONTEL
CH7002D
Table 1. Pin Description (continued)
44-Pin
PLCC
Type
Symbol
36
In
ADDR/FF0
Description
I2C Address Select/Flicker Filter (bit 0)(internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes ADDR or I2C
Address Select, which corresponds to bits 1 and 0 of the I2C device address
(see the I2C Control Port Operation section for details), creating an address
selection as follows:
ADDR I2C Address Selected
1
1110101 = 75H = 117
0
1110110 = 76H = 118
When the PMODE pin is pulled low, this pin becomes FF0 or Flicker Filter
select, the function of which corresponds to bit 0 of the Flicker Filter register,
which selects between the following:
FF0
Flicker Filter Mode
0
0:1:0 No filtering
1
1:2:1 Moderate filtering (default)
This pin-programming is “mux-ed” with the Flicker Filter register (bit 0). All
related modes are described under the Registers and Programming section.
38
In
PMODE
Programming Mode (internal pull-up)
The PMODE pin selects between the two alternative programming modes for
the CH7002, which in turn alters the function of five additional pins
(RESET/DM0, SD/DM1, SC/DM2, XCLK/SD3, and ADDR/FF0). When
PMODE is kept high (default), the chip is placed in I2C programming mode.
When PMODE is pulled low, the chip is placed in direct pin programming
mode.
41
In
VREF2
Internal Voltage Reference
VREF2 provides a typical 2.5V reference that is used as an internal bias to
the ADCs. A 0.1 µF decoupling capacitor should be connected between
VREF2 and ground.
43
In
VREF1
ADC Voltage Reference Input / Output
VREF1 provides a typical 1.235V reference that sets the RGB input full scale
at 0.75V. A 0.1 µF decoupling capacitor should be connected between
VREF1 and ground. VREF1 may also be forced by external reference, where
(VFS is the full scale input voltage):
VFS ~ VREF1 * 0.75/1.235
19, 20
NC
NC
No Connect
Note: For complete information concerning external signal connections, terminations, and system design considerations,
refer to the Application Information section.
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CHRONTEL
CH7002D
Functional Description
The CH7002 is a fully integrated system solution for converting analog RGB and synchronization signals from a
standard VGA source into high-quality NTSC or PAL video signals. This solution involves both hardware and
software elements, which work together, to produce an optimum TV screen image based on the original computer
generated pixel data. All essential circuitry for this conversion are integrated on chip. On-chip circuitry includes:
memory, memory control, scaling, PLL, ADC, DAC, filters, and a NTSC/PAL encoder. All internal signal
processing, including NTSC/PAL encoding, is performed using digital techniques, to ensure that the high-quality
video signals are not affected by drift issues associated with analog components. No additional adjustment is
required during manufacturing.
CH7002 is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. The
CH7002 is designed to provide an ideal solution for computer motherboards, add-on graphics cards, TV-sets, and
scan converter boards.
Architectural Overview
The CH7002 is a complete TV output subsystem, using both hardware and software elements, to produce an image
on TV, that is virtually identical to the image that would be displayed on a monitor. Creating a compatible TV
output from a VGA input is a relatively straightforward process. This process includes a standard conversion from
RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, then encoding the
pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a
TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a
compatible TV output that displays a sharp and stable image of the right size, with minimal artifacts from the
conversion process.
As a key part of the overall system solution, the CH7002 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600),
the CH7002 software may be invoked to establish the appropriate TV output display. The software then programs
the various timing parameters of the VGA controller to create an output signal that will be compatible with the
chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates,
total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7002 can render
a superior TV image, without the added cost of a full frame buffer memory, normally used to implement features
such as scaling and full synchronization. Without this added system software, TV output solutions can only
guarantee compatible operation in VGA standard mode 12 (640x480x16 color, 60 Hz).
The CH7002 hardware accepts direct VGA outputs (analog RGB inputs), which are digitized on a pixel-by-pixel
basis by three 8-bit video A/D converters. The digitized RGB inputs are then color space converted into YUV in 42-2 format (encoded into luminance (Y) and color-difference (U,V) signals) and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling, and 3-line vertical flicker
filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL
scan-rates; the vertical flicker filter eliminates flicker at the output, while the underscan scaling reduces the size of
the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to
minimize aliasing problems. The digital encoder receives the filtered signals and transforms the signals into
composite and S-Video outputs, which are converted by the three 8-bit DACs into analog outputs.
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CHRONTEL
CH7002D
Clock Generation and Video Timing
All clock signals of the CH7002 are generated from the VGA synchronization inputs by a low-jitter, PLL circuit.
The VGA input and sync timing are illustrated in Figures 3, 5 and 6. The VGA pixel clock is generated internally,
using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in
preventing aliasing artifacts. All synchronization and color burst envelope pulses are internally generated, using
only the timing signals provided by the VGA synchronization inputs.
In situations where the CH7002 is placed next to a graphics controller (e.g. motherboard or add-in cards), the
graphics pixel clock can be provided to CH7002, directly from the graphics controller via pin XCLK. This
arrangement minimizes phase jitter of the system clock used in the encoder. See the sections on Application
Information and Registers and Programming for detailed information on how to connect and enable this function.
31.78 µs
H
25.42 µs
3.81 µs
R,G,B
DATA
ACTIVE VIDEO
1.91 µs
0.64 µs
Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode
Figure 3: Typical VGA Input Timing
31.78 µs
H
63.56 µs
V*
(ACTIVE LOW)
Figure 4: VGA Horizontal and Vertical Sync Input Timing
Note: The values shown in Figures 4 and 5 represent typical timing parameters for VGA controllers operating in 640x480
resolution at 60 Hz, with the CH7002 in overscan mode. Other resolutions and display modes have different timing
requirements.
EXT
PCLK
HSYNC and
VSYNC
t1
EXT
PCLK
HSYNC and
V
VSYNC
SYNC
t2
Figure 5: External Clock Input Timing
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CHRONTEL
CH7002D
Color Burst Generation*
The CH7002 employs a proprietary technique for generating the color sub-carrier frequency. This method allows
the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the accuracy of
the sub-carrier frequency independent of the sampling rate. As a result, the CH7002 is compatible with any VGA
chip, since the CH7002 sub-carrier frequency is not dependent on the pixel rates of VGA manufacturers. This
feature is a significant benefit, since even a ± 0.01% sub-carrier frequency variation may be enough to cause some
television monitors to lose color lock.
Internal Voltage Reference
The on-chip generated ADC voltage references are brought out to pins VREF1 and VREF2 for decoupling purposes.
VREF1 and VREF2 should each have a 0.1 µF decoupling capacitor between each pin and ground. VREF2 provides
a typical 2.5V reference used for setting the internal bias to the ADCs. VREF1 provides a typical 1.235V reference
used for setting the RGB input full scale at 0.75V. VREF1 can be forced by an external voltage reference to
accommodate different RGB input ranges. An additional on-chip bandgap circuit is used, in the DAC, to generate a
reference voltage, which in conjunction with a reference resistor at pin RSET, sets the output ranges of the DACs.
For each DAC, the current output per LSB step is determined by the following equation:
ILSB = V(RSET)/RSET * 1/24 = 1.235/324 * 1/24 = 159 uA (nominal)
The value of RSET can be adjusted to achieve a desired output signal level. A valid range for RSET is any value at
or over 300 ohms.
Operating Modes
The CH7002 is designed to accept certain limited input resolutions, primarily 640x480 and 800x600, from a VGA
type graphics controller. The CH7002 is also designed to support both NTSC and PAL output formats, with scaling
to provide either an overscanned or underscanned image, when displayed on a TV. This combination of input
resolution and output formatting results in a matrix of operating modes which are listed below, and are described in
detail in Table 2. Note that all of these modes may be set either by I2C programming or by direct pin programming:
8
•
•
Modes 2 and 3 support 640x480 into a NTSC format in overscan and underscan forms respectively.
Modes 1 and 4 support 640x480 into a PAL format in underscan and overscan forms respectively. Note that
Mode 1 is the recommended operating mode for this resolution because it provides a higher overall quality
image.
•
•
Modes 0 and 5 support 800x600 into a PAL format in underscan and overscan forms respectively.
Mode 6 supports 800x600 into a NTSC format in an underscan form.
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CHRONTEL
CH7002D
Operating Modes (Continued)
Table 2. CH7002 Operating Modes
PAL OUT
800x600 IN
PAL OUT
640x480 IN
Underscan
NTSC
640x480 IN
Overscan
NTSC OUT
640x480 IN
Underscan
PAL OUT
640x480 IN
Overscan
PAL OUT
800x600 IN
Overscan
NTSC OUT
800x600 IN
Underscan
Mode
0
1
2
3
4
5
6
Pixel
Clock
35.400
25.000
25.175
28.196
25.000
29.500
43.636
Scale
Factor
5/6
1/1
1/1
7/8
1/1
1/1
3/4
Total VGA
Lines
750
625
525
600
625
625
700
Active
VGA Lines
600
480
480
480
480
600
600
Fvert VGA
(Hz)
50.0
50.00
59.94
59.94
50.00
50.00
59.94
Fhor VGA
(KHz)
37.5
31.250
31.469
35.964
31.250
31.250
41.958
Total TV
Lines
625
625
525
525
625
625
525
Active TV
Lines
500
480
480
420
480
600
450
Fvert TV
(Hz)
50.00
50.00
59.94
59.94
50.00
50.00
59.94
Fhor TV
(Hz)
15625.0
15625.0
15734.3
15734.3
15625.0
15625.0
15734.3
Name
Overscan/Underscan
The inclusion of both overscan and underscan forms of output display have been created to enable optimal use of the
CH7002 for different application needs. In general, underscan provides an image that is entirely viewable on screen.
It should be used as the default for most applications (e.g. viewing text screens, operating games, running
productivity applications, working within Windows). Overscan provides an image that bleeds past the edges of the
TV screen, exactly like normal television programs and movies appear on TV. It is only recommended for viewing
movies or video clips coming from the computer.
Anti-Flicker Filter
The CH7002 integrates a 3-line vertical filter circuit to help eliminate the flicker associated with interlaced displays.
When operating in underscan mode, this flicker circuit provides a adaptive filter algorithm for implementing flicker
reduction based on an approximate 1:2:1 weighting sequence. When operating in overscan mode, it provides four
anti-flicker filter modes as shown in Table 3. These modes are fully selectable, via I2C, and a subset is selectable
(either 0:1:0 filtering or 1:2:1 filtering) when using direct pin programming mode.
Table 3. Anti-Flicker Filter Modes
9
FF0
FF1
Filter Modes
0
0
0:1:0 averaging (no filtering)
0
1
1:3:1 averaging
1
0
1:2:1 averaging
1
1
1:1:1 averaging
*Patent number 5,874,846
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CHRONTEL
CH7002D
Power Management
The CH7002 supports four operating states (including Normal [On], Power Down, S-Video Off, and Composite
Off) to provide optimal power consumption for the application involved. Using the programmable power down
modes accessed over the I2C port, the CH7002 may be placed in either Normal state, or any of the four power
managed states listed below (see the Miscellaneous Control Register under the Registers and Programming
section). To support power management, a TV sensing function (see Connection Detect Register) is provided, which
identifies whether a TV is connected to S-Video or Composite, or neither. This sensing function can then be used to
enter into the appropriate operating state (e.g., if TV is sensed only on Composite, the S-Video Off mode could be
set by software).
Power State
Functional Description
Normal (On):I
In the normal operating state, all functions and pins are active
Power Down:I
In the complete power-down state, most pins and circuitry are
disabled.The CLKOUT pin, however, will continue to provide
14.318 Mhz out. This places the CH7002 in its lowest power
consumption mode
Composite Off
In Composite-off state, power is shut off to the unused DAC
associated with CVBS output, thereby reducing power by
approximately 10%
S-Video Off
Power is shut off to the unused DAC associated with CVBS output
When using direct pin-programming mode for the CH7002, only Normal and Power Down states are supported as
selected by the Display Mode inputs. When inputs DM[2:0] are set to a 111 state, the CH7002 is placed in Power
Down state. The CH7002 operates in Normal mode when the Display Mode settings are set to any valid state (where
DM[2:0] is between 000 and 110).
Luminance Filter Options
The CH7002 contains a set of luminance filters to provide a controllable bandwidth output on both composite and SVideo outputs. The response of the luminance filters are shown in the graphs in Figures 7 and 8. The horizontal axis
is frequency in Mhz, and the vertical axis is gain in dBs.
The possible S-Video MHz responses are:
Y_SV0: A high frequency response, selected by setting YC-HI to 1 in the Y-filter register.
Y_SV1: A lower frequency response, selected by setting YC-HI to 0 in the Y-filter register.
Y_SV2: A lower frequency response, with peaking enabled, which gives improved transient response,
with matching pre-shoot and overshoot of 6%. This is selected by setting YC-HI to 0 and
YPEAKD to 0 in the Y-filter register. Note that peaking can only be enabled in the lower
frequency response mode.
The possible CVBS (composite) responses are:
Y_CV0: A high frequency response, selected by setting YCV-HI to 1 in the Y-filter register.
Y_CV1: A lower frequency response, selected by setting YCV-HI to 0 in the Y-filter register. This setting
will result in a reduced amount of cross-luminance artifacts.
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CH7002D
0
-1
-2
-3
-4
dB
Y_SV0
Y_SV1
-5
-6
-7
-8
-9
-10
0
Y_SV2
Y_CVO
Y_CV1
1
2
3
4
5
6
Freq (MHz)
Figure 6: Luminance Frequency Response - Detailed View
0
Y_SV0
-10
Y_SV1
-20
Y_SV2
-30
Y_CVO
dB
Y_CV1
-40
0
1
2
3
4
5
6
7
8
9
10
11
12
Freq (MHz)
Figure 7: Luminance Frequency Response - Full View
Notes:
1 The curves shown are valid for operating modes 2 and 6. Mode 0 frequency values are 20% higher, mode 1
and 3 frequency values are 12% higher, and mode 4 frequency values are 1% lower, due to changes in clock
frequencies.
2 The Y_SV1 and Y_CV0 responses are identical; therefore the curves lie on top of each other.
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CHRONTEL
CH7002D
NTSC and PAL Operation
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to
characterize these outputs are listed in Table 4 and shown in Figure 8. (See Figures 9 through 16 for illustrations of
composite and S-Video output waveforms.)
Table 4. NTSC/PAL Composite Output Timing Parameters (in µS)
Symbol
Level (mV)
Description
Duration (uS)
NTSC
PAL
NTSC
PAL
A
Front Porch
310
310
1.49 - 1.52
1.50 - 1.78
B
Horizontal Sync
24
24
4.69 - 4.72
4.43 - 4.73
C
Breezeway
310
310
0.60
0.57 - 0.60
D
Color Burst
310
310
2.48 - 2.50
2.33 - 2.52
E
Back Porch
310
310
1.60
1.50 - 1.60
F
Black
363
310
0.92 - 3.64
0.00 - 4.24
G
Active Video
363-1030
310-977
45.40 - 50.84
45.20 - 53.00
H
Black
363
310
0.92 - 3.64
0.00 - 4.24
Notes: For this table and all subsequent figures: RSET = 324 ohms; V(RSET) = 1.235 V; 75 ohms doubly terminated
load (BLR=61 for NTSC, and BLR=52 for PAL), 100% amplitude, 100% saturation bars are shown (100%=0.66071V).
1 Durations vary slightly in different modes due to the different clock frequencies used.
2 Active video times vary greatly due to different scaling ratios used in different modes.
3 Black times (F and H) vary with position controls.
A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
12
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
START
OF
VSYNC
ANALOG
FIELD 1
520
521
522
523
524
525
1
2
3
4
5
6
7
8
9
ANALOG
FIELD 2
258
259
260
261
262
263
264
265
266
267
268
270
269
271
272
9
10
LINE RATE = HALF THE VGA LINE RATE IN MODES 1, 2, 4 AND 5
LINE RATE
= HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480)
FIELD RATE = VGA VERTICAL REFRESH RATE IN ALL MODES
FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480)
Figure 9: Interlaced NTSC Video Timing
START
OF
VSYNC
ANALOG
FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
8
ANALOG
FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
ANALOG
FIELD 3
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
ANALOG
FIELD 4
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
Figure 10: Interlaced PAL Video Timing
201-0000-029 Rev 6.1, 8/2/99
13
CHRONTEL
CH7002D
White
Yellow
27.48
25.41
1.030
0.953
Cyan
Green
22.08
20.01
0.828
0.750
Magenta
Red
16.99
14.93
0.637
0.560
Blue
Black
Blank
11.59
9.69
8.26
0.435
0.363
0.310
Sync
0.64
0024
Color bars:
Black
Blue
Red
Magenta
V
Green
Cyan
Yellow
mA
White
Color/Level
Figure 11: NTSC Y (Luminance) Output Waveform
26.05
23.98
0.977
0.899
Cyan
Green
20.65
18.58
0.774
0.697
Magenta
Red
15.56
13.50
0.584
0.506
Blue
10.16
0.381
Blank
8.26
0.310
Sync
0.64
0.024
Black
White
Yellow
Color bars:
Blue
Red
Magenta
V
Green
Cyan
Yellow
mA
White
Color/Level
Figure 12: PAL Y (Luminance) Video Output Waveform
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CHRONTEL
CH7002D
0.893
Peak Burst
19.69
0.739
Blank
15.88
0.596
Peak Burst
12.07
0.337
Black
23.82
Blue
Yellow/Blue
Red
1.012
0.989
Magenta
27.00
26.36
Green
Cyan/Red
Green/Magenta
Cyan
V
Yellow
mA
White
Color bars:
Color/Level
3.579545 MHz Color Burst
(9 cycles)
Yellow/Blue
7.94
0.298
Green/Magenta
Cyan/Red
5.40
4.76
0.202
0.179
Figure 13: NTSC C (Chrominance) Video Output Waveform
0.893
Peak Burst
19.69
0.739
Blank
15.88
0.596
Peak Burst
12.07
0.337
Black
23.82
Blue
Yellow/Blue
Red
1.012
0.989
Magenta
27.00
26.36
Green
Cyan/Red
Green/Magenta
Cyan
V
Yellow
mA
White
Color bars:
Color/Level
4.433619 MHz Color Burst
(10 cycles)
Yellow/Blue
7.94
0.298
Green/Magenta
Cyan/Red
5.40
4.76
0.202
0.179
Figure 14: PAL C (Chrominance) Video Output Waveform
201-0000-029 Rev 6.1, 8/2/99
15
CHRONTEL
CH7002D
1.030
Peak Burst
12.07
0.453
Black
9.69
0.363
Blank
8.26
0.310
Peak Burst
4.45
Black
27.48
Blue
White
Color bars:
Red
1.251
Magenta
33.35
Green
Peak Chrome
Cyan
V
Yellow
mA
White
Color/Level
0.167
3.579545 MHz Color Burst
(9 cycles)
Sync
0.64
0.024
Figure 15: Composite NTSC Video Output Waveform
12.07
0.453
Blank/Black
8.26
0.310
Peak Burst
4.45
0.167
Sync
0.64
0.024
Black
Peak Burst
Blue
0.977
Red
26.05
Magenta
White
Color bars:
Green
1.197
Cyan
V
Peak Chrome 31.92
White
mA
Yellow
Color/Level
4.433619 MHz Color Burst
(10 cycles)
Figure 16: Composite PAL Video Output Waveform
16
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
I2C Port Operation
The CH7002 contains a standard I2C control port, through which the control registers can be written and read. This
port is comprised of a two-wire serial interface, pins SD (bi-directional) and SC, which can be connected directly to
the SDB and SCB buses as shown in Figure 17.
The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure
17). The CH7002 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master
device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an
open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400
kbit/s.
+VDD
RP
SDB (Serial Data Bus)
SCB (Serial Clock Bus)
SD
SC
DATAN2
OUT
MASTER
SCLK
OUT
FROM
MASTER
DATA IN
MASTER
BUS MASTER
DATAN2
OUT
SCLK
IN1
DATA
IN1
DATAN2
OUT
SCLK
IN2
SLAVE
DATA
IN2
SLAVE
Figure 17: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected
to them are shown in Figure 17. A pull-up resistor (RP) must be connected to a 5V +/- 10% supply. The CH7002 is
a device with input levels related to VDD.
Maximum and minimum values of pull-up resistor (R P)
The value of RP depends on the following parameters:
• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = Iinput)
The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 3mA at
VOLmax = 0.4 V for the output stages.
• RP >= (VDD – 0.4) / 3 (RP in kΩ)
The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum
value of RP due to the specified rise time. The equation for RP is shown below:
• RP <= 103/C (where RP is in kΩ and C, the total capacitance, is in pF)
The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 µA.
Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of R P.
The RP limit depends on VDD and is shown below:
• RP <= (100 x VDD)/ Iinput (where RP is in kΩ and Iinput is in µA)
201-0000-029 Rev 6.1, 8/2/99
17
CHRONTEL
CH7002D
Transfer Protocol
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data, data, data). A basic serial port
transfer protocol is shown in Figure 18 below.
SD
I2C
1-7
8
Device ID
R/W*
SC
Start
Condition
9
1-8
ACK
Data1
CH7002
acknowledge
9
1-8
ACK
Data n
CH7002
acknowledge
9
ACK
CH7002
acknowledge
Stop
Condition
Figure 18: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high, this is the
“START” condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high, this is the
“STOP” condition.
3. Upon receiving the first START condition, the CH7002 expects a Register Address Byte (RAB) from the
master device. The format of the RAB byte is shown below (note that B[2:0] is determined by the state of
the ADDR pin).
Device Address Byte (DAB)
R/W
18
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
1
ADDR*
ADDR
R/W
Read/Write Indicator
“0”:
master device will write to the CH7002 at the register location specified by the address
AR[3:0]
“1”:
master device will read from the CH7002 at the register location specified by the
address AR[3:0.]. After the DAB is received, the CH7002 expects a Register Address
Byte (RAB) from the master. The format of the RAB is shown below (note that B4, B5,
and B7 are not used).
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
Register Address Byte (RAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
AutoInc
X
X
AR[3]
AR[2]
AR[1]
AR[0]
AutoInc
Register Address Auto-Increment - to facilitate sequential r/w of registers.
“1”:
Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be
incremented by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will automatically be incremented by one. The
Address Register will not be changed for the first read after an RAB.
“0”:
Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a
new RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will remain unchanged.
AR[3:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7002. The R/W* access,
which follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W* = 0,1
and AutoInc = 0,1.
CH7002 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7002 always acknowledges for writes (see Figure 19). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
Data Output
By Master-Transmitter
not acknowledge
Data Output
By the CH7002
SC from
Master
acknowledge
1
2
Start
Condition
8
9
clock pulse for
acknowledgement
Figure 19: Acknowledge on the Bus
Figure 20 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,
following the Register Address Byte (RAB), is the data to be written into the register specified by AR[3:0]. If
AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
201-0000-029 Rev 6.1, 8/2/99
19
CHRONTEL
CH7002D
CH7002
acknowledge
SD
CH7002
acknowledge
CH7002
acknowledge
CH7002
acknowledge
CH7002
acknowledge
I2C
SC
Start
Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Device
R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Stop
Condition
Figure 20: Alternate Write Mode
Note: * The acknowledge is from the CH7002 (slave).
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in Figure 21.
CH7002
acknowledge
SD
CH7002
acknowledge
CH7002
acknowledge
CH7002
acknowledge
I2C
SC
Start
Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
RAB n
ACK
Data n
ACK
Data n+1
ACK
Stop
Condition
Figure 21: Auto-Increment Write Mode
Note: * The acknowledge is from the CH7002 (slave).
When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment
for each write cycle until AR[3:0] = 0Bh. (0Bh is the address of the Address Register.) The next byte of information
represents a new auto-sequencing “Starting address,” which is the address of the register to receive the next byte.
The auto-sequencing then resumes based on this new “Starting address.” The auto-increment sequence can be
terminated anytime by either a “STOP” or “RESTART” condition. The write operation can be terminated with a
“STOP” condition.
CH7002 Read Cycle Protocols (R/W* = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7002 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 1. The second byte is the RAB
with AR[3:0], containing the address of the register that the master device intends to read, from in AR[3:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START,” without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=0, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 1
and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. Afterwards, the master may read another data byte, and so on. In summary, a RESTART condition,
20
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in Figure 22.
CH7002
acknowledge
CH7002
acknowledge
CH7002
acknowedge
Master
does not
acknowledge
SD
I2C
1-7
8
9
1-8
9
Device
R/W*
ACK
RAB 1
ACK
SC
Start
Condition
I2C
10
Restart
Condition
1-7
8
9
1-8
9
Device
R/W*
ACK
Data 1
ACK
10
Restart
Condition
Master does
not acknowledge
CH7002
CH7002
acknowledge
CH7002
acknowledge
acknowledge
I2 C
8
9
1-8
9
10
R/W*
ACK
RAB 2
ACK
Restart
Condition
1-7
Device
ID
I2C
1-7
Device
ID
8
9
1-8
9
R/W*
ACK
Data 2
ACK
Stop
Condition
Figure 22: Alternate Read Mode
If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read
from successive registers, without providing a second RAB.
CH7002
acknowledge
CH7002
CH7002
acknowledge
Master
acknowledge
Master does
not acknowledge
just before Stop
condition
SD
I2C
SC
Start
Condition
I2 C
1-7
8
9
1-8
9
Device
R/W*
ACK
RAB n
ACK
10
1-7
Restart
Device
Condition
8
9
1-8
9
1-8
9
R/W*
ACK
Data n
ACK
Data
n+1
ACK
Stop
Condition
Figure 23: Auto-increment Read Mode
When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for
each read cycle. When the content of the Address Register reaches 0Bh, it will wrap around and start from 00h
again. The auto increment sequence can be terminated by either a “STOP” or “RESTART” condition. The read
operation can be terminated with a “STOP” condition. Figure 23 shows an auto-increment read cycle terminated by
a STOP or RESTART condition.
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21
CHRONTEL
CH7002D
Registers and Programming
The CH7002 is a fully programmable device, providing for full functional control through the I2C port, or partial
functional control, through direct hardware pins. The CH7002 contains a total of 12 registers, which are listed in
Table 5.
Table 5. Register Map
Register
Symbol
Address
Bits
Functional Summary
Display Mode
DMR
00H
3
Display mode selection
Flicker Filter
FFR
01H
2
Flicker filter mode
selection
Y Filter
YFR
02H
3
Y (luma) filter bandwidth
selection
Sampling Delay
SDR
03H
4
Sampling clock delay
timing adjustment
Black Level
BLR
04H
7
Black level adjustment
Position Control
PCR
05H
4
Enables movement of
displayed image on TV
Reserved
06H
Reserved for future use
Version ID
VIR
07H
3
Device version number
Miscellaneous
Control
MCR
08H
8
Power management and
other controls
Connection
Detect
CDR
09H
4
Detection of TV
presence
Test
TR
0AH
8
Reserved
Address
AR
0BH
4
Current register being
addressed
Symbol: DMR
Display Mode Register
Address: 00H
Bits: 3
Bit:
7
6
5
4
3
2
1
0
Symbol:
DM2
DM1
DM0
Type:
R/W
R/W
R/W
Default:
0
1
0
This register provides programmable control of the CH7002 display mode, including input resolution, output TV
format, and overscan/underscan scaling. The three-bit field, DM[2:0], selects the display mode to be used according
to the following table of modes. Note that this programming of DM[2:0] is mutually exclusive to the pinprogramming method (only one mode of programming may be used at any one time, based on the state of the
PMODE pin).
22
DM2
DM1
DM0
Input Res
Output
Over/Under Scan
0
0
0
800x600
PAL
Underscan
0
0
1
640x480
PAL
Underscan
0
1
0
640x480
NTSC
Overscan
0
1
1
640x480
NTSC
Underscan
1
0
0
640x480
PAL
Overscan
1
0
1
800X600
PAL
Overscan
1
1
0
800x600
NTSC
Underscan
1
1
1
Reserved
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
Register Descriptions (continued)
Flicker Filter Register
Bit:
7
Symbol: FFR
Address: 01H
Bits: 2
6
5
4
3
2
1
0
Symbol:
FF1
FF0
Type:
R/W
R/W
Default:
0
1
The flicker filter register provides for flicker filter mode selection, only when operating in Overscan modes (display
modes 2 or 4). The low order bits of this register, FFR1 and FFR0, are logically “muxed” with the external pins
MS1 and MS0 respectively. Flicker filter bits, FFR[1:0], form a two-bit value which corresponds to the flicker
filter mode selection as follows:
FFR[1:0]
Mode
Comments
00
0:1:0
Flicker filtering is disabled
01
1:2:1
Moderate flicker filtering Default Mode
10
1:3:1
Low flicker filtering
11
1:1:1
High flicker filtering
Y (Luma) Filter Register
Bit:
7
6
Symbol: YFR
Address: 02H
Bits: 3
2
1
0
Symbol:
5
4
3
YPEAKD
YC-HI
YC-HI
Type:
R/W
R/W
R/W
Default:
0
0
0
This register enables the selection of alternative Luma filters for use with either composite or S-video outputs as
well as the disabling of the Y-peaking circuit. In the default condition, the CH7002 is setup to use lower bandwidth
filters with peaking enabled. Programming a “1” into each of these bit positions has the following effect:
Bit Position
Functional Description
CVBS-HI
Selects the high bandwidth filter for composite video outputs
YC-HI
Selects the high bandwidth filter for S-Video outputs and disables
the Y-peaking circuit
YPEAKD
Disables the Y-peaking circuit
Sampling Delay Register
Bit:
7
6
Symbol: SDR
Address: 03H
Bits: 4
3
2
1
0
Symbol:
5
4
SD3
SD2
SD1
SD0
Type:
R/W
R/W
R/W
R/W
Default:
0
0
0
0
This register sets the delay timing, between the on-chip sampling clock and the sync signals, for the analog RGB
inputs. The four least significant bits of this register provide a programmable delay value, in 15 programmable
steps, with each step being 2.5 ns (nominal). As shown, the default value is 0 delay. Selecting a value of 4 creates a
delay of 10 ns and a value of 8 places; the sampling delay is at the opposite phase of sampling the input signals.
201-0000-029 Rev 6.1, 8/2/99
23
CHRONTEL
CH7002D
Register Descriptions (continued)
Black Level Register
Bit:
7
Symbol: BLR
Address: 04H
Bits: 7
6
5
4
3
2
1
0
Symbol:
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
1
1
1
0
1
This register sets the black level, which is used as a relative baseline to reference the range of luminance values to
be output. The first seven bits of this register, BL[6:0], provide a programmable black level value, which must be set
between 51 and 80 (S-Video has limitation above 80), with the default of 61.
Position Control Register
Bit:
7
6
Symbol: PCR
Address: 05H
Bits: 4
5
4
3
2
1
0
Symbol:
LEFT
RIGHT
UP
DOWN
Type:
W
W
W
W
Default:
1
1
1
1
This register is used to shift the displayed TV image, in any orthogonal direction (left or right and up or down), to
achieve a centered image on screen. Each of the first four bits of this register, DOWN, UP, LEFT, AND RIGHT,
correspond to one of the basic directions of movement. As any of these bits are toggled (from 1 to 0 and back to 1),
the displayed image shifts four pixels in that direction from its current location (e.g. toggling UP will move the TV
image up by 4 input pixels). These four directional bits are bit-wise “ANDed,” with the signals from the four
corresponding input pins, so that position control can be effected at any time by using programming or toggle
switches. Note that the image positioning will be reset (to initial condition) by toggling into certain display modes.
When operating in modes 1 to 6, entering into mode 0 and returning will reset positioning. When operating in mode
0, entering into mode 1 and returning will also reset positioning. Resetting the position can be used to enable
absolute position programming by starting from a known reference.
Version ID Register
Bit:
7
Symbol: VIR
Address: 07H
Bits: 3
6
5
4
3
2
1
0
Symbol:
VIR3
VIR1
VIR0
Type:
R
R
R
Default:
0
0
0
This read-only register contains a 3-bit value, indicating the identification number, assigned to this version of the
CH7002. The default value shown is pre-programmed into this chip and is useful for checking the correct version
of this chip before proceeding with its programming.
24
201-0000-029 Rev6.1, 8/2/99
CHRONTEL
CH7002D
Register Descriptions (continued)
Miscellaneous Control Register
Symbol: MCR
Address: 08H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
CEE
BUD
ECE
ECD2
SP0
Reserved
PD1
PD0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
1
1
This register provides control of a number of different and unrelated functions, segmented into the following:
Power Down - The CH7002 provides programmable control of its operating states, including normal and three
reduced power modes. Bits 0 and 1 of MCR setup these modes as follows:
PD[1:0]
Operating State
Functional Description
11
Normal (On):
All circuits and pins are active
10
S-Video Off:
Power is shut off to the unused DACs associated with Y and
C outputs
01
Power Down:
Most pins and circuitry are disabled (except for the bandgap
reference)
00
Composite Off:
Power is shut off to the unused DAC associated with CVBS
output
Scratchpad Bits - One bit has been set aside as a scratchpad bit, with no on-chip control functions as a convenience
for programming.
Control Bits - Several control bits are provided to enable/disable specific video control functions:
Symbol
Functional Description
ECE
External Clock Enable. Setting this bit enables the external clock
input on the XCLK pin
BUD
Burst Update Clock Disable. Setting this bit disables the burst
frequency counter updates
CEE
Contrast Enhancement Enable. Setting this bit enables a contrast
enhancement circuit
ECD2
External clock divide by two enable. Setting this bit enables
dividing the incoming pixel clock by two.
Connection Detect Register
Bit:
7
6
Symbol: CDR
Address: 09H
Bits: 4
3
2
1
0
Symbol:
Y
C
CVBS
SENSE
Type:
R
R
R
W
Default:
0
0
0
0
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5
4
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CHRONTEL
CH7002D
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or composite
video outputs. The status bits, Y, C, and CVBS, correspond to both the DAC outputs for S-Video (Y and C outputs)
and composite video (CVBS). However, the values contained in these status bits ARE NOT VALID until a sensing
procedure is performed. Using this register requires a sequence of events to enable the sensing of outputs, then
reading out the applicable status bits. The detection sequence works as follows:
1. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that
during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.
2. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs
and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold
value, it is considered connected. If it is above this voltage, it is considered unconnected. During this step,
each of the three status bits corresponding to individual analog outputs will be set if they are NOT
CONNECTED.
3. Read the status bits. The status bits, Y, C, and CVBS (corresponding to S-Video Y and C outputs and
composite video) now contain valid information which can be read to determine which outputs are
connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.
Test Register
Symbol: TR
Address: 0AH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
T7
T6
T5
T4
T3
T2
T1
T0
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
0
0
0
The Test Register contains 8 bits which are reserved for implementing patterns and measurements for tests. Writing
a logical one into each bit, in this register, places the chip in a specific test mode. These test modes are not
documented for use herein, since they are used only for manufacturing test.
Address Register
Bit:
3
2
1
0
Symbol:
AR3
AR2
AR1
AR0
Type:
R/W
R/W
R/W
R/W
X
X
X
X
Default:
7
Symbol: AR
Address: 0BH
Bits: 4
0
6
0
5
0
4
0
The Address Register points to the register currently being accessed. Since the most significant four bits of all
addresses are zero, this register contains only the four least significant bits, AR[3:0].
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CHRONTEL
CH7002D
Application Information
Figure 24 on page 28 shows the basic power, input, control, and output connections of the CH7002 necessary to
generate TV output from VGA analog (RGB) input signals. This connection shows the most simplified
configuration, in which all control of the CH7002 modes and features are accomplished using the I 2C serial control
port.
Basically, the CH7002 receives analog RGB as well as TTL-compatible horizontal and vertical sync signals from
the VGA interface. In the configuration shown, the pixel clock is regenerated internally to the CH7002 using a
“genlock” PLL and the HSYNC input as a reference frequency. A 14.31818 oscillator provides a frequency
reference for color subcarrier generation.
Power Connections
The CH7002 has three separate sets of power connections to the external system. The AVDD connections supply
power to the video ADCs and genlock PLL. The DVDD connections power the digital circuits, including memory,
control, and signal processing functions. Finally, the VDD connection powers the S-Video and composite video
DAC’s and output circuits.
Normally, all power supply connections will be derived from a single board level supply bus. If the system includes
other potentially noisy digital components, it is best to use a separate linear voltage regulator to power the CH7002.
As with all video frequency analog devices, careful attention to power supply distribution is essential to achieve
optimum performance. A detailed discussion of recommended power supply distribution and decoupling methods is
provided in the section entitled PC Board Layout Guidelines.
Analog Input Connections
The CH7002 processes the video signals received on the RGB input pins. The first step in processing is to convert
the analog signals into corresponding digital values through the use of a triple, high-speed ADC. The analog input
pins accommodate signals ranging between 0 and 750 mV; this range is compatible with the standard output of a
VGA, properly terminated with a 37.5 ohms effective load.
The RC filter networks (see Figure 24 on page 28) serve to bandlimit the input signals to avoid aliasing artifacts.
Typical Use Configuration
The VGA input configured for applications that do not require RGB buffering before the monitor is shown in
Figure 24. In this configuration, 75 Ω input termination must be guaranteed by: termination by the monitor
connection, discrete 75 Ω resistors on the PCB, or a dummy 75 Ω termination connector. The total RGB trace on the
PCB must be kept as short as possible to avoid cable reflection problems.
Refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance
value for the tuning capacitor should be obtained from the crystal manufacturer.
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27
CHRONTEL
CH7002D
ISOLATION
and
DECOUPLING
+5V
AVDD
DVDD
VDD
R
RECONSTRUCTION
FILTER
(OPTIONAL)
Y
75
G
VGA
INTERFACE
B
RECONSTRUCTION
FILTER
(OPTIONAL)
C
75
CH7002
H
RECONSTRUCTION
FILTER
CVBS
75
V
UP
DOWN
LEFT
RIGHT
RESET*
PMODE
ADDR/FF0
XCLK/SD3
PD1
FF1
I2C
SD
INTERFACE
MASTER
DEVICE
SC
RSET
330
0.1
XI
Vref1
XI.FIN
Vref2
14.31818MHz
0.1
AGND
DGND
GND
Figure 24: CH7002 Typical Connection Diagram
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CHRONTEL
CH7002D
Analog Output Connections
The Y (luminance), C (chrominance), and CVBS (composite video, blanking and sync) outputs are direct current
source outputs from the video DACs. An external shunt terminating resistor (nominally 75 ohms) is placed at the
DAC outputs and serves to convert the current output to a voltage. Proper NTSC and PAL format output levels are
achieved when the total effective termination is 37.5 ohms. External “reconstruction” filter networks are usually
used to create a smooth and bandlimited output waveform. A reconstruction filter is recommended on the CVBS out
to minimize image artifacts. The filters on the Y and C outputs often are not required and may unnecessarily limit
signal bandwidth. Figure 25 shows a typical reconstruction filter structure and component values.
47pF
1.2uH
1.2uH
150pF
270pF
Figure 25: Typical Fourth-Order Reconstruction Filter
Control Interface
The operating modes of the CH7002 may be controlled either through dedicated digital input pins, or through the
I2C serial control interface. Selection of the control method is established by the PMODE pin; this pin should be
strapped to either DVDD or GND, when the device is powered up, and should not be changed during operation.
When PMODE=1, the I2C interface is enabled. Both of the SD/DM1 and SC/DM2 pins become the Serial Data and
Serial Clock signals for the two-wire I2C interface.
When PMODE= 0, the following pin functions are defined as:
• RESET*/DM0 becomes an input selecting CH7002 operating mode
•
•
SD/DM1 becomes an input selecting CH7002 operating mode
SC/DM2 becomes an input selecting CH7002 operating mode
•
ADDR/FF0 becomes an input selecting CH7002 deflicker mode
•
XCLK/SD3 becomes an input, selecting one of two analog input sample points
When pin control mode (PMODE=0) is selected, the function of the SC/DM2, SD/DM1, and RESET*/DM0 pins is
identical to that of bits DM2, DM1, DM0 in configuration register DMR (Display Mode Register). The encoding of
these inputs is restated in Table 6.
Table 6. Encoding Inputs Pin Control Mode
DM2
DM1
DM0
Input Resolution
0
0
0
800x600
PAL
Underscan
0
0
1
640X480
PAL
Underscan
0
1
0
640X480
NTSC
Overscan
0
1
1
640X480
NTSC
Underscan
1
0
0
640X480
PAL
Overscan
1
0
1
800X600
PAL
Overscan
1
1
0
800X600
NTSC
Underscan
1
1
1
Power Down
None
None
201-0000-029 Rev 6.1, 8/2/99
Output Format
Scaling
29
CHRONTEL
CH7002D
Position Control
The CH7002 defines four pins (UP, DOWN, LEFT, RIGHT) which provide a hardware-controlled positioning
mechanism to adjust the horizontal and vertical position of the output image on the television screen. These inputs
are rising edge-triggered, asynchronous, TTL-compatible inputs. They may be controlled from other logic devices
such as I/O ports or microcontrollers, or may be connected to SPST switches directly. The inputs include an on-chip
pull-up resistor so that only simple switch closures to ground are required. Care should be taken to avoid switch
bounce. Also, simultaneous assertion of more than one of the four inputs should be avoided.
Crystal Oscillator
The CH7002 includes an oscillator circuit which allows an inexpensive 14.31818 MHz crystal to be connected
directly. Alternatively, an externally generated 14.31818 MHz clock source may be supplied to the CH7002. If an
external source is used, it should have TTL level specifications. The clock should be connected to the XO/FIN pin
(pin 18), and the XI pin (pin 17) should be tied to ground. An external source should also exhibit +/- 50 ppm or
better frequent accuracy, and have low jitter characteristics.
If a crystal is used, the designer should ensure that the following conditions are met:
• Crystal is specified as 14.31818 MHz, +/- 50 ppm in parallel resonance
•
•
Crystal is operated with a load capacitance equal to its specified value
External load capacitors have their ground connection very close to the CH7002
•
To allow tunability, a variable cap may be used from XI to ground
Note that the XI and XO/FIN pin each have approximately 15-10 pF of shunt capacitance internal to the device. To
calculate the proper external load capacitance to be added to the XI and XO/FIN pins, the following calculation
should be used:
Cext = (2 * Cload) - Cint
where external load capacitance shall include routing capacitance on the PCB:
Cext = External load capacitance required on XI and XO/FIN nodes
Cload = Crystal load capacitance specified by crystal manufacturer
Cint = Capacitance internal to CH7002 (approximately 15-10 pF on each of XI and
XO/FIN pins)
PC Board Layout Guidelines
The CH7002 is a high performance, mixed-signal IC containing precision analog and digital circuits. This section
provides general guidelines for CH7002 PCB layout. Information on the ground plane, power planes, power supply
decoupling, and layout for critical analog/digital signals and circuitry are included. The following design guidelines
are intended to optimize the layout for minimum signal coupling. These are only recommendations. The user is
urged to implement the configurations and evaluate the performance of the entire system before bringing the design
to production.
Two-Layer vs. Four-Layer Designs
The CH7002 can be successfully used in either double-sided PCB applications, or PCB designs using four (or more)
layers of interconnect. Using at least four layers will usually simplify the design task, and may also lower radiated
emissions. In either case, the use of ground and power planes are necessary to achieve full performance. Ground and
power planes should fill all available PCB areas not used for routing signals.
In the case of 4-layer designs, the recommended layer utilization is as follows:
30
•
Layer 1 (top): Analog interconnections
•
•
Layer 2: Ground plane
Layer 3: Power supply planes
•
Layer 4: Digital interconnections
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CHRONTEL
CH7002D
If a 2-layer design is used, the layer utilization should be:
•
•
Layer 1: Analog interconnects, area-filled power supply planes
Layer 2: Digital interconnects, area-filled ground plane
Placement Considerations
The CH7002 device should be placed in close proximity with other analog components it connects to, or shares
power connections. Conversely, the device should be located as far as possible from noise-producing digital
components such as microprocessors, DRAM arrays, system clock generators, etc.
Power Distribution and Decoupling
As previously described, the CH7002 has three separate sets of power connections to the external system. Normally,
all power supply connections will be derived from a single board level supply bus. If the system includes other
potentially noisy digital components, it is best to use a separate linear voltage regulator to power the CH7002.
The three power buses should be isolated from each other through the use of ferrite beads. Surface mount beads,
having a nominal impedance of 55-60 ohms at 100MHz, are usually effective.
It is critically important that all power supply connections be effectively decoupled. Each power pin should be
decoupled to its “associated” ground pin (see Table 7), with a high-quality ceramic surface mount capacitor. These
capacitors should be placed as close as possible to the device pins; the preferred value is 0.1 uF. In the case of
especially noisy environments, greater decoupling effectiveness can be achieved by adding a 0.01 uF ceramic cap in
parallel with each 0.1 uF cap. The 0.01 uF cap provides greater bypassing of very high frequency noise. Each
CH7002 ground pin should be directly connected to its respective decoupling capacitor lead; then, both the pin and
the lead should be connected to the ground plane. If possible, a physical connecting trace between the CH7002
ground pin and the capacitor lead should be present on the connecting layer, rather than relying on the ground plane
alone for the connections. All ground traces should be short and wide, with multiple ground vias to minimize
parasitic inductance. A recommended power supply isolation and decoupling strategy is detailed in Figure 27 on
page 33.
Table 7. Power and Ground Pin Decoupling
Power Pin
Pin Number
Associated Ground Pin
DVDD1
8
10
DVDD2
14
16
DVDD3
33
31
VDD1
25
21
AVDD1
44
2
AVDD2
7
6
AVDD3
37
39
AVDD4
40
42
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CHRONTEL
CH7002D
Power Supply Sequencing
It is important to ensure that the three separate power supply rails of theCH7002 (VDD, AVDD, and DVDD) are
applied simultaneously during the power-up process. Failure to do so may, in rare instances, put the CH7002 into a
non-functional “latchup” condition, which can possibly destroy the device.When the power rails are derived from a
single 5 volt source as shown in Figure 27, sequencing is not an issue and the latchup problem will not occur. In
some designs, however, the analog (AVDD, VDD) and digital (DVDD) supplies may be derived from separate
sources such as the separate outputs of a multi-output switching power supply. In this case, significant delays may
be created between application of the analog and digital voltages, creating the potential latchup condition.
Whenever the possibility of power sequencing delays exist, the design should include back-to-back connected
diodes coupling the analog and digital supply rails, as shown in Figure 27.
Using this arrangement, the first supply to come up will “pull” the other supply rail along with it, eliminating the
latchup potential. Use of rectifier-type diodes with at least 400mA forward current ratings is suggested. It is
suggested that the diodes be connected on the power-supply side of any ferrite beads or other isolation networks
POWER SUPPLY
OUTPUT
#1
POWER SUPPLY
OUTPUT
#2
1N4001
25
8, 14, 33
37
7, 40, 44
CH7002B
Figure 26: Power Sequencing
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CHRONTEL
CH7002D
Regulated +5 Vd c
10uF
0.1
AVDD(37)
Ferrite Bead
0.1
.01
(opt)
AGND(39)
AVDD(44)
Ferrite Bead
0.1
0.1
.01
(opt)
AGND(2)
AVDD(7)
.01
(opt)
0.1
0.1
AGND(6)
.01
(opt)
AVDD(40)
AGND(42)
Ferrite Bead
0.1
0.1
.01
(opt)
DVDD(8)
DGND(10)
0.1
.01
(opt)
DVDD(14)
DGND(16)
C
H
7
0
0
2
DVDD(33)
0.1
.01
(opt)
DGND(31)
Ferrite Bead
0.1
.01
(opt)
VDD(25)
GND(21)
Figure 27: Power Supply Isolation Decoupling Configuration
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33
CHRONTEL
CH7002D
Optional Controls and Circuits
Full Scale Input Range Adjustment
The full-scale input range of the CH7002 may be modified from its nominal value of 750 mV. This is accomplished
by forcing a DC voltage into the VREF1 pin, thus overriding the internally-generated reference voltage. The simple
circuit shown below allows adjustment of the VREF1 voltage, over approximately a 1.0 to 2.5 volt range.
+5 V
AVDD
2.7K
Vref1
2K
CH7002
0.1uF
1.2K
AGND
Figure 28: Full-Scale Input Range Adjustment
Electrical Specifications
Table 8. Absolute Maximum Ratings
Symbol
Description
VDD relative to GND
Input voltage of all digital pins
TSC
Min
Max
Units
- 0.5
7.0
V
GND - 0.5
Vdd + 0.5
V
Analog output short circuit duration
Typ
Indefinite
Sec
TAMB
Ambient operating temperature
- 55
70
°C
TSTOR
Storage temperature
- 65
150
°C
TJ
Junction temperature
150
°C
Vapor phase soldering (one minute)
220
°C
Maximum power dissipation
1.9
W
TVPS
PMAX
Notes:
1 Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating conditions section of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2 The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive
device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce
destructive latchup.
3 The temperature assumes a still environment with no active cooling.
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CHRONTEL
CH7002D
Electrical Specifications (Continued)
Table 9. Recommended Operating Conditions
Symbol
Description
DAC power supply voltage
VDD
AVDD
Analog supply voltage
DVDD
Digital supply voltage
Min
Typ
Max
Units
4.75
5.00
5.25
V
70
°C
5.00
5.00
TA
Ambient operating temperature 3
RL
Output load to DAC outputs
0
25
1.14
1.235
37.5
VREF1
ADC voltage reference input/output
VREF2
Internal voltage reference
Ohms
1.26
V
2.5
V
Table 10. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V ± 5%)
Symbol
Description
Video D/A resolution
Min
Typ
Max
Unit
8
8
8
Bits
Full scale output current
33.89
mA
Video level error
using external reference
using internal reference
IREF1
5
10
VREF1 input current (VREF1 = 1.235V)
Total Current Consumption
%
%
10
µA
345
mA
Note: As applied to Tables 6, 7, and 8, Recommended Operating Conditions are used as test conditions unless otherwise specified.
External voltage reference used with RSET = 324Ω, VREF1 = 1.235V.
Table 11. Digital Inputs / Outputs
Symbol
Description
Test Condition @ TA = 25OC
Min
Typ
Max
Output high voltage
Ioh = - 400 mA
VOL
Output low voltage
Iol = 3.2 mA
0.4
V
VIH
Input high voltage
2.0
Vdd +
0.5
V
GND - 0.5
0.8
V
5
25
mA
10
mA
VIL
Input low voltage
IPU
Input internal pull-up current
ILK
Input leakage current
CDIN
Input capacitance
CDOUT
2.4
Unit
VOH
V
-10
f = 1 MHz, Vin = 2.4V
Output capacitance
7
pF
10
pF
Table 12. Timing
Symbol
Description
t1
Sync to external clock
setup time
2
nS
t2
Sync to external clock
hold time
2
nS
201-0000-029 Rev 6.1, 8/2/99
Min
Typ
Max
Unit
35
CHRONTEL
ORDERING INFORMATION
Part number
Package type
Number of pins
Voltage supply
CH7002D-V
PLCC
44
5V
Chrontel
2210 O’Toole Avenue
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: [email protected]
1997 Chrontel, Inc. All Rights Reserved.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE
SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably
expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not
responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no
liability for errors contained in this document. Printed in the U.S.A.
36
201-0000-029 Rev. 6.1, 8/2/99