SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD SN54LV161A . . . FK PACKAGE (TOP VIEW) A B NC C D 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 ENP GND NC description/ordering information 4 The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. QA QB NC QC QD LOAD ENT D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) CLK CLR NC VCC RCO D SN54LV161A . . . J OR W PACKAGE SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection ORDERING INFORMATION TOP-SIDE MARKING Tube of 40 SN74LV161AD Reel of 2500 SN74LV161ADR SOP − NS Reel of 2000 SN74LV161ANSR 74LV161A SSOP − DB Reel of 2000 SN74LV161ADBR LV161A Tube of 90 SN74LV161APW Reel of 2000 SN74LV161APWR Reel of 250 SN74LV161APWT TVSOP − DGV Reel of 2000 SN74LV161ADGVR LV161A CDIP − J Tube of 25 SNJ54LV161AJ SNJ54LV161AJ CFP − W Tube of 150 SNJ54LV161AW SNJ54LV161AW SOIC − D −40°C to 85°C TSSOP − PW −55°C 125°C −55 C to 125 C ORDERABLE PART NUMBER PACKAGE† TA LV161A LV161A LCCC − FK Tube of 55 SNJ54LV161AFK SNJ54LV161AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"#$ $%$ & $'("%$ !((#$ % ' )!*+%$ %#, &(! $'(" )#'%$ )#( # #(" ' #-% $(!"#$ %$%( .%((%$/, &(!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++ )%(%"##(, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 description/ordering information (continued) These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS 2 CLR LOAD ENP OUTPUTS ENT CLK QA QB QC QD FUNCTION L X X X X L L L L Reset to “0” H L X X ↑ A B C D Preset Data H H X L ↑ No Change No Count H H L X ↑ No Change No Count H H H H ↑ Count up Count H X X X ↑ No Change No Count POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the overall logic diagram of the device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CK† TG CK† SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 recommended operating conditions (see Note 4) SN54LV161A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 Output voltage 0 0 VCC −50 V VCC × 0.3 5.5 0 VCC −50 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V V V µA −2 −6 −6 −12 −12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT 0.5 VCC × 0.3 VCC × 0.3 0 Input transition rise or fall rate MAX 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current SN74LV161A 0 200 0 200 0 100 0 100 0 20 0 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV161A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 MIN TYP SN74LV161A MAX MIN VCC−0.1 2 VCC−0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOH = −6 mA IOH = −12 mA II ICC VCC TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.8 1.8 pF & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time before CLK↑ SN54LV161A MIN MAX SN74LV161A MIN CLK high or low 7 7 7 CLR low 7 7 7 CLR 4.5 4.5 4.5 Data (A, B, C, and D) 7.5 8.5 8.5 ENP, ENT 9.5 11 11 LOAD low 10 11.5 11.5 1.5 1.5 1.5 Hold time, all synchronous inputs after CLK↑ MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time before CLK↑ SN54LV161A MIN MAX SN74LV161A MIN CLK high or low 5 5 5 CLR low 5 5 5 CLR 2.5 2.5 2.5 Data (A, B, C, and D) 5.5 6.5 6.5 ENP, ENT 7.5 9 9 LOAD low 8 9.5 9.5 1 1 1 Hold time, all synchronous inputs after CLK↑ MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before CLK↑ th Hold time, all synchronous inputs after CLK↑ MIN MAX SN74LV161A MIN CLK high or low 5 5 5 CLR low 5 5 5 CLR 1.5 1.5 1.5 Data (A, B, C, and D) 4.5 4.5 4.5 ENP, ENT 5 6 6 LOAD low 5 6 6 1 1 1 & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 %$0# ( $$!# ## )(! .! $#, 8 SN54LV161A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd tPHL CLR CLK tpd tPHL SN74LV161A CL = 15 pF 50* 125* 40* 40 CL = 50 pF 30 95 25 25 MIN MAX MIN MAX 16.2* 1* 19.5* 1 19.5 RCO (count mode) 8.9* 17* 1* 20.5* 1 20.5 11.9* 20.6* 1* 24.5* 1 24.5 RCO 8.3* 15.7* 1* 19* 1 19 Q 8.8* 17* 1* 20.5* 1 20.5 RCO 9.8* 16.6* 1* 20* 1 20 Q 10.5 19.2 1 22.5 1 22.5 RCO (count mode) 11.7 20 1 23.5 1 23.5 14.5 23.6 1 27.5 1 27.5 11 18.7 1 22 1 22 CL = 15 pF CL = 50 pF RCO Q 11.4 20 1 23.5 1 23.5 RCO 12.6 19.6 1 23 1 23 CLR UNIT MHz 7.9* RCO (preset mode) ENT SN54LV161A MIN Q RCO (preset mode) ENT TA = 25°C TYP MAX LOAD CAPACITANCE ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX tpd* CL = 15 pF* 80* 165* 70* 70 CL = 50 pF 55 125 50 50 tPHL* CLR CLK tpd tPHL MIN MAX 15* 1 15 6.7 13.6 1* 16* 1 16 8.6 17.2 1* 20* 1 20 RCO 6.2 12.3 1* 14.5* 1 14.5 Q 6.5 13.6 1* 16* 1 16 RCO 7.2 13.2 1* 15.5* 1 15.5 Q 7.8 16.3 1 18.5 1 18.5 RCO (count mode) 8.7 17.1 1 19.5 1 19.5 10.6 20.7 1 23.5 1 23.5 RCO 8.3 15.8 1 18 1 18 Q 8.4 17.1 1 19.5 1 19.5 RCO 9.2 16.7 1 19 1 19 RCO (count mode) CL = 15 pF CL = 50 pF CLR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz 1* * On products compliant to MIL-PRF-38535, this parameter is not production tested. 10 MAX 12.8 RCO (preset mode) ENT MIN 6 RCO (preset mode) ENT SN74LV161A MIN Q CLK SN54LV161A LOAD CAPACITANCE ns ns SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd 220 115* 115 95 165 85 85 MIN MAX 9.5* 1 9.5 RCO (count mode) 5.1* 8.1* 1* 9.5* 1 9.5 6.3* 10.3* 1* 12* 1 12 RCO 4.8* 8.1* 1* 9.5* 1 9.5 Q 4.9* 9* 1* 10.5* 1 10.5 RCO 5.5* 8.6* 1* 10* 1 10 Q 5.9 10.1 1 11.5 1 11.5 RCO (count mode) 6.6 10.1 1 11.5 1 11.5 7.8 12.3 1 14 1 14 RCO 6.1 10.1 1 11.5 1 11.5 Q 6.3 11 1 12.5 1 12.5 RCO 6.9 10.6 1 12 1 12 ENT CL = 15 pF CL = 50 pF CLR UNIT MHz 1* RCO (preset mode) tPHL 135* CL = 50 pF MAX 8.1* CLR CLK SN74LV161A CL = 15 pF MIN 4.5* ENT tpd SN54LV161A MIN Q RCO (preset mode) tPHL TA = 25°C TYP MAX LOAD CAPACITANCE ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV161A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 0.8 V Quiet output, minimum dynamic VOL −0.2 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 25.8 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz 23.6 pF & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0 %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 50% VCC 0V tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC VCC Output Control tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV161AD ACTIVE SOIC D 16 SN74LV161ADBR ACTIVE SSOP DB SN74LV161ADBRE4 ACTIVE SSOP SN74LV161ADE4 ACTIVE SN74LV161ADG4 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV161APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV161ADBR DB 16 MLA 330 16 8.2 6.6 2.5 12 16 Q1 SN74LV161ADGVR DGV 16 MLA 330 12 6.8 4.0 1.6 8 16 Q1 SN74LV161ADR D 16 FMX 0 16 6.5 10.3 12.1 2 16 Q1 SN74LV161ANSR NS 16 MLA 330 16 8.2 10.5 2.5 12 16 Q1 SN74LV161APWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LV161ADBR DB 16 MLA 342.9 336.6 28.58 SN74LV161ADGVR DGV 16 MLA 338.1 340.5 20.64 SN74LV161ADR D 16 FMX 342.9 336.6 28.58 SN74LV161ANSR NS 16 MLA 342.9 336.6 28.58 SN74LV161APWR PW 16 MLA 338.1 340.5 20.64 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. 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Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power Wireless www.ti.com/lpw Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated