SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 D D D D D D D D D D D D D UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C High-Drive (–24/24 mA at 2.5-V and –32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package SN54ALVTH16601 . . . WD PACKAGE SN74ALVTH16601 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR and the DGVR package is abbreviated to VR. description The ’ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UBT and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 description (continued) Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16601 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALVTH16601 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS CLKENAB OEAB LEAB CLKAB A OUTPUT B X H X X X Z X L H X L L X L H X H H L L X X H B0‡ H L L X X B0‡ L L L ↑ L L L L ↑ H H L B0‡ † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established L 2 L L POST OFFICE BOX 655303 L or H X • DALLAS, TEXAS 75265 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 logic diagram (positive logic) OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 CE 3 1D C1 CLK 54 B1 CE 1D C1 CLK To 17 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . –0.5 V to 7 V Output current in the low state, IO: SN54ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA SN74ALVTH16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3) SN54ALVTH16601 SN74ALVTH16601 MIN MAX MIN 2.7 2.3 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current IOL TYP TYP 2.7 1.7 0 VCC 5.5 0.7 0 –6 Low-level output current Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled VCC V mA 8 24 10 mA ns/V µs/V 200 –40 V –8 6 125 V 5.5 18 10 UNIT V 0.7 Input voltage MAX 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3) SN54ALVTH16601 SN74ALVTH16601 MIN MAX MIN 3.6 3 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current IOL ∆t/∆v TYP TYP 3.6 2 0 5.5 0.8 0 V VCC V 5.5 V –24 –32 mA Low-level output current 24 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64 Input transition rise or fall rate 10 10 Outputs enabled VCC UNIT V 0.8 Input voltage MAX mA ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V VRST‡ VCC = 2.7 V IEXk IOZ(PU/PD)h Cio VCC = 2.7 V, VCC = 2.3 V, 0.2 0.4 IOL = 8 mA IOL = 18 mA 0.4 V 0.5 IOL = 24 mA IO = 1 mA, VI = VCC or GND 0.5 0.55 0.55 ±1 ±1 10 10 VI = 5.5 V VI = VCC 10 10 1 1 VI = 0 VI or VO = 0 to 4.5 V –5 –5 VCC = 2.7 V IBHLO# IBHHO|| Ci 1.8 A or B ports VCC = 2.3 V, VCC = 2.7 V, V V 0.2 VI = VCC or GND VI = 5.5 V VCC = 0, VCC = 2.3 V, –1.2 UNIT VCC–0.2 IOL = 100 µA IOL = 6 mA VCC = 2.7 V, VCC = 0 or 2.7 V, Ioff IBHL§ IBHH¶ SN74ALVTH16601 MIN TYP† MAX –1.2 VCC–0.2 1.8 Control inputs II ICC SN54ALVTH16601 MIN TYP† MAX TEST CONDITIONS ±100 VI = 0.7 V VI = 1.7 V VI = 0 to VCC VI = 0 to VCC V µA µA 115 115 µA –10 –10 µA 300 300 µA –300 –300 µA VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care 125 125 µA ±100 ±100 µA VCC = 2.7 V, IO = 0, VI = VCC or GND Outputs high 0.04 0.1 0.04 0.1 Outputs low 2.5 4.5 2.5 4.5 0.04 0.1 0.04 0.1 VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 Outputs disabled 3 3 7 7 mA pF pF † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ Data must not be loaded into the flip-flops/latches after applying power. § The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k Current into an output in the high state when VO > VCC h High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V VRST‡ Control inputs Ioff IBHL§ IBHH¶ IBHLO# IBHHO|| IEXk IOZ(PU/PD)h ICC 2 IOL = 100 µA IOL = 16 mA 0.2 IOL = 24 mA IOL = 32 mA 0.5 IOL = 48 mA IOL = 64 mA 0.55 0.5 VCC = 3.6 V VI = 0 VI or VO = 0 to 4.5 V –5 VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC 0.55 0.55 ±1 ±1 10 10 10 10 1 1 µA –75 –75 µA 500 500 µA Outputs low Outputs disabled VI = 3.3 V or 0 VO = 3.3 V or 0 µA –500 0.06 VCC = 3.3 V, VCC = 3.3 V, µA 75 Outputs high Ci µA 75 –500 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND V –5 ±100 VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care ∆ICC◊ Cio V 0.55 VI = 5.5 V VI = VCC VCC = 3.6 V, IO = 0, VI = VCC or GND 0.2 0.4 VI = VCC or GND VI = 5.5 V VCC = 3.6 V, VCC = 3 V, V V VCC = 3.6 V, VCC = 0 or 3.6 V, VCC = 3 V, VCC = 3.6 V, –1.2 UNIT VCC–0.2 VCC = 3.6 V VCC = 0, VCC = 3 V, SN74ALVTH16601 MIN TYP† MAX –1.2 VCC–0.2 2 IO = 1 mA, VI = VCC or GND II A or B ports SN54ALVTH16601 MIN TYP† MAX TEST CONDITIONS 125 125 µA ±100 ±100 µA 0.1 0.06 0.1 3.5 5 3.5 5 0.06 0.1 0.06 0.1 0.4 0.4 3 3 7 7 mA mA pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Data must not be loaded into the flip-flops/latches after applying power. § The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k Current into an output in the high state when VO > VCC h High-impedance state during power up or power down ◊ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH16601 MIN fclock tw Clock frequency Pulse duration 150 CLK high or low 2.3 2.3 A or B before LE↓ A or B after CLK↑ Hold time A or B after LE↓ CLKEN after CLK↑ MAX 150 1.8 CLKEN before CLK↑ th MIN 1.8 Data high Setup time SN74ALVTH16601 LE high A or B before CLK↑ tsu MAX 4 4 Data low 5.2 5.2 CLK high 0.7 0.7 CLK low 0.9 0.9 Data high 1.7 1.7 Data low 2.3 2.3 Data high 0.5 0.5 Data low 0.5 0.5 CLK high 2.3 2.3 CLK low 2.4 2.4 Data high 0.5 0.5 Data low 0.5 0.5 UNIT MHz ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) SN54ALVTH16601 MIN fclock tw Clock frequency Pulse duration Setup time 150 CLK high or low 2.3 2.3 Data high 2.4 2.4 Data low 3.8 3.8 1 1 CLK low 0.6 0.6 Data high 1.4 1.4 Data low 1.9 1.9 Data high 0.5 0.5 Data low 0.5 0.5 CLK high A or B before LE↓ CLK high A or B after LE↓ CLKEN after CLK↑ 2 2 CLK low 2.3 2.3 Data high 0.6 0.6 Data low 0.5 0.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 150 1.8 A or B after CLK↑ Hold time MIN 1.8 CLKEN before CLK↑ th SN74ALVTH16601 LE high A or B before CLK↑ tsu MAX UNIT MHz ns ns ns SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALVTH16601 MIN MAX 150 B or A A or B LEBA or LEAB A or B CLKBA or CLKAB A or B OEBA or OEAB A or B OEBA or OEAB A or B SN74ALVTH16601 MIN MAX 150 UNIT MHz 1.1 4.1 1.1 4.1 1.6 4.8 1.6 4.8 2.1 5 2.1 5 2.4 5.4 2.4 5.4 2 5 2 5 2.5 5.9 2.5 5.9 1.2 4.8 1.2 4.8 1 4.6 1 4.6 1.2 5.2 1.2 5.2 1 3.9 1 3.9 ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALVTH16601 MIN MAX 150 B or A A or B LEBA or LEAB A or B CLKBA or CLKAB A or B OEBA or OEAB A or B OEBA or OEAB A or B SN74ALVTH16601 MIN MAX 150 UNIT MHz 1.4 3.9 1.4 3.9 1.1 3.9 1.1 3.9 2 4.6 2 4.6 2.1 4.6 2.1 4.6 1.9 4.5 1.9 4.5 2.2 4.6 2.2 4.6 1 4.2 1 4.2 1 4.4 1 4.4 1.8 5.3 1.8 5.3 1.7 4.6 1.7 4.6 ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH16601, SN74ALVTH16601 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES143A – SEPTEMBER 1998 – REVISED JULY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V 0V Output Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPHL VOH 1.5 V tPLZ tPZL 1.5 V tPLH 1.5 V 0V 3V 1.5 V 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V 0V tsu Data Input 1.5 V Input 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated