SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C High Drive (–24/24 mA at 2.5-V VCC and –32/64 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating D D D D D D Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise ESD Protection Exceeds JESD-22 – 2000-V Human-Body Model – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) (A114-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Packaged in Plastic Fine-Pitch Ball Grid Array Package NOTE: For tape and reel order entry: The GKER package is abbreviated to KR. description The ’ALVTH32374 devices are 32-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flops take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH32374 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALVTH32374 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z terminal assignments GKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 A 1Q2 1Q1 1OE 1CLK 1D1 1D2 A B 1Q4 1Q3 GND GND 1D3 1D4 B C 1Q6 1Q5 C 1Q7 1VCC GND 1D6 1Q8 1VCC GND 1D5 D 1D7 1D8 E 2Q2 2Q1 GND GND 2D1 2D2 F 2Q4 2Q3 2D4 2Q6 2Q5 1VCC GND 2D3 G 1VCC GND 2D5 2D6 H 2Q7 2Q8 2OE 2CLK 2D8 2D7 J 3Q2 3Q1 3OE 3CLK 3D1 3D2 K 3Q4 3Q3 GND GND 3D3 3D4 J L 3Q6 3Q5 3Q8 3Q7 2VCC GND 3D6 M 2VCC GND 3D5 K 3D7 3D8 1 2 3 4 5 6 D E F G H L N 4Q2 4Q1 GND GND 4D1 4D2 M P 4Q4 4Q3 4D4 N 4Q6 4Q5 2VCC GND 4D3 R 2VCC GND 4D5 4D6 P T 4Q7 4Q8 4OE 4CLK 4D8 4D7 R T 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 logic diagram (positive logic) 1OE A3 2OE A4 H4 1CLK 2CLK C1 1D1 H3 A5 A2 1D C1 1Q1 2D1 E5 To Seven Other Channels E2 1D 2Q1 To Seven Other Channels NOTE A: 1VCC is associated with these channels. 3OE J3 4OE J4 T4 3CLK 4CLK C1 3D1 T3 J5 J2 1D C1 3Q1 4D1 N5 To Seven Other Channels 1D N2 4Q1 To Seven Other Channels NOTE B: 2VCC is associated with these channels. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output current in the low state, IO: SN54ALVTH32374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH32374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH32374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA SN74ALVTH32374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3) SN54ALVTH32374 SN74ALVTH32374 MIN MAX MIN 2.7 2.3 VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH High-level output current IOL ∆t/∆v TYP TYP 2.7 1.7 0 VCC 5.5 0.7 0 VCC –6 Low-level output current V V 5.5 V –8 mA 6 8 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24 Input transition rise or fall rate 10 10 Outputs enabled UNIT V 0.7 Input voltage MAX mA ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3) SN54ALVTH32374 SN74ALVTH32374 MIN MAX MIN 3.6 3 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH High-level output current Low-level output current Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz IOL TYP TYP 3.6 2 0 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled VCC UNIT V V 0.8 Input voltage MAX 0.8 V 5.5 V –24 –32 mA 24 32 48 64 5.5 0 10 VCC 10 –40 ns/V µs/V 200 125 mA 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL VCC = 2 2.3 3V Control inputs VCC = 2.7 V, VCC = 0 or 2.7 V, Data inputs VCC = 2.7 V II Ioff IBHL‡ IBHH§ SN54ALVTH32374 MIN TYP† MAX TEST CONDITIONS SN74ALVTH32374 MIN TYP† MAX –1.2 VCC–0.2 1.8 –1.2 V 1.8 IOL = 100 µA IOL = 6 mA 0.2 0.2 0.4 IOL = 8 mA IOL = 18 mA 0.4 V 0.5 IOL = 24 mA VI = VCC or GND 0.5 ±1 ±1 VI = 5.5 V VI = 5.5 V 10 10 10 10 VI = VCC VI = 0 1 1 –5 –5 ±100 VI or VO = 0 to 4.5 V VI = 0.7 V VCC = 2.3 V, VCC = 2.7 V, VI = 1.7 V VI = 0 to VCC IEX|| VCC = 2.7 V, VCC = 2.3 V, VI = 0 to VCC VO = 5.5 V IOZ(PU/PD)k VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 2.7 V IOZL VCC = 2.7 V VCC = 2.7 V, IO = 0, VI = VCC or GND Outputs high 0.04 0.1 0.04 0.1 ICC Outputs low 2.3 4.5 2.3 4.5 Outputs disabled 0.04 0.1 0.04 0.1 VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 3.5 Ci V VCC–0.2 VCC = 0, VCC = 2.3 V, IBHLO¶ IBHHO# UNIT µA µA 115 115 µA –10 –10 µA 300 300 µA –300 –300 µA 125 125 µA ±100 ±100 µA VO = 2.3 V, VI = 0.7 V or 1.7 V 5 5 µA VO = 0.5 V, VI = 0.7 V or 1.7 V –5 –5 µA 3.5 mA pF Co 6 6 pF † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 3 V to 3.6 V, VOL VCC = 3 V Control inputs Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# IEX|| 2 IOL = 100 µA IOL = 16 mA 0.2 IOL = 24 mA IOL = 32 mA 0.5 IOL = 48 mA IOL = 64 mA 0.55 0.2 0.4 0.5 V 0.55 ±1 ±1 10 10 10 10 1 1 VCC = 3.6 V VI = 0 VI or VO = 0 to 4.5 V –5 VCC = 3.6 V, VCC = 3 V, V V VI = 5.5 V VI = VCC VCC = 3 V, VCC = 3.6 V, –1.2 UNIT VCC–0.2 VI = VCC or GND VI = 5.5 V VCC = 0, VCC = 3 V, SN74ALVTH32374 MIN TYP† MAX –1.2 VCC–0.2 2 VCC = 3.6 V, VCC = 0 or 3.6 V, II Data inputs SN54ALVTH32374 MIN TYP† MAX TEST CONDITIONS VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC µA –5 ±100 µA 75 75 µA –75 –75 µA 500 500 µA –500 µA –500 125 125 µA ±100 ±100 µA IOZ(PU/PD)k VO = 5.5 V VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 3.6 V VO = 3 V, VI = 0.8 V or 2 V 5 5 µA IOZL VCC = 3.6 V VO = 0.5 V, VI = 0.8 V or 2 V –5 –5 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.07 Outputs low Outputs disabled ∆ICCh VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VCC = 3.3 V, VCC = 3.3 V, Co VI = 3.3 V or 0 VO = 3.3 V or 0 0.1 0.07 0.1 3.2 5 3.2 5 0.07 0.1 0.07 0.1 0.4 0.4 3.5 3.5 6 6 mA mA pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) SN54ALVTH32374 MIN fclock tw Clock frequency MAX SN74ALVTH32374 MIN 150 Pulse duration, CLK high or low tsu Setup time, time data before CLK↑ th Hold time, time data after CLK↑ MAX 150 1.5 1.5 Data high 1.1 1 Data low 1.4 1.3 Data high 0.6 0.5 Data low 0.9 0.8 UNIT MHz ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) SN54ALVTH32374 MIN fclock tw Clock frequency tsu Setup time, time data before CLK↑ th Hold time, time data after CLK↑ MAX SN74ALVTH32374 MIN 250 Pulse duration, CLK high or low MAX 250 1.5 1.5 Data high 1.1 1 Data low 1.6 1.5 Data high 0.6 0.5 Data low 1.1 1 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALVTH32374 MIN MAX 150 CLK Q OE Q OE Q SN74ALVTH32374 MIN MAX 150 UNIT MHz 1.4 3.9 1.5 3.8 1.4 3.9 1.5 3.8 1 4.2 1 4.1 1 3.8 1 3.7 1.7 4.3 1.8 4.2 1 3.5 1 3.4 ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALVTH32374 MIN MAX 250 CLK Q OE Q OE Q SN74ALVTH32374 MIN MAX 250 UNIT MHz 1 3.4 1 3.2 1 3.3 1 3.2 1 3.9 1 3.8 1 3.4 1 3.3 1 4.7 1 4.6 1 4.4 1 4.2 ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH32374, SN74ALVTH32374 2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES280 – SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 1.5 V 0V 1.5 V 0V tPLH Output tPLZ 3V 1.5 V tPZH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL VOH 1.5 V 1.5 V tPZL 3V 1.5 V 3V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V 0V tsu Data Input 1.5 V Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated