TI SN74ABT3611

SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
D
D
D
D
D
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
64 × 36 Clocked FIFO Buffering Data From
Port A to Port B
Mailbox-Bypass Register In Each Direction
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
Full Flag and Almost-Full Flag
Synchronized by CLKA
D
D
D
D
D
D
D
Empty Flag and Almost-Empty Flag
Synchronized by CLKB
Passive Parity Checking on Each Port
Parity Generation Can Be Selected for Each
Port
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 10 ns
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired.
Parity generation can be selected for data read from each port. Two or more devices are used in parallel to create
wider datapaths.
The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FF) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port clock that writes
data to its array (CLKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage
synchronized to the port clock that reads data from its array.
The SN74ABT3611 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
•
•
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature
number SCAA007)
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC – No internal connection
2
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• DALLAS, TEXAS 75265
W/RB
CLKB
ENB
CSB
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AFA
FFA
CSA
ENA
CLKA
W/RA
VCC
PGA
PEFA
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
PEFB
PGB
VCC
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
NC
NC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A24
A25
A26
VCC
A27
A28
A29
GND
A30
A31
A32
A33
A34
A35
GND
B35
B34
B33
B32
B31
B30
GND
B29
B28
B27
VCC
B26
B25
B24
B23
PCB PACKAGE
(TOP VIEW)
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
NC
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
AFA
FFA
CSA
ENA
CLKA
W/RA
VCC
PGA
PEFA
GND
MBF2
MBA
FS1
FS0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
GND
PEFB
PGB
VCC
W/RB
CLKB
ENB
CSB
NC
NC
PQ PACKAGE†
(TOP VIEW)
17 16 15 14 13 12 11 10 9
GND
NC
NC
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
8
7
6
5
4
3
2
18
1 132 130 128
126 124
122 120 118
129
131
125 123
121
119
127
117
116
19
115
20
114
21
113
22
112
23
111
24
110
25
109
26
108
27
107
28
106
29
105
30
104
31
103
32
102
33
101
34
100
35
99
36
98
37
97
38
96
39
95
40
94
41
93
42
92
43
91
44
90
45
89
46
88
47
87
48
86
49
85
84
50
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
VCC
A24
A25
A26
GND
A27
A28
A29
V CC
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
B33
GND
B32
B31
B30
V CC
B29
B28
B27
GND
B26
B25
B24
V CC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
† Uses Yamaichi socket IC51-1324-828
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3
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
functional block diagram
CLKA
CSA
W/RA
ENA
MBA
Mail1
Register
PEFB
Parity
Gen/Check
PGB
36
64 × 36
SRAM
Write
Pointer
A0 – A35
Output Register
Device
Control
Parity
Generation
ODD/
EVEN
MBF1
Input Register
RST
Port-A
Control
Logic
36
Read
Pointer
B0 – B35
Status-Flag
Logic
FF
AF
EF
AE
FIFO
FS0
FS1
ProgrammableFlag
Offset Register
PGA
PEFA
Parity
Gen/Check
Mail2
Register
Port-B
Control
Logic
MBF2
4
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CLKB
CSB
W/RB
ENB
MBB
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
I/O
A0 – A35
I/O
Port-A data. The 36-bit bidirectional data port for side A.
AE
O
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the offset register, X.
AF
O
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the offset register, X.
B0 – B35
I/O
Port-B data. The 36-bit bidirectional data port for side B.
CLKA
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.
CLKB
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. EF and AE are synchronized to the low-to-high transition of CLKB.
CSA
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0 – A35 outputs are in the high-impedance state when CSA is high.
CSB
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0 – B35 outputs are in the high-impedance state when CSB is high.
EF
O
Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads from
its memory are disabled. Data can be read from the FIFO to its output register when EF is high. EF is forced low when
the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO
memory.
ENA
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB
I
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FF
O
Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its
memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition of
CLKA after reset.
FS1, FS0
I
Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the almost-full and almost-empty offset register, X.
MBA
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
MBB
I
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0 – B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
the FIFO output register data for output.
MBF1
O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1 is set high when the device is reset.
MBF2
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA
O
(port A)
DESCRIPTION
Port-A parity error flag. When any byte applied to A0 – A35 fails parity, PEFA is low. Bytes are organized as A0 – A8,
A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of ODD/EVEN.
The parity trees used to check the A0 – A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/RA low,
MBA high, and PGA high, PEFA is forced high, regardless of the state of the A0 – A35 inputs.
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5
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
Terminal Functions (continued)
TERMINAL
NAME
PEFB
I/O
O
(port B)
DESCRIPTION
Port-B parity error flag. When any byte applied to terminals B0 – B35 fails parity, PEFB is low. Bytes are organized as
B0 – B8, B9 – B17, B18 –B26, and B27 – B35, with the most-significant bit of each byte serving as the parity bit. The type
of parity checked is determined by the state of ODD/EVEN.
The parity trees used to check the B0 – B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB low, ENB high, W/RB
low, MBB high, and PGB high, PEFB is forced high regardless of the state of the B0 – B35 inputs.
PGA
I
Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity
generated is selected by the state of ODD/EVEN. Bytes are organized as A0 – A8, A9 – A17, A18– A26, and A27 – A35.
The generated parity bits are output in the most-significant bit of each byte.
PGB
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of ODD/EVEN. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and B27 – B35. The
generated parity bits are output in the most significant bit of each byte.
RST
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. This sets AF, MBF1, and MBF2 high and EF, AE, and FF low. The low-to-high transition of RST latches
the status of FS1 and FS0 to select AF and AE flag offset.
W/RA
I
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high.
W/RB
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is high.
detailed description
reset
The SN74ABT3611 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of the FIFO and forces the full flag (FF) low, the empty flag (EF)
low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags
(MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be
reset after power up before data is written to its memory.
A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
Table 1. Flag Programming
FS1
FS0
RST
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
↑
16
H
L
↑
12
L
H
↑
8
L
L
↑
4
FIFO write/read operation
The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the
A0– A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FF is high (see Table 2).
6
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
FIFO write/read operation (continued)
Table 2. Port-A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0 – A35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO write
L
H
H
H
↑
In high-impedance state
Mail1 write
L
L
L
L
X
Active, mail2 register
None
L
L
H
L
↑
Active, mail2 register
None
L
L
L
H
X
Active, mail2 register
None
L
L
H
H
↑
Active, mail2 register
Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A. The state of the port-B data (B0 – B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 – B35 outputs are
in the high-impedance state when either CSB or W/RB is high. The B0 – B35 outputs are active when both CSB
and W/RB are low. Data is read from the FIFO to the B0 – B35 outputs by a low-to-high transition of CLKB when
CSB is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
MBB
CLKB
B0 – B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
None
L
H
H
H
↑
In high-impedance state
Mail2 write
L
L
L
L
X
Active, FIFO output register
None
L
L
H
L
↑
Active, FIFO output register
FIFO read
L
L
L
H
X
Active, mail1 register
None
L
L
H
H
↑
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
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7
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB.
Table 4 shows the relationship of the flags to the FIFO.
Table 4. FIFO Flag Operation
NUMBER OF WORDS
IN THE FIFO
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
EF
AE
AF
FF
0
L
L
H
H
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
L
† X is the value in the almost-empty flag and almost-full flag offset register.
empty flag (EF)
The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When EF is high,
new data can be read to the FIFO output register. When EF is low, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked to its output register. A word written to
the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles; therefore,
EF is low if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have
not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high
transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs
at time tsk1, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization
cycle (see Figure 4).
full flag (FF)
The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an
SRAM location is free to receive new data. No memory locations are free when FF is low and attempted writes
to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is incremented. From the time a word is read from the
FIFO, its previous memory location is ready to be written in a minimum of three port-A clock cycles. FF is low
if less than two CLKA cycles have elapsed since the next memory write location has been read. The second
low-to-high transition on CLKA after the read sets FF high and data can be written in the following clock cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization
cycle (see Figure 5).
8
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
almost-empty flag (AE)
The FIFO almost-empty flag is synchronized to the port clock that reads data from its array (CLKB). The
almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register
is loaded with one of four preset values during a device reset (see reset). AE is low when the FIFO contains
X or fewer words in memory and is high when the FIFO contains (X + 1) or more words.
Two low-to-high transitions on the port-B clock (CLKB) are required after a FIFO write for the almost-empty flag
to reflect the new level of fill. The almost-empty flag (AE) of a FIFO containing (X + 1) or more words remains
low if two CLKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. AE is set high
by the second CLKB low-to-high transition after the FIFO write that fills memory to the (X + 1) level. A low-to-high
transition on CLKB begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that
fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 6).
almost-full flag (AF)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full
state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with
one of four preset values during a device reset (see reset). AF is low when the FIFO contains (64 – X) or more
words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer words.
Two low-to-high transitions on the port-A clock (CLKA) are required after a FIFO read for AF to reflect the new
level of fill. The almost-full flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two CLKA cycles
have not elapsed since the read that reduced the number of words in memory to [64 – (X + 1)]. AF is set high
by the second CLKA low-to-high transition after the FIFO read that reduces the number of words in memory
to [64 – (X + 1)]. A low-to-high transition on CLKA begins the first synchronization cycle if it occurs at time tsk2,
or greater, after the read that reduces the number of words in memory to [64 – (X + 1)]. Otherwise, the
subsequent CLKA cycle can be the first synchronization cycle (see Figure 7).
mailbox registers
Two 36-bit bypass registers are on the SN74ABT3611 to pass command and control information between port
A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port-data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when
a port-A write is selected by(CSA, W/RA, and ENA) with MBA high. A low-to-high transition on CLKB writes
B0– B35 data to the mail2 register when a port-B write is selected by (CSB, W/RB, and ENB) with MBB high.
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register
are ignored while its mail flag is low.
When the port-B data (B0 – B35) outputs are active, the data on the bus comes from the FIFO output register
when MBB is low and from the mail1 register when MBB is high. Mail2 data is always present on A0 – A35 outputs
when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a
port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by
a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The
data in a mail register remains intact after it is read and changes only when new data is written to the register.
parity checking
The port-A (A0 – A35) inputs and port-B (B0 – B35) inputs each have four parity trees to check the parity of
incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on
the port-parity-error flag (PEFA, PEFB). Odd or even parity checking can be selected and the parity-error flags
can be ignored if this feature is not desired.
POST OFFICE BOX 655303
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
parity checking (continued)
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more bytes of a port is reported by a low level on the corresponding port parity
error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, and
port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35. When odd/even parity is selected,
PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to its bits.
The four parity trees used to check the A0 – A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, PEFA is held high, regardless of the
levels applied to the A0 – A35 inputs. Likewise, the parity trees used to check the B0 – B35 inputs are shared
by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from
the mail1 register with parity generation is selected with CSB low, ENB high, W/RB low, MBB high, and PGB
high, PEFB is held high, regardless of the levels applied to the B0 – B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN74ABT3611 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless
of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the
ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. Therefore, the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time
constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read a new word to the FIFO output
register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0 – B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0 – A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB
is low, MBA, MBB is high, CSA, CSB is low, ENA, ENB is high, and PGA, PGB is high. Generating parity for
mail-register data does not change the contents of the register.
10
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
th(RS)
CLKB
tsu(RS)
RST
FS1, FS0
th(FS)
tsu(FS)
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
0,1
tpd(C-FF)
FF
tpd(C-FF)
tpd(C-EF)
EF
tpd(C-AE)
AE
tpd(C-AF)
AF
MBF1,
MBF2
tpd(R-F)
Figure 1. Device Reset Loading the X Register With the Value of Eight
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
tc
tw(CLKH)
tw(CLKL)
CLKA
FF
High
ÌÌÌ
ÌÌÌ
ÏÏÏÏÏÏÏÏ ÌÌÌ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏ
ÌÌÌ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÌÌÌ
ÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎ
ÌÌÌ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌ ÎÎÎÎÎÎÎ ÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ
É
tsu(EN1)
th(EN1)
tsu(EN1)
th(EN1)
tsu(EN3)
th(EN3)
tsu(EN2)
th(EN2) tsu(EN2)
CSA
W/RA
th(EN2)
MBA
th(EN2)
tsu(EN2)
ENA
tsu(D)
th(D)
W1
A0 – A35
No Operation
W2
ODD/
EVEN
tpd(D-PE)
PEFA
tpd(D-PE)
Valid
Valid
Figure 2. FIFO1 Write-Cycle Timing
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
tc
tw(CLKH)
tw(CLKL)
CLKB
EF
High
CSB
ÎÎÎÎ
ÏÏÏÏÏÏ
W/RB
MBB
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
tsu(EN2)
ENB
tpd(M-DV)
ten
B0 – B35
PGB,
ODD/
EVEN
tsu(PG)
ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ
tsu(EN2)
th(EN2)
tsu(EN2)
th(EN2)
ta
Previous Data
th(PG)
th(EN2)
No
Operation
ta
Word 1
tdis
Word 2
ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu(PG)
th(PG)
Figure 3. FIFO Read-Cycle Timing
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
tc
tw(CLKH)
tw(CLKL)
CLKA
CSA Low
W/RA High
tsu(EN3)
ÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÎÎÎÎÎ
ÏÏÏÏÎÎÎÎÎ
ÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(EN3)
MBA
tsu(EN2)
th(EN2)
ENA
FFA High
A0 – A35
tsu(D)
th(D)
W1
tsk1†
tc
tw(CLKL)
tw(CLKH)
1
CLKB
2
tpd(C-EF)
EF
tpd(C-EF)
Empty FIFO
CSB Low
W/RB Low
MBB Low
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu(EN2)
th(EN2)
ENB
ta
B0 – B35
W1
† tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of EF high may occur one CLKB cycle later than shown.
Figure 4. EF-Flag Timing and First Data Read When the FIFO Is Empty
14
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
tc
tw(CLKH)
tw(CLKL)
CLKB
CSB
Low
W/RB
Low
MBB
Low
ÏÏÏÏ ÎÎÎ
tsu(EN2)
ENB
EFB
th(EN2)
High
ta
B0 – B35 Previous Word in FIFO Output Register
Next Word From FIFO
tsk1†
tc
tw(CLKH)
1
CLKA
Full FIFO
FF
CSA
W/RA
MBA
ENA
tw(CLKL)
2
tpd(C-FF)
tpd(C-FF)
Low
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ
High
tsu(EN3)
th(EN3)
tsu(EN2)
th(EN2)
tsu(D)
A0 – A35
th(D)
To FIFO
† tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less tsk1, FF may transition high one CLKA cycle later than shown.
Figure 5. FF-Flag Timing and First Available Write When the FIFO Is Full
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
ÏÏÏÏÏÎÎÎÎÎ
ÏÏÏÏÏÎÎÎÎÎ
th(EN2)
tsu(EN2)
ENA
tsk2†
CLKB
1
2
tpd(C-AE)
tpd(C-AE)
AE
X Words in FIFO
ÏÏÏÏÏÎÎÎÎÎ
ÏÏÏÏÏÎÎÎÎÎ
(X + 1) Words in FIFO
tsu(EN2)
ENB
th(EN2)
† tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AE may transition high one CLKB cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 6. Timing for AE When the FIFO Is Almost Empty
tsk2‡
CLKA
ENA
1
ÏÏÏÏÏÎÎÎÎÎ
ÏÏÏÏÏÎÎÎÎÎ
tpd(C-AF)
AF
CLKB
[64 – (X + 1)] Words in FIFO
tpd(C-AF)
(64 – X) Words in FIFO
ÏÏÏÏÏ ÎÎÎÎÎ
ÏÏÏÏÏ ÎÎÎÎÎ
tsu(EN2)
ENB
2
th(EN2)
tsu(EN2)
th(EN2)
‡ tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, AF may transition high one CLKB cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for AF When the FIFO Is Almost Full
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
th(EN1)
tsu(EN1)
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
CSA
W/RA
MBA
ENA
tsu(D)
A0 – A35
W1
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(D)
CLKB
tpd(C-MF)
tpd(C-MF)
MBF1
CSB
W/RB
ÎÎÎÎ
MBB
ÏÏÏÏÏÏ
ÏÏÏÏ ÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
tsu(EN2)
ENB
th(EN2)
tpd(M-DV)
ten
tpd(C-MR)
B0 – B35
tdis
W1 (remains valid in mail1 register after read)
FIFO Output Register
NOTE A: Port-B parity generation off (PGB = L)
Figure 8. Timing for Mail1 Register and MBF1 Flag
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKB
th(EN1)
tsu(EN1)
CSB
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
W/RB
MBB
ENB
tsu(D)
B0 – B35
W1
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
th(D)
CLKA
tpd(C-MF)
tpd(C-MF)
MBF2
CSA
ÏÏÏÏÏ
W/RA
MBA
ÎÎÎÎÎÎ
ÏÏÏÏ ÎÎÎÎ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
tsu(EN2)
ENA
ten
A0 – A35
tdis
tpd(C-MR)
W1 (remains valid in mail2 register after read)
NOTE A: Port-A parity generation off (PGA = L)
Figure 9. Timing for Mail2 Register and MBF2 Flag
18
th(EN2)
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
ODD/
EVEN
W/RA
MBA
PGA
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
tpd(O-PE)
PEFA
tpd(O-PE)
Valid
Valid
tpd(E-PE)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tpd(E-PE)
Valid
Valid
NOTE A: CSA = L and ENA = H
Figure 10. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
MBB
PGB
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
tpd(O-PE)
PEFB
tpd(O-PE)
Valid
Valid
tpd(E-PE)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tpd(E-PE)
Valid
Valid
NOTE A: CSB = L and ENB = H
Figure 11. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
ODD/
EVEN
CSA Low
W/RA
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
MBA
PGA
ten
A8, A17,
A26, A35
tpd(E-PB)
tpd(O-PB)
Generated Parity
Mail2 Data
tpd(E-PB)
Generated Parity
Mail2 Data
NOTE A: ENA = H
Figure 12. Parity-Generation Timing When Reading From the Mail2 Register
ODD/
EVEN
CSB Low
W/RB
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌ
MBB
PGB
B8, B17,
B26, B35
tpd(E-PB)
tpd(M-DV)
ten
NOTE A: ENB = H
tpd(O-PB)
Generated Parity
tpd(E-PB)
Generated Parity
Mail1
Data
Figure 13. Parity-Generation Timing When Reading From the Mail1 Register
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Mail1 Data
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
Package thermal impedance, θJA (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
–4
mA
IOL
TA
Low-level output current
8
mA
70
°C
High-level input voltage
2
Operating free-air temperature
0
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 4 mA
IOL = 8 mA
II
IOZ
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or 0
VO = VCC or 0
ICC
VCC = 5.5 V,
IO = 0 mA,
MIN
TYP‡
2.4
VI = VCC or GND
VI = 0,
VO = 0,
UNIT
V
0.5
V
± 50
µA
± 50
µA
Outputs high
60
Outputs low
130
Outputs disabled
Ci
MAX
mA
60
f = 1 MHz
4
pF
Co
f = 1 MHz
‡ All typical values are at VCC = 5 V, TA = 25°C.
8
pF
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CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 14)
’ABT3611-15
MIN
fclock
Clock frequency, CLKA or CLKB
tc
Clock cycle time, CLKA or CLKB
MAX
’ABT3611-20
MIN
66.7
MAX
’ABT3611-30
MIN
50
MAX
33.4
UNIT
MHz
15
20
30
MHz
tw(CLKH) Pulse duration, CLKA and CLKB high
6
8
12
ns
tw(CLKL)
Pulse duration, CLKA and CLKB low
6
8
12
ns
tsu(D)
Setup time, A0 – A35 before CLKA↑ and B0 – B35 before CLKB↑
4
5
6
ns
tsu(EN1)
Setup time, CSA, W/RA before CLKA↑; CSB, W/RB,
before CLKB↑
6
6
7
ns
tsu(EN2)
Setup time, ENA before CLKA↑; ENB before CLKB↑
4
5
6
ns
tsu(EN3)
Setup time, MBA before CLKA↑; ENB before CLKB↑
4
5
6
ns
tsu(PG)
Setup time, ODD/EVEN and PGB before CLKB↑†
4
5
6
ns
tsu(RS)
Setup time, RST low before CLKA↑ or CLKB↑‡
5
6
7
ns
tsu(FS)
Setup time, FS0 and FS1 before RST high
5
6
7
ns
th(D)
Hold time, A0 – A35 after CLKA↑ and B0 – B35 after CLKB↑
1
1
1
ns
th(EN1)
Hold time, CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑
1
1
1
ns
th(EN2)
Hold time, ENA after CLKA↑; ENB after CLKB↑
1
1
1
ns
th(EN3)
Hold time, MBA after CLKA↑; MBB after CLKB↑
1
1
1
ns
th(PG)
Hold time, ODD/EVEN and PGB after CLKB↑†
0
0
0
ns
th(RS)
Hold time, RST low after CLKA↑ or CLKB↑‡
6
6
7
ns
th(FS)
Hold time, FS0 and FS1 after RST high
4
4
4
ns
tsk1§
Skew time between CLKA↑ and CLKB↑ for EFA, EFB,
FFA, and FFB
8
8
10
ns
tsk2§
Skew time between CLKA↑ and CLKB↑ for AEA, AEB,
AFA, and AFB
9
16
20
ns
† Applies only for a rising edge of CLKB that does a FIFO read
‡ Requirement to count the clock edge as one of at least four needed to reset a FIFO
§ Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Figures 1 through 13)
’ABT3611-15
PARAMETER
MIN
MAX
fmax
’ABT3611-20
MIN
66.7
MAX
’ABT3611-30
MIN
50
MAX
UNIT
33
ns
ta
Access time, CLKB↑ to B0 – B35
2
10
2
12
2
15
ns
tpd(C-FF)
Propagation delay time, CLKA↑ to FF
2
10
2
12
2
15
ns
tpd(C-EF)
Propagation delay time, CLKB↑ to EF
2
10
2
12
2
15
ns
tpd(C-AE)
Propagation delay time, CLKB↑ to AE
2
10
2
12
2
15
ns
tpd(C-AF)
Propagation delay time, CLKA↑ to AF
2
10
2
12
2
15
ns
tpd(C-MF)
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
1
9
1
12
1
15
ns
tpd(C-MR)
Propagation delay time, CLKA↑ to B0 – B35† and CLKB↑ to
A0 – A35‡
3
12
3
14
3
16
ns
tpd(M-DV)
Propagation delay time, MBB to B0 – B35 valid
1
11
1
11.5
1
12
ns
tpd(D-PE)
Propagation delay time, A0 – A35 valid to PEFA valid; B0 – B35
valid to PEFB valid
3
12
3
13
3
14
ns
tpd(O-PE)
Propagation delay time, ODD/EVEN to PEFA and PEFB
3
11
3
12
3
14
ns
tpd(O-PB)§
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26,
A35) and (B8, B17, B26, B35)
2
12
2
13
2
15
ns
tpd(E-PE)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
PEFA; CSB, ENB, W/RB, MBB, or PGB to PEFB
1
12
1
13
1
15
ns
tpd(E-PB)§
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, MBB, or PGB
to parity bits (B8, B17, B26, B35)
3
14
3
15
3
16
ns
tpd(R-F)
Propagation delay time, RST to AE low and (AF, MBF1, MBF2)
high
1
15
1
20
1
30
ns
ten
Enable time, CSA and W/RA low to A0 – A35 active and CSB low
and W/RB high to B0 – B35 active
2
10
2
12
2
14
ns
tdis
Disable time, CSA or W/RA high to A0 – A35 at high impedance
and CSB high or W/RB low to B0 – B35 at high impedance
1
9
1
10
1
11
ns
† Writing data to the mail1 register when the B0 – B35 outputs are active and MBB is high.
‡ Writing data to the mail2 register when the A0 – A35 outputs are active and MBA is high.
§ Applies only when reading data from a mail register
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
5V
1.1 kΩ
From Output
Under Test
680 Ω
30 pF
(see Note A)
LOAD CIRCUIT
3V
3V
Timing
Input
High-Level
Input
1.5 V
GND
tw
3V
Data,
Enable
Input
1.5 V
3V
1.5 V
Low-Level
Input
GND
1.5 V
1.5 V
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Enable
1.5 V
GND
th
tsu
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
1.5 V
1.5 V
GND
tPLZ
Low-Level
Output
tPZL
≈3V
1.5 V
VOL
3V
≈0V
tpd
tpd
VOH
1.5 V
1.5 V
GND
tPZH
High-Level
Output
1.5 V
Input
VOH
In-Phase
Output
1.5 V
1.5 V
VOL
tPHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B. tPZL and tPZH are the same as ten.
C. tPLZ and tPHZ are the same as ten.
Figure 14. Load Circuit and Voltage Waveforms
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
fdata = 1/2 fclock
TA = 25°C
CL = 0 pF
I CC(f) – Supply Current – mA
350
300
VCC = 5.5 V
VCC = 5 V
250
200
VCC = 4.5 V
150
100
50
0
0
10
20
30
40
50
60
70
80
fclock – Clock Frequency – MHz
Figure 15
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
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