Programmable Analog Signal Processor GENNUM C␣ ␣ O␣ ␣ R␣ ␣ P␣ ␣ O␣ ␣ R␣ ␣ A␣ ␣ T␣ ␣ I␣ ␣ O␣ ␣ N GP520A - DATA SHEET FEATURES Principle features of the preamp are the input impedance 100 kΩ and a gain of 14 dB. • programmable parameters - gain - low pass filter - high pass filter - AGC threshold - release time - MPO - receiver bias voltage The programmable filter block is composed of a low pass and high pass filter which generates a range of high and low pass corner frequencies. Although the control current to this block varies linearly, linear to logarithmic conversion is performed internally in order to adjust the corner frequencies logarithmically. Both filters feature a 12 dB/octave rolloff and unity gain. • on-chip voltage regulator • typical gain 60 dB • voltage drive output stage • telecoil preamp The filters are followed by an AGC block. Up to 35␣ dB of adjustable gain is provided as well as programmable threshold and release time. The attack time of the AGC block remains fixed and is independent of the release time. The output current is driven into the preamp of the clipper, thus, the AGC converts a voltage input into a current output and is therefore, a transconductance block. STANDARD PACKAGING • Chip (136 x 110 mils) Au Bump CIRCUIT DESCRIPTION The next stage is an electronic MPO control peak “clipper” providing electronic clipping of the signal and setting of the maximum output level. The clipper output is also a transconductance block and drives a 40 kΩ resistor (ROUT␣ 8) tied to the supply. The GP520A is a programmable analog signal path IC designed for use in hearing instruments. The GP520A’s programmable parameters are adjusted by external programming currents, such as generated by the GP521. The GP520A provides a 2.5 µA reference current for use by the GP521. Sixteen settings are possible in the GP521, allowing the Programmable Current Sink (PCS) to sink between 0 and 1.875 x IREF . The input of the final stage is an inverting operational amplifier. A feedback resistance of 240 kΩ is provided internally and this final stage is thus configured as a voltage drive output stage. The DC bias current through the receiver is also programmable. The GP520A is composed of five functional blocks. The input preamp, a filter block, the AGC block, MPO clipper and the output stage. V REG V CC A OUT 9 15 HPFB HP 18 BUFFER IN 24 LPFB 22 19 BUFFER OUT 26 RECT. IN CAGC 27 1 DELTA CCOMP OUT B IN 3 5 31 B OUT CCLIP 7 30 V cc 13 VOLTAGE REGULATOR FULL WAVE RECTIFIER R THRESHOLD R OUT 8 + 28 LP FILTER AGC VC AMP CLIPPER - 50k COUT 8 R 29 + HP + 2R PREAMP A IN 14 AVERAGING CIRCUIT RIN14 - FILTER - 40K R 11 DOUT OUTPUT + LIN/LOG CONVERTER 12 DIN - 10K P GND 10 RF 6 GND 20 I HP LIN/LOG CONVERTER 21 I LP LIN/LOG CONVERTER I REF 16 I REF 25 I REL VBIAS 2 23 I THRESH I GAIN 4 I CLIP 17 I BIAS All resistors in ohms, all capacitors in farads unless otherwise stated. FUNCTIONAL BLOCK DIAGRAM Revision Date: May 1998 Document No. 510 - 78 - 06 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 Web Site: www.gennum.com E-mail: [email protected] CHIP PAD DIAGRAM ABSOLUTE MAXIMUM RATINGS 30 31 CCOMP 28 29 CCLIP 27 TEL-B TEL-C RECT.IN PARAMETER VALUE / UNITS 1 CAGC Supply Voltage 5V 2 I THRESH 3 DELTA OUT 4 I CLIP I GAIN 23 5 B IN LPFB 22 6 GND I LP 21 7 B OUT I HP 20 8 COUT 9 V CC Pad 3, 8, 10, 11, 13, 17 -0.1 V to VCC + 0.1 V Pad 1, 15, 16, 18, 19, 22, 24, 26 -0.1 V to VREG + 0.1 V Pad 4, 5, 7, 14, 20, 21, 23, 25, 27 -0.1 V to 0.7 V Pad 2 VREG -0.7 V to VREG + 0.1 V CAUTION CLASS 1 ESD SENSITIVITY BUFFER OUT 26 I REL 25 BUFFER IN 24 GP520A I BIAS 17 10 DIN I REF 16 11 DOUT 12 ELECTRICAL CHARACTERISTICS HP 19 HPFB 18 A OUT 15 PGND 13 V REG A IN 14 All parameters are measured at TA = 25oC All gains are calculated from equation G = 20 LOG (∆OUT/∆IN) where ∆OUT and ∆IN are appropriate voltage or current increases. All resistances are calculated according to equation R = (V P - VQ) / ICOND where V P is voltage on the pad loaded with I COND current. V Q - quiescent (unbias) voltage measured on the pad, (nothing connected to the pin). V P is the actual voltage measured on the pad at given condition (where P is pad number). For all graphs IREF is measured with 0.5V biased voltage on pin 16. GENERAL PARAMETER SYMBOL Amplifier Current IAMP Minimum Voltage VCC CONDITIONS MIN All PCS set to 15 TYP - 1.1 MAX 600 - - UNITS µA - V REGULATOR TESTS Regulator Voltage (Pad 13) VREG Short Circuit Current (Pad 13) ISC S1 — closed - 0.98 - V - 2.0 - mA - 2.5 - µA CURRENT REFERENCE Current Reference (Pad 16) IR PREAMPLIFIER Quiescent Voltage on Pad 14 VQ14 600 - - mV Quiescent Voltage on Pad 15 VQ15 600 - - mV Input Resistance (Pad 14) RIN 14 I14 = 0.3µA (S2 closed)(Note 1 ) - 100 - kΩ Output Swing High (Pad 15) VOH V 14 = 0.8V (S3 closed)(Note 1) 200 - - mV Output Swing Low (Pad 15) VOL V1 -200 - - mV Max Source Current (Pad 15) ISOURCE V14 = 0.8V (S3, S4 closed) V15 = VQ15+100mV 30 - - µA Max Sinking Current (Pad 15) ISINK V14 = 0.4V (S3,S4 closed) V15 = VQ15-100mV 30 - - µA Preamp Voltage Gain GAIN V14= V Q14 ± 10mV (S3 closed) - 14 - dB NOTE: 1. VOL = VOH = V P15 – VQ15 510 - 78 - 06 = 0.4V (S3 closed) All switches remain OPEN unless otherwise stated in CONDITIONS column. 2 S4 - - + + 1.3V 9 S1 10n 10n 68n 10K V15 A OUT V CC V REG 68n 27 1 26 31 B OUT B OUT CAGC 15 30 5 VCC 7 VOLTAGE REGULATOR 13 2k2 3µ3 11 A IN 14 DOUT + PREAMP S2 S3 - RIN14 40K 10K I14 V14 + 12 P GND 6 GND All resistors in ohms, all capacitors in farads unless otherwise stated. Fig. 1 Preamplifier and Regulator Test Circuit HIGH PASS FILTER PARAMETER SYMBOL CONDITIONS MIN Quiescent Voltage on Pad 18 VQ18 - Quiescent Voltage on Pad 19 VQ19 Quiescent Voltage on Pad 20 VQ20 Maximum DC Current from Pad 19 IHP MAX Minimum DC Current from Pad 19 Buffer Gain MAX UNITS 650 - mV - 650 - mV - 550 - mV I HP = 0µA ( S3 closed) - 2 - µA IHP MIN IHP=1.875 x I R (S3 closed) - 200 - nA GAIN V19 = VQ19 ± 100mV - 0 - dB - 13 - kΩ (S2 closed) Input Resistance Pad 20 RIN20 IHP = I R TYP All switches remain OPEN unless otherwise stated in CONDITIONS column. + V19 V CC V REG 18 10n 10n 68n 10K CAGC LPFB HPFB HP 9 68n S3 S2 19 22 27 1 26 30 B B OUT IN 31 5 13 2k2 R + HP 3µ3 VCC 7 11 2R FILTER - DOUT R LIN/LOG CONVERTER 12 P GND RIN 0.6 V 20 I HP 6 GND LIN/LOG CONVERTER 21 I LP All resistors in ohms, all capacitors in farads unless otherwise stated. I HP Fig. 2 High Pass Filter DC Test Circuit 3 510 - 78 - 06 LOW PASS FILTER PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Quiescent Voltage on Pad 21 VQ21 - 550 - mV Quiescent Voltage on Pad 22 VQ22 - 650 - mV Quiescent Voltage on Pad 24 VQ24 - 650 - mV Quiescent Voltage on Pad 26 VQ26 - 650 - mV Maximum DC Current from Pad 22 ILP MAX ILP = 0µA (S1 closed) - 2.0 - µA Minimum DC Current from Pad 22 ILP MIN ILP =1.875 x I R (S1 closed) - 0.7 - µA Output Swing High (Pad 26) VOH V24 = VQ24 + 100mV (S2 closed)(Note 1) - 100 - mV Output Swing Low (Pad 26) VOL V24 = VQ24 - 100mV (S2 closed )(Note 1) - -100 - mV Max Sinking Current from Pad 26 ISINK V24 = 0.4V; 30 - - µA -30 - - µA V 26 = VQ26 - 100mV (S2, S3 closed) Max Sourcing Current to Pad 26 V24 = 0.8V; V 26 = VQ26 ± 100mV ISOURCE (S2, S3 closed) Buffer Gain GAIN V26 = VQ26 ± 100mV - 0 - dB Input Resistance (Pad 21) RIN21 ILP = I R - 13 - kΩ NOTE: 1. VOH = V OL = V P26 - V Q26 All switches remain OPEN unless otherwise stated in CONDITIONS column. + + V24 V26 +1.3 V S2 S1 V CC LPFB 9 V REG 68n S3 BUFFER IN 22 BUFFER OUT 24 68n 10n RECT. C AGC IN 27 1 30 26 10n 10K B 31 IN 5 B OUT VCC 7 13 2k2 R + LP 3µ3 11 FILTER - DOUT R LIN/LOG CONVERTER 0.6 V I REF R IN 12 P GND 6 GND 21 I LP 16 I REF All resistors in ohms, all capacitors in farads, unless otherwise stated. I LP Fig. 3 Low Pass Filter DC Test Circuit 510 - 78 - 06 4 1n5 TP 680p 2n2 V CC A OUT 9 13 15 2n2 68n HPFB 18 BUFFER LPFB OUT 24 BUFFER 26 27 22 IN HP 19 VOLTAGE REGULATOR 68n 10n 10n 10K BOUT 1 31 30 5 BIN 7 VCC 2k2 R + 3µ3 LP FILTER 11 DOUT R AIN 14 + 2R PREAMP 10µ RIN14 + HP FILTER - 40K R 10K LIN/LOG CONVERTER 0.6V LIN/LOG CONVERTER 0.6 V 20 I HP 12 6 P GND GND 21 I LP All resistors in ohms, all capacitors in farads, unless otherwise stated. PINK NOISE GENERATOR I LP I HP Fig. 4 AC Test Circuit for High & Low Pass Filters 10k IHP = 1.875 x IR CORNER FREQUENCY (HZ) CORNER FREQUENCY (Hz) 10k 1k 1k 100 80 0 0.25 0.5 0.75 1 1.25 1.5 1.75 700 2 NORMALIZED I HP / I R CURRENT 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 NORMALIZED I HP / I R CURRENT Fig. 6 Low Pass Filter Corner Frequency vs I LP Current (Note 1) (Fig.4 Test Circuit) Fig. 5 High Pass Filter Corner Frequency vs IHP Current (Note 1) (Fig.4 Test Circuit) NOTES: 1. Corner frequency calculated in reference to signal at 3 kHz 5 510 - 78 - 06 AGC CONTROL STAGE PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Quiescent Voltage on Pad 2 VQ2 ITHRESH = I R - 400 - mV Quiescent Voltage on Pad 3 VQ3 IGAIN = IR x 1.875 - 700 - mV Quiescent Voltage on Pad 23 VQ23 - 500 - mV Quiescent Voltage on Pad 25 VQ25 - 500 - mV Quiescent Voltage on Pad 27 VQ27 - 600 - mV Release Current Max (Pad 1) IREL MAX IREL = 0 (S1 closed) - 300 - nA Release Current Min (Pad 1) IREL MIN IREL = 1.875 x I R (S1 closed) - 30 - nA Input Resistance (Pad 25) RIN25 IREL = I R - 17 - kΩ Input Resistance (Pad 27) RIN27 I27 = ± IR - 4 - kΩ Max Transconductance (Pad 26 to VO ) G MAX IGAIN =I R x 2 x 1.875 VP26=30 mV pp ITHRESH =1.875 x I R (Note 1) - 160 - µA/V Gain Range (Pad 26 to V ) o GAIN RANGE ITHRESH =1.875 x I R (Note 2) V26 = 25 mV pp - 33 - dB Output Limiting Level (Pad 3) OUTLIM ITHRESH =I R, I GAIN = 2 x 1.875 x I R - 0.7 - µARMS - 13 - dB - 5 - V26 = 100 mV pp (Note 3) Limiting Level Range LIMRANGE IGAIN = I R x 2 x1.875 (Note 4) V26 = 100 mV pp AGC Compression Ratio CMPRAT ITHRESH =I R IGAIN = 2 x 1.875 x I R (Note 5) Unless otherwise stated in CONDITIONS column all switches remain OPEN, all current sources are 0µA NOTES: 1. G MAX = V o / (V 26 x 1M) 4. LIM RANGE 5. CMP 2. GAINRANGE = 20 LOG ( V o[I GAIN = 2 x1.875 x I R]/ V o [I GAIN = 0]) RAT = = 20 LOG (Vo [I THRESH=1.875 x I R]/Vo [I THRESH =0] ) 10 20 LOG (V o [ V 26=5.62mV RMS]/V o[V 26=17.8mV RMS ]) -45dBV -35dBV 3. OUT LIM = V / 1M o R1=1M +12V 2 7 6 LT001 3 + 4 0.1 68n V IN LPFB 9 V REG 13 68n 10µ 1.3 V 22 VOLTAGE REGULATOR BUFFER OUT BUFFER IN 24 26 RECT. IN 27 FULL WAVE RECTIFIER R 10n S1 10k DELTA OUT C AGC 1 3 31 AVERAGING CIRCUIT B IN 7 -12V VCC 30 RF THRESHOLD 2k2 + 3µ3 5 10n B OUT VO LP FILTER AGC - 11 DOUT R AIN 14 V REG - 0.6 V LIN/LOG CONVERTER 12 P GND 6 23 2 I THRESH IGAIN 25 I REL GND I REL I THRESH IGAIN Fig. 7 AGC Control Stage Test Circuit 510 - 78 - 06 6 All resistors in ohms, all capacitors in farads unless otherwise stated. IINNIN = 63 dBV 1 30 ITHRESH = 1.875 x IR IN = - 63 dBV 20 R1=100kΩ GAIN (dB) RELEASE TIME (s) IGAIN = 3.75 x IR 0.1 10 0 -10 0.01 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 0.5 NORMALIZED I REL / I R CURRENT Fig. 8 Release Time vs I REL (Fig.7 Test Circuit) 1.5 2 2.5 3 3.5 4 GAIN / I R CURRENT Fig. 9 AGC Gain vs IGAIN (Fig.7 Test Circuit) -40 1 RF = 50kΩ IGAIN = 3.75 x I R VIN = - 30 dBV -50 CLIP LEVEL (Vp-p) INPUT THRESHOLD (dBV) 1 NORMALIZED I -60 (S3-b) 0.1 -70 0 0.25 0.5 0.75 1 1.25 NORMALIZED I THRESH / I 1.5 1.75 0.01 2 R CURRENT 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 NORMALIZED I CLIP / I R CURRENT Fig. 10 Threshold Level vs I THRESH (Fig.7 Test Circuit) Fig. 11 Output Swing vs ICLIP (Fig.13 Test Circuit) (note 1) 0.3 BIAS VOLTAGE (V) I10 = 0µA 0.25 0.2 0.15 0.1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 NORMALIZED I BIAS / I R CURRENT Fig. 12 Receiver Bias Voltage vs IBIAS (Fig. 14 Test Circuit) NOTE: 1. Switch S2 - open, S4 - closed. 7 510 - 78 - 06 CLIPPER STAGE PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Quiescent Voltage on Pad 5 V Q5 (S1 closed) - 550 - mV Input Bias Current (Pad 5) I BIAS RF1 =1M RF2=0Ω ( Note 1 ) - 0 - nA Quiescent Voltage on Pad 4 V Q4 - 500 - mV Quiescent Voltage on Pad 8 V Q8 - 1.2 - V Output Swing High 1 (Pad 8) V OH1 5 - - mV -5 - - mV ( Note 3) - 1 - Output Swing Low 1 (Pad 8) V OL 1 I IN = +1µA I CLIP = 0µA (Note 2 ) I IN = -1µA I CLIP = 0µA (Note 2 ) Output Clip Symmetry 1 V SYM 1 Output Swing High 2 (Pad 8) V OH 2 I IN = 5µA I CLIP = 1.875 x I R ( Note 2) - 50 - mV Output Swing Low 2 (Pad 8) V OL 2 I IN = -5µA I CLIP = 1.875 x I R ( Note 2) - -50 - mV Output Clip Symmetry 2 V SYM 2 ( Note 3) - 1 - Output Resistance (Pad 8) R OUT 8 I P8 = 10µA (S2 closed ) - 40 - kΩ Clipper Voltage Gain GAIN VIN = 50mV pp (S3-b ) I CLIP=1.875 x IR (Note 4) - 12 - dB All switches remain as shown in the Test Circuit unless otherwise stated in CONDITIONS column. NOTES: 1. IBIAS = (V7 – V7 ) / 1MΩ RF = 1MΩ 2. V OL 3. VSYM = (2VOH / ( VOH - VOL )) RF= 0Ω 4. GAIN = 20 log (V8 / V7) = V OH = V Q8 - V8 10 K 10µ b S3 VIN S2 S1 a IIN 9 26 I RF=10k 68n 68n 1.3 V P8 10n 10n 27 1 31 7 5 VCC 8 30 VCC 13 2k2 ROUT 3.3 VC AMP 12 CLIPPER 11 4 6 All resistors in ohms, all capacitors in farads unless otherwise stated ICLIP Fig. 13 Clipper Test Circuit 510 - 78 - 06 8 OUTPUT STAGE PARAMETER SYMBOL Quiescent Voltage on Pad 17 V17 Min Receiver Bias Voltage VREC MIN Max Receiver Bias Voltage MIN TYP MAX UNITS - 1.2 - V I BIAS = 0µA (Note 1) - 100 - mV VREC MAX I BIAS = IR x 1.875 (Note 1) - 300 - mV Input Resistance Pad 17 RIN17 I BIAS = IR - 40 - kΩ Internal Feedback Resistor RF I 10 = I R - 240 - kΩ Max Sinking Current (Pad 11) I SINK (S1 closed) - 10 - mA NOTE: 1. V REC= V cc - V11 CONDITIONS All switches remain as shown in the Test Circuit otherwise stated in the CONDITION column. 68n 10n 68n 9 I 10 10k +1.3 V 26 27 1 B IN 5 D IN B OUT 7 V CC 10n 30 10 31 RF V REG 13 S1 - 3µ3 OUTPUT + 2k2 11 D OUT V BIAS R IN 17 12 P GND 6 17 I BIAS GND All resistors in ohms, all capacitors in farads, unless otherwise stated. Fig. 14 Output Stage Test Circuit COMMENTS: 1. Pin 23 and Pin 4 represent virtual ground inputs. 2. If the length of the wires between the current sources and the GP520A is extensive, it may be necessary to connect an RC filter close to the appropriate GP520A pin for noise immunity. e.g. 100k 4 ICLIP 10µ GP520A All resistors in ohms, all capacitors in farads, unless otherwise stated. 9 510 - 78 - 06 V CC C4 C6 C5 C7 C8 C12 2n2 2n2 1n5 680p 68n 68n 10n 9 R 27 1 FULL WAVE RECTIFIER AVERAGING CIRCUIT 26 C11 10n 31 3 7 5 30 THRESHOLD R OUT 8 + LP 8 AGC FILTER - 50k VC AMP CLIPPER C10 R 14 22n 24 50k VC 68n V cc 29 MIC 22 VOLTAGE REGULATOR 28 C2 18 19 15 13 C1 + 3µ3 C9 C3 RIN14 + PREAMP - + HP FILTER - 2R RF 40k OUTPUT + R 10k LIN/LOG CONVERTER 12 6n8 10 6 21 20 LIN/LOG CONVERTER I REF LIN/LOG CONVERTER 2 25 16 11 VBIAS 4 23 17 V cc All resistors in ohms, all capacitors in farads unless otherwise stated. Fig. 15 Typical Application Circuit V CC 10k C6 1n5 15 18 19 22 C5 C7 C8 C12 C9 680p 68n 68n 10n 68n 24 R FULL WAVE RECTIFIER AVERAGING CIRCUIT 31 3 10n 7 5 30 THRESHOLD 8 VC AMP AGC FILTER CLIPPER C10 R 2n2 14 T 1 - 29 3u3 27 + LP 50k 1u 26 C11 50k VC V cc VOLTAGE REGULATOR 28 RIN14 MIC 2n2 C4 2n2 9 13 1k C1 C3 2n2 + PREAMP - 2R + HP FILTER - 10 R 40k OUTPUT + M R 2n2 10k LIN/LOG CONVERTER 12 6 20 LIN/LOG CONVERTER I REF LIN/LOG CONVERTER 21 16 25 2 11 VBIAS 23 4 17 All resistors in ohms, all capacitors in farads unless otherwise stated. Fig. 16 Typical Telecoil Application Circuit DOCUMENT IDENTIFICATION: DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. REVISION NOTES: Updated to Data sheet Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright September 1989 Gennum Corporation. All rights reserved. 510 - 78 - 06 6n8 F 10 Printed in Canada. V cc