NT6828 I2C Bus Controlled On-Screen Display Features I2C Bus Interface with Slave Address $7A (Receiver Only) Horizontal Frequency Range: 30KHz ~ 120KHz Flexible Display Resolution: up to 1524 dots per row Internal PLL Generating a Stable and Wide-Ranged System Clock (92.2 MHz) OSD Screen Comprising of Character Arrays of 15 Rows by 30 Columns 12 X 18 Dot Matrix Per Character Total of 256 Fonts Including 248 ROM Fonts and 8 RAM Fonts Programmable Vertical and Horizontal Position Adjustment for OSD Display Position 8-Color Selection for Each Character and 8-Color Control on Each Row with Overlapped by Windows Character Blinking, Shadowing & Bordering Display Effects Double Character Height and Width for Each Row Programmable Height of Characters Display Row To Row Spacing Control Four Overlapping and Programmable Windows with 8Color Control Hsync & Vsync Input Polarity Selectable 8 Channels PWM DAC with 8 bits resolution & OpenDrain Output Structure 16 DIP and 24 Skinny DIP packages General Description RAM fonts, variable character height with row-to-row spacing adjustment, 8 color selections for each character, double height/width controls for each row, four available overlapping windows with color & size controls, as well as other I/O interfaces to compliment an external video chipset. NT6828 is designed for displaying symbols and characters onto a CRT monitor. Its operation is controlled by the micro-controller with I2C bus interface. By sending the proper data and commands to NT6828, it can carry out the full screen display automatically while the time base is generated by the on-chip PLL circuit. There are many functions provided on this chip to fully support numerous user applications. These functions are: adjustment of OSD windows position, built-in ROM & NT6828 provides eight optional PWM channels with 8-bit resolution for external digital to analog control. Pin Configurations 24 Skinny DIP 16 DIP VCO 2 RP 3 4 AVCC HFLB N.C. SDA SCL 5 6 7 8 16 15 14 13 12 11 10 9 DGND R G B FBKG PWM/HFTON VFLB DVCC 1 AGND 1 24 DGND VCO 2 23 R RP 3 22 G AV DD 4 21 B HFLB 5 20 FBKG N.C. 6 PWM/HFTON SDA 7 19 18 SCL 8 17 DVCC PWM0 9 16 PWM7 PWM1 10 15 PWM6 PWM2 11 14 PWM5 PWM3 12 13 PWM4 NT6828K 1 NT6828 AGND VFLB V2.1 NT6828 Block Diagram SCL SDA I2 C BUS RECEIVER BUS CONTROL BUFFER ROM/RAM FONT 12 * 18 VERTICAL CONTROL DISPLAY MEMORY DISPLAY EFFECT VPOL HFLB HSYNC HPOL VCO PLL CIRCUIT TEST CIRCUIT CONTOL REG. TIMING GENERATOR COLOR CONTROL POWER ON LOW VOLTAGE RESET PWM Channel HORIZONTAL CONTROL POWER SYSTEM AVCC RP FBKG PWM / HFTON 2 DGND VSYNC DVCC AGND VFLB R/G/B OUTPUT CONTROL PWM0-7 NT6828 Pin Description Pin No. Designation I/O/P/R 1 AGND P Analog Ground 2 2 VCO - Voltage I/P to Control Oscillator 3 3 RP - Bias Resistor. (To be used as a bias internal VCO to resonate at the specific range of pixel clock) 4 4 AVCC P Analog Power Supply (5V Typ.) 5 5 HFLB I Horizontal Fly-back Input (Schmitt Trigger Buffer) 6 6 N.C. - - 7 7 SDA I SDA Pin Of I2C Bus (Schmitt Trigger Buffer) with internal 100K ohm pulled-high resistance 8 8 SCL I SCL Pin Of I2C Bus (Schmitt Trigger Buffer) with internal 100K ohm pulled-high resistance 9 PWM0 O 5V PWM Channel 0. Open-drain output structure 10 PWM1 O 5V PWM Channel 1. Open-drain output structure 11 PWM2 O 5V PWM Channel 2. Open-drain output structure 12 PWM3 O 5V PWM Channel 3. Open-drain output structure 12 PWM4 O 5V PWM Channel 4. Open-drain output structure 14 PWM5 O 5V PWM Channel 5. Open-drain output structure 15 PWM6 O 5V PWM Channel 6. Open-drain output structure 16 PWM7 O 5V PWM Channel 7. Open-drain output structure 9 17 DVCC P Digital Power Supply (5V Typ.) 10 18 VFLB I Vertical Fly-back Input (Schmitt Trigger Buffer) 11 19 PWM/ HFTON O PWM output or gain controlled of R,G,B channels. 12 20 FBKG O Fast Blanking Output. (To be used as switching signal for the R,G,B OSD video signals.) 13 21 B O Blue Color Output with Push-Pull Output Structure 14 22 G O Green Color Output with Push-Pull Output Structure 15 23 R O Red Color Output with Push-Pull Output Structure 16 24 DGND P Digital Ground 16 Pin 24 Pin 1 Description 3 NT6828 Functional Description 1. Memory Map 7 0 7 Fonts Address $00-$FF 0 Row Attribute Register 7 7 COLUMN 0 30 ROW ATTRIBUTE REGISTER 29 ROW 0 0 DISPLAY REGISTER 31 RESERVED 0 14 Memory Map of Display Register (Row 0 - 14) 7 0 Character Attribute Register 7 0 0 29 ROW 0 COLUMN CHARACTER ATTRIBUTE REGISTER 14 Memory Map of Attribute Register (Row 0 - 14) 4 NT6828 7 0 7 0 Window 1-4 Control Register PWM Control Register 7 7 ROW 0 0 15 7 WINDOW1 - WINDOW4 0 0 OSD SCREEN CONTROL 11 12 PWM CONTROL 18 19 26 COLUMN 7 0 OSD Screen Control Register Memory Map of Control Register (Row 15) 5 NT6828 2. List of Control Registers: (1) Display Register: Row 0 - 14, Column 0 - 29 7 Row 0-14 Column 0-29 6 5 4 3 2 1 MSB 0 LSB Fonts’ Address $00 - $FF Bit 7 - 0: In this eight bit address one of the 256 characters/symbols resided in the character ROM/RAM fonts. (Please refer to Figure 1.) Note that for 0 - 247 (ROM fonts) and 248 - 255 (RAM fonts) need to be programmed by the user. Each font consists of 12 x 18 dots matrix. (Please refer to Figure 2.) (2) Character Attribute Register: Row 0 - 14, Column 0 - 29 7 6 5 Row 0-14 Column 0-29 4 3 2 1 0 BLNK R G B Characters’ Attribute Control Bit 3: BLNK- This bit is to enable the blinking effect of the corresponding character/symbol as the bit is set to ‘1’. The blinking frequency is approximately 1Hz with 50/50 duty cycle at 80Hz vertical sync frequency. Bit 2 - 0: R/G/B-These three bits define the color attributes of the corresponding character/symbol. (Please refer to Table 1 for the color selections.) Table 1. Character/Windows Color Selection COLOR R G B Black 0 0 0 Blue 0 0 1 Green 0 1 0 Cyan 0 1 1 Red 1 0 0 Magenta 1 0 1 Yellow 1 1 0 White 1 1 1 6 NT6828 ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0A ) ( 0B ) ( 0C ) ( 0D ) ( 0E ) ( 0F ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1A ) ( 1B ) ( 1C ) ( 1D ) ( 1E ) ( 1F ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 2A ) ( 2B ) ( 2C ) ( 2D ) ( 2E ) ( 2F ) ROM Fonts .. . ( D0 ) ( D1 ) ( D2 ) ( D3 ) ( D4 ) ( D5 ) ( D6 ) ( D7 ) ( D8 ) ( D9 ) ( DA ) ( DB ) ( DC ) ( DD ) ( DE ) ( DF ) ( E0 ) ( E1 ) ( E2 ) ( E3 ) ( E4 ) ( E5 ) ( E6 ) ( E7 ) ( E8 ) ( E9 ) ( EA ) ( EB ) ( EC ) ( ED ) ( EE ) ( EF ) ( FE ) ( FF ) RAM Fonts ( F0 ) ( F1 ) ( F2 ) ( F3 ) ( F4 ) ( F5 ) ( F6 ) ( F7 ) ( F8 ) ( F9 ) ( FA ) Figure 1. Font Configuration 1 2 3 4 5 6 7 8 9 10 1112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 2. 12 x 18 Dots Matrix Font 7 ( FB ) ( FC ) ( FD ) NT6828 (3) Row Attribute Register: Row 0 - 14, Column 30 7 6 5 Row 0-14 Column 30 4 3 2 1 0 RW GW BW DBH DBW Rows’ Attribute Control Bit 4 - 2: RW/GW/BW- These three bits define the color attributes of the corresponding character/symbol at each row when overlapped by window and its control bit ROW cleared to ‘0’. (Please refer to Table 2 for the color selections.) Bit 1: DBH- This bit controls the height of the displayed character/symbol. When this bit is set, the character/symbol is displayed in double height. (Please refer to Figure 3.) Bit 0: DBW- This bit controls the width of the displayed character/symbol. When this bit is set, the character/symbol is displayed in double width. (Please refer to Figure 3.) Table 2. Character/Windows Color Selection COLOR RW GW BW Black 0 0 0 Blue 0 0 1 Green 0 1 0 Cyan 0 1 1 Red 1 0 0 Magenta 1 0 1 Yellow 1 1 0 White 1 1 1 8 NT6828 (4) Window 1 Registers: Row 15, Column 0 7 Row 15 Column 0 6 5 Row Start Address MSB 4 3 LSB MSB 2 1 Row End Address 0 LSB Window 1 Row Size Control Bit 7 - 4: These bits determine the row start position of window 1on the 15 x 30 OSD screen. (Please refer to Figure 4.) Bit 3 - 0: These bits determine the row end position of window 1on the 15 x 30 OSD screen. (Please refer to Figure 4.) 7 Row 15 Column 1 6 5 4 Column Start Address MSB 3 LSB 2 1 0 WINEN ROW_ Window1 Column Size Control & Attribute Control Bit 7 - 3: These bits determine the column start position of window 1on the 15 x 30 OSD screen. (Please refer to Figure 4.) Bit 2: WINEN- This bit enables the window 1 as it is set. Bit 1: ROW - This bit determines the row color attributes of the characters, which is overlapped by this window. Clear this bit to enable the row color attributes set by the control bit2~4 at the control registers at row 0 - 14, column 30. 7 Row 15 Column 2 6 5 4 Column End Address MSB 3 LSB 2 1 0 R G B Window1 Column Size Control & Attribute Control Bit 7 - 3: These bits determine the column end position of window 1on the 15 x 30 OSD screen. (Please refer to Figure 4.) Bit 2 - 0: R/G/B- These bits control the background color of window 1. Please refer to the Table for color selection. Note: Window 1 control registers occupy column 0 - 2 of row 15, Window 2 from column 3 - 5, Window 3 from 6 - 8 and Window 4 from 9 - 11. The function of Window 2 - 4 control registers is the same as Window 1. Window 1 has the highest priority, whereas Window 4, the least whereas window with higher priority will overlap window with lower if their display area have overlapped. The higher priority color will take occupy the overlapping window area. If the start address of the row/column is greater than the end address then this window will not be displayed. Set out of 15 Row & 30 Column OSD display range , the abnormal OSD screen will be displayed. 9 NT6828 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 10 10 11 11 11 12 12 12 13 13 13 14 14 14 15 15 15 16 16 16 17 17 17 18 18 18 2 3 4 5 6 7 8 19 Normal 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Double Width 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Double Height Figure 3. Double Height & Width Effect Row Start Address 30 Column Start Address Column End Address WINDOW1/2/3/4 AREA Row End Address 15 Row Start/End Control Register: row15 /column 0/3/6/9 Column Start Control Register: row15 /column 1/4/7/10 Column End Control Register: row15 /column 2/5/8/11 Window Color Control Register: row15 /column 2/5/8/11 Figure 4. Windows’ Size Setting 10 NT6828 (5) OSD Screen Position Control Registers: Row 15, Column 12 - 13 7 Row 15 Column 12 6 5 4 3 2 1 0 VPOS MSB LSB Vertical Position Adjustment Bit 7 - 0: VPOS - These bits determine the vertical starting position for the OSD screen display. It is the vertical delay starting from the leading edge of VFLB. The unit of this setting is 4 horizontal lines. The equation is defined as: Vertical delay = (Vpos x 4 +1) x Horizontal Line The default value of it is 4 ($04) after power on. Please refer Figure 5. 7 Row 15 Column 13 6 5 4 3 2 1 0 HPOS MSB LSB Horizontal Position Adjustment Bit 7 - 0: HPOS- These bits determine the horizontal starting position for the OSD screen display. It is the horizontal delay starting from the leading edge of HFLB. The unit of this setting is a 6-dot movement shift to the right on the monitor screen. The equation is defined as: Horizontal delay = (Hpos x 6 + 49) / P.R. Where the P.R. (pixel rate) is defined by the HDR & Horizontal Frequency. P.R. (Pixel Rate) = HDR * 12 * FreqHFLB Please refer to the HDR control register at row15 / column15 for the P.R. setting. After power-on, the default value of these bits is 15 ($ 0F). (Please refer to Figure 5.) 11 NT6828 T HFLB HFLB VPOS *4 + 1 lines VFLB HPOS *6 + 49 dots T Raster 30 ( 30*12 =360 Dots ) u OSD Screen VFLB 15 Figure 5. OSD Screen Position Note: The figure above illustrates the positions adjustment of all displayed characters on the screen relative to the leading edge of horizontal and vertical fly-back signals. 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Normal Shadowing Bordering Figure 6. Shadowing & Bordering Effects 12 NT6828 (6) Character Height Control: Row 15, Column 14 7 Row 15 Column 14 6 5 4 3 2 1 0 CRH6 CRH5 CRH4 CRH3 CRH2 CRH1 CRH0 Characters’ Height Control Bit 6 - 0: CRH6-CRH0- These bits determine the displayed characters’ height. The characters, originally 12 x 18 font matrix, can be expanded from 18 to 71 lines. (Please refer to Table 3 & 4 below.) Table 3. Lines Expanded Control CRH6 - CRH0 Lines Inserted CRH6 = ‘ 1 ‘ , CRH5 = ‘ 1 ‘ All 18 lines repeat three times CRH6 = ‘ 1 ‘ , CRH5 = ‘ 0 ‘ All 18 lines repeat twice CRH6 = ‘ 0 ‘ , CRH5 = ‘ X ‘ All 18 lines repeat once CRH4 = ‘ 1 ‘ Insert 16 lines CRH3 = ‘ 1 ‘ Insert 8 lines CRH2 = ‘ 1 ‘ Insert 4 lines CRH1 = ‘ 1 ‘ Insert 2 lines CRH0 = ‘ 1 ‘ Insert 1 lines Table 4. Lines Expanded Position Repeat Position No. of Lines Inserted 1 2 3 4 5 6 7 8 Insert 1 lines 9 10 11 12 13 14 15 16 17 ! Insert 2 lines ! Insert 4 lines ! ! ! ! ! Insert 8 lines ! Insert 16 lines ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Insert 17 lines ! ! ! ! ! ! ! Note: Please refer to Table 5, where there are listed examples for this line expanded algorithm. 13 ! 18 NT6828 Table 5. Line Expanded Example Example 1: set CRH0 = 1, CRH2 = 1, CRH3 = 1 Line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Original Font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! CRH0 ! CRH2 ! CRH3 Result : 31 lines 18+ 8*CRH3+4*CRH2 +CRH0 ! ! !! ! ! !! !! ! ! ! ! ! ! ! ! ! !! !! !! !! !! !! !! ! !! !! !! ! ! Example 2: set CRH0 = 1, CRH 3 = 1, CRH4 = 1 Line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Original Font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! CRH0 ! CRH3 ! CRH4 ! Line >= 18 ! Result : 45 lines 18+( 18 * CRH4) + (8*CRH3)+(CRH0) !! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !!! !! !!! !! !!! !! 14 !!! !!! !!! !! !!! !! !!! !! !!! !! !! NT6828 (7) Flexible Display Control Register: Row 15, Column 15 7 6 5 4 3 2 1 0 HDR Row 15 Column 15 MSB LSB Horizontal Display Resolution Control Bit 6 - 0: HDR- These bits determine the resolution of horizontal display line. The unit of this setting is 12 dots (1 character). With a total of 92, the user can adjust the resolution from 36 to 127 characters on each horizontal line steps ($24 - $7F: 36 - 127 steps; note that its value can not be smaller than 36 at any given time.) Also make a special note that the resolution adjustment must be joined together with the VCO setting at row15 / column18 control register. The default value is 40 after power-on. (Please refer to the Table showing the control register at row15 / column18.) (8) OSD Row to Row Space Control Register: Row 15, Column 16 7 6 5 4 Row 15 Column 16 3 2 1 R2RSPACE MSB 0 LSB Row To Row Space Adjustment Bit 4 - 0: R2RSPACE- These bits define the row to row spacing in unit of horizontal line. It means extra lines, defined by this 5-bit value, will be appended for each display row. The default value of it is 0 after power-on and there is no any extra line inserted between each row. (9) Input/Output Control Register: Row 15, Column 17 7 Row 15 Column 17 6 OSDEN BSEN 5 4 SHADOW RGBF 3 2 1 0 BLANK CLRWIN CLRDSPR FBKGC OSD Screen Control 1 Bit 7: OSDEN- This bit will enable the OSD circuit as it is set to ‘1’. The default value is ‘0’ after power-on. Bit 6: BSEN- This bit will enable the bordering and shadowing effect as it is set to ‘1’. The default value of this bit is ‘0’ after power-on. Bit 5: SHADOW- When the BSEN is set to ‘1’, it will enable the shadowing effect as this bit set to ‘1’. Otherwise, it will enable the bordering effect as this bit cleared to ‘0’. The default value is ‘0’ after power-on. (Please refer to Figure 6) Bit 4: RGBF- This bit controls the driving state of the output pins, R, G, B and FBKG when the OSD is disabled. After power-on, this bit is cleared to ‘0’ and all of the R, G, B and FBKG pins output at high impedance state while the OSD being disabled. If this bit is set to ‘1’, these R, G, B pins will drive low while OSD is being disabled, but the FBKG pins will output ‘0’ if the FBKGP bit is set to ‘1’, whereas output ‘1’, set to ‘0’. Bit 3: BLANK- This bit will force the FBKG pin to output high as it is set to ‘1’. The default value of this bit is ‘0’ after power-on. Bit 2: CLRWIN- This bit will clear all of windows’ WINEN control bit as it is set to ‘1’. The default value of this bit is ‘0’ after power-on. Bit 1: CLRDSPR- This bit will clear all of the contents in the display registers as it is set to ‘1’. The default value of this bit is ‘0’ after power-on. Bit 0: FBKGC This bit determines the configuration of FBKG output pin. When it is cleared, the FBKG pin will output high while displaying characters or windows. Otherwise, it will output high only while displaying characters. The default value is ‘0’ after power-on. Please refer to Figure 7 for the FBKG O/P timing. 15 NT6828 (10) Row 15, Column 18: 7 6 Row 15 Column 18 5 4 3 2 1 0 FBKGOP PWMCTRL DBOUNCE HPOL VPOL VCO1 VCO0 OSD Screen Control 2 Bit 6: FBKGOP- This bit selects the polarity of the output signal of FBKG pin. This signal is active low when the user clears this bit. Otherwise, active high set this bits. The default value is ‘1’ after power-on. Please refer to Figure 7 for the FBKGOP control timing. Bit 5: PWMCTRL- This bit selects the output option to PWM/HFTON pin. This bit will enable the PWM output as it is set to ‘1’. Otherwise, it will select the HFTON option. The default value is ‘0’ after power-on. Please refer to Figure 7 for the HFTON O/P timing and refer to Figure 8 PWMCLK O/P timing. Bit 4: DBOUNCE- This bit activates the debounce circuit of horizontal and vertical scan. It prevents from the OSD screen shaking when the user adjusts the horizontal phase or vertical position. This bit is cleared after power-on. Bit 3: HPOL- This bit selects the polarity of the input signal of horizontal sync (HFLB pin). If the input sync signal has negative polarity, the user must clear this bit. Otherwise, set this bit to ‘1’ to accept a positive polarity signal. After power-on, this bit is cleared to ‘0’ and it will accept a negative polarity sync signal. Bit 2: VPOL- This bit selects the polarity of the input signal of vertical sync (VFLB pin). If the input sync signal is negative polarity, the user must clear this bit. Otherwise, set this bit to ‘1’ to accept the positive polarity signal. After poweron, this bit is cleared to ‘0’ and it will accept a negative polarity sync signal. Bit 1 - 0: VCO1/0- These bits select the VCO frequency range when the user sets the horizontal display resolution flexibly. It is related to the horizontal display resolution and the user must set the control register at row15 / column15 properly. The default value is VCO1 = 0 & VCO0 = 0 after power-on state. The relationship between VCO1/0 and display resolution is listed as follows: P.R. (Pixel Rate) = HDR * 12 * FreqHFLB Table 6. VCO Section & Freq. Limitation Section VCO1 VCO0 VCO Freq. Min VCO Freq. Max Freq1 0 0 6 12 Freq2 0 1 12 24 Freq3 1 0 24 48 Freq4 1 1 48 92.2 Unit P.R. Limit HFLB Freq. Limit MHz Min < P.R. < Max ( Min / HDR*12 ) < FreqHFLB < Max / ( HDR*12 ) If there are no signals at HFLB input, the PLL will generate an approximate 1.8 MHz clock to ensure the proper operation of the I2C bus and other control registers. 16 NT6828 FBKG HFTON Scan Line Window Background Chacracter Shadowing FBKGOP bit = ‘1’ FBKGC bit = ‘0’ Window Background FBKGOP bit = ‘1’ FBKGC bit = ‘1’ Figure 7. FBKG and HFTON Output Waveform under FBKGOP and FBKGC Bits Controlled 17 NT6828 (11) PWM Channels Control Registers: Row 15, Column 19 - 26 7 Row 15 Column 19-26 6 5 4 3 2 1 MSB 0 LSB PWM Channel Control Bit 7 - 0: These bits determine the output duty cycle and waveforms of PWM. When these bits are set to 00H, the DAC will output LOW (GND level). After power-on, all of PWM will output low ($00). Table 7. PWM Clock & Pixel Clock Relationship Section VCO1 VCO0 VCO Freq. Min VCO Freq. Max Freq1 0 0 6 12 Freq2 0 1 12 24 Unit PWM CLK PWM Refresh Rate Freq1 Freq1 / 256 Freq2/2 Freq2 / 2 / 256 MHz Freq3 1 0 24 48 Freq3/4 Freq3 / 4 / 256 Freq4 1 1 48 92.2 Freq4 /8 Freq4 / 8 / 256 Note: Each of PWM channel will be separated by half of PWM clock. (Each has an 8-bit resolution.) 2 3 M-1 M M+1 255 0 .. . PWMCLK 1 .. . 0 PWM0 PWM1 .. . PWM6 PWM7 Figure 8. PWMCLK and PWM O/P timing 18 1 2 3 NT6828 3. I2C Bus Communication: The relative figure shows the I2C Bus transmission format. The master initiates a transmission routine by generating a START condition, followed by a slave address byte. Once the address is properly identified, the slave will respond with an ACKNOWLEDGE signal by pulling the SDA line LOW during the ninth SCL clock. Each data byte which then follows must be eight bits long, plus the ACKNOWLEDGE bit, which makes up nine bits all together. Appropriate row and column address information and display data can be downloaded sequentially in one of the three transmission formats described in Figure “Access Register Operation”. In the cases of no ACKNOWLEDGE or completion of data transfer, the master will generate a STOP condition to terminate the transmission routine. Note that the OSD_EN bit must be set after all the display information has been sent in order to activate the displaying circuitry of NT6828, so that the received information can then be displayed. (1) Access the Display Control Registers: After proper identification by the receiving device, the data train of arbitrary length is transmitted from the master. There are three transmission formats from (a) to (c) as referred to Figure 9 & Table 8. The data train in each sequence consists of row addresses, column addresses, and data. In format (a), data must be preceded with the corresponding row address and column address. This format is particularly suitable for updating small amounts of data between different rows. However, if the current information byte has the same row address as the one before, format (b) is recommended. For a full screen pattern change (which requires a massive information update), or during a power-on situation, most of the row and column addresses on either (a) or (b) format will appear to be redundant. A more efficient data transmission format (c) should be applied. This sends the starting row and column addresses once only, and then treats all subsequent data as display information. The row and column addresses will be automatically incremented internally for each display information data from the starting location. To differentiate the row and column addresses when transferring data from master, the MSB (Most Significant Bit) is set as in Table Transmission: ‘1’ represents row, while ‘0’ represents column address. Furthermore, to distinguish the column address between format (a), (b) and (c); the sixth bit of the column address is set to ‘1’, which represents format (c), and a ‘0’ for format (a) or (b). There is some limitation when using mix-formats during a single transmission. It is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). (2) Access the RAM Fonts Area: There are some differences when accessing the RAM font. One font consists of 18 rows and 12 columns of dot matrix. At each row of one font, there are 18 bits of data which allocates 2 bytes of control data with 4 unavailable bits. Thus, each font occupies 36 bytes of control data. From the memory map of RAM fonts, font0 is allocated at row 0 & column 0 - 35, and font1, row 1 & column 0 ~ 35, etc. (Please refer to Figure 9.) Table 8. Address Data Transmission for Registers ITEM Display Register Attribute / Control Register RAM Fonts No ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 Type 1 Row 1 0 0 X D D D D (a), (b), (c) 2 Column 0 0 X D D D D D (a), (b) 3 Column 0 1 X D D D D D (c) 4 Row 1 0 1 X D D D D (a), (b), (c) 5 Column 0 0 X D D D D D (a), (b) 6 Column 0 1 X D D D D D (c) 7 Row 1 1 X X X D D D (a), (b), (c) 8 Column 0 0 D D D D D D (a), (b) 9 Column 0 1 D D D D D D (c) 19 NT6828 --------------- Repeat -------------- Type (a) (1) (2) (3) (4) (5) (3) (4) (5) START OSD Slave Row Address Column Address Information Row Address Column Address Information Condition Address ‘$7A’ Data Data Data Data Data Data 8 bits 8 bits 8 bits 8 bits (2) (3) (4) (5) 8 bits 8 bits 8 bits ------ Repeat ----- Type (b) (1) (4) (5) (6) START OSD Slave Row Address Column Address Information Column Address Information Condition Address ‘$7A’ Data Data Data Data Data 8 bits 8 bits 8 bits 8 bits 8 bits … STOP Condition 8 bits Repeat Type (c) (1) (2) (3) (4) (5) START OSD Slave Row Address Column Address Information Condition Address ‘$7A’ Data Data Data 8 bits 8 bits 8 bits 8 bits (5) (5) Information Data Information Data 8 bits 8 bits Figure 9. Access Register Operation RAM FONT 0 row0 1 row1 2 row2 3 row3 4 row4 5 row5 6 row6 Column Address 1 2 3 4 5 6 7 8 9 10 1112 0&1 2&3 4&5 6&7 8&9 10&11 12&13 14&15 16&17 18&19 20&21 22&23 24&25 26&27 28&29 30&31 32&33 34&35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 10. RAM Font Access 20 7 row7 (6) … STOP Condition (6) … STOP Condition NT6828 4. OSD Display Format: OSD Screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0 1 2 3 Double Height 4 5 6 7 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 8 9 10 11 12 13 14 15 Line Expanded = 22 lines & Double Width Line Expanded = 22 lines & Double Height Figure 11. OSD Display Format Figure 12-1. Font Code Example NT682800013 21 Double Width NT6828 Figure 12-1. Font Code Example 682800013 (continued) Figure 12-2. Font Code Example NT682800012 22 NT6828 Figure 12-2. Font Code Example NT682800012 (continued) 23 NT6828 Absolute Maximum Rating* *Comments Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Supply Voltage . . . . . . . . . . . . . . . -0.3V to +7.0V VCC (measured to GND) . . . . . . . . . . . 4.75V to 5.25V Operating Temperature . . . . . . . . . . .0 to +70 0 C Electrical Characteristics (VCC = 5V, Tamb = 25qC) Symbol VCC Parameters Min. Typ. Max. Unit 4.75 5 5.25 V Typ. Max. Unit 22 25 mA Supply Voltage Conditions DC Electrical Characteristics Symbol Parameter IDD Operating Current VIH1 Input High Voltage VIL1 Input Low Voltage VIH2 IIC Bus Input High Voltage VIL2 IIC Bus Input Low Voltage Min. 2 0.8 3 1.5 VFLB, HFLB with Schmitt Trigger Buffer V VFLB, HFLB Schmitt Trigger Buffer V SCL, SDA V Driving current of R, G, B, FBKG, HFTON output pins at 2.4V output voltage 80 mA Isink1 Sinking current of R, G, B, FBKG, HFTON output pins at 0.4V output voltage 20 mA Isink2 Sinking current of PWM output pins at 0.4V output voltage 4 mA Ileak Leakage current of R, G, B, FBKG pins at Hi-Z state Iiicl IIC Bus Output Sink Current Vth Input Threshold Voltage at HFLB & VFLB pin 5 1.8 VSTIH Schmitt Trigger Input High Voltage VSTIL Schmitt Trigger Input Low Voltage 0.8 Input Current of Hsync, Vsync, SDA, SCL pins -10 Iin 24 uA Output Floating State & Measured at 2.5V mA Viicoutl = 0.4 V 2.0 2.2 V 1.7 2 V 1.1 No loading V Idrive1 10 Condition V +10 uA Schmitt Trigger Buffer NT6828 Output state VH Input voltage VL 1.1V 1.7V Figure 13. Schmitt Trigger Diagram 25 NT6828 AC Characteristics Symbol Parameters Fhfy Horizontal Fly-back Frequency Vhfly Horizontal Fly-back Input Min. 30 Thflymin Minimum Pulse Width of Horizontal Flyback Thflymax Maximum Pulse Width of Horizontal Flyback Fvfy Vertical Fly-back Frequency Vvfly Vertical Fly-back Input Typ. Minimum Pulse Width of Vertical Fly-back Tvflymax Maximum Pulse Width of Vertical Fly-back Unit 120 KHz 5 V 0 V 0.7 us 50 Tvflymin Max. 5.5 us 200 Hz 5 V 0 V 20 us 1 ms 5V 2.0 V HFLB 0V Thwidth 5V 2.0 V VFLB 0V Tvwidth Figure 14. H/V Fly-Back Signal 26 Conditions NT6828 I2C Bus – Slave Receiver (Slave address: $7A) Symbol Fmaxcl Parameters Min. Typ. Max. Unit 100 KHz Maximum SCL Clock Frequency VIL Input Low Voltage -0.5 1.5 V VIH Input High Voltage 3.0 5.5 V Tlow Low Period of the SCL Clock 4.7 us Thigh High Period of the SCL Clock 4.0 us Tsudat Data Setup Time 250 ns Thddat Data Hold Time 300 ns Tiicr Rise Time of IIC Bus 1000 ns Tiicf Fall Time of IIC Bus 300 ns Tsusta Setup Time Condition Thdsta 1.3 us Hold Time for START Condition 4.0 us Tsusta Set-up Time for START Condition 4.7 us Tsusto Set-up Time for STOP Condition 4.0 us Tiicbuf The time that the IIC bus must be free before next new transmission can start 4.7 us Iiicl Tfilter for Repeated START IIC Bus Sink Current 4 5 Input filter spike suppression 100 Conditions SCL,SDA mA Viicoutl = 0.4 V ns SCL,SDA Note: Please refer to I2C Table Control and I2C Sub Address Control. SDA Tiicbuf Tlow Tiicr Tiicf Thdsta SCL Thdsta Thddat Tsudat Tsusta Tsusto Thigh STOP START START 27 STOP NT6828 Application Circuit 1M 0. 01uf 5. 6K 12K 0. 01uf 5. 6K VC C 0. 1u H F LB 220u 100 1 2 3 4 5 6 7 8 9 10 11 12 AG N D D GND VC O R RP G AVC C B H F LB F BKG NC PW M/H F TON SD A VF LB SC L D VC C PW M0 PW M7 PW M1 PW M6 PW M2 PW M5 PW M3 PW M4 24 23 22 21 20 19 18 17 16 15 14 13 100P 100P 100P 100P R OUT GOUT BO U T F BKG H F TO N 470 470 470 470 100 220 VF LB 100P VC C 100P 0. 1u N T6828 220u 100 SD A 100 SC L VC C 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 4. 7K 47K PW M 0 47K PW M 1 47K PW M 2 47K PW M 3 47K PW M 4 47K PW M 5 47K PW M 6 47K PW M 7 1uf 1uf 1uf 1uf 1uf 1uf 28 1uf 1uf NT6828 Ordering Information Part No. Packages NT6828 16 DIP NT6828K 24 Skinny DIP 29 NT6828 Package Information P-DIP 16L Outline Dimensions unit: inches/mm D 16 E1 9 1 8 E A1 A2 Base Plane Seating Plane L A C S B é e1 B1 Symbol A A1 A2 B B1 C D E E1 e1 L é eA S eA Dimension in inch Dimension in mm 0.175 Max. 4.45 Max. 0.010 Min. 0.25 Min. 0.130±0.010 3.30±0.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.060 +0.004 1.52 +0.10 -0.002 -0.05 0.010 +0.004 0.25 +0.10 -0.002 -0.05 0.750 Typ. (0.770 Max.) 19.05 Typ. (19.56 Max.) 0.300±0.010 7.62±0.25 0.250 Typ. (0.262 Max.) 6.35 Typ. (6.65 Max.) 0.100±0.010 2.54±0.25 0.130±0.010 3.30±0.25 0°~ 15° 0°~ 15° 0.345±0.035 0.040 Max. 8.76±0.89 1.02 Max. Note: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash. 30 NT6828 Package Information Skinny-DIP 24L Outline Dimensions unit: inches/mm D 13 E1 24 1 12 E A1 A2 Base Plane Seating Plane L A C S B e1 D B1 Symbol A A1 A2 B B1 C D E E1 e1 L é eA S eA Dimension in inch Dimension in mm 0.175 Max. 4.45 Max. 0.010 Min. 0.25 Min. 0.130±0.010 3.30±0.25 0.018 +0.004 0.46 +0.10 -0.002 -0.05 0.060 +0.004 1.52 +0.10 -0.002 -0.05 0.010 +0.004 0.25 +0.10 -0.002 -0.05 0.750 Typ. (0.770 Max.) 19.05 Typ. (19.56 Max.) 0.300±0.010 7.62±0.25 0.250 Typ. (0.262 Max.) 6.35 Typ. (6.65 Max.) 0.100±0.010 2.54±0.25 0.130±0.010 3.30±0.25 0°~ 15° 0°~ 15° 0.345±0.035 0.040 Max. 8.76±0.89 1.02 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash. 31