TI SN74HC7002DR

SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS033E – MARCH 1984 – REVISED JULY 2003
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to
6V
Typical tpd = 14 ns
Low Power Consumption, 20-µA Max
ICC
Low Input Current of 1 µA Max
Operation From Very Slow Input
Transitions
Temperature-Compensated Threshold
Levels
High Noise Immunity
SN54HC7002 . . . J OR W PACKAGE
SN74HC7002 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
SN54HC7002 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
4B
description/ordering information
In these devices, each circuit functions as a
quadruple NOR gate. They perform the Boolean
function Y = A • B or Y = A + B in positive logic.
However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
1Y
NC
2A
NC
2B
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
4
NC – No internal connection
ORDERING INFORMATION
PDIP – N
SN74HC7002N
Tube of 50
SN74HC7002D
Reel of 2500
SN74HC7002DR
Reel of 250
SN74HC7002DT
Reel of 2000
SN74HC7002NSR
Tube of 90
SN74HC7002PW
Reel of 2000
SN74HC7002PWR
Reel of 250
SN74HC7002PWT
CDIP – J
Tube of 25
SNJ54HC7002J
SNJ54HC7002J
CFP – W
Tube of 150
SNJ54HC7002W
SNJ54HC7002W
LCCC - FK
Tube of 55
SNJ54HC7002FK
SOP – NS
TSSOP – PW
–55°C
125°C
–55 C to 125
C
TOP-SIDE
MARKING
Tube of 25
SOIC – D
85°C
C
–40°C
–40
C to 85
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74HC7002N
HC7002
HC7002
HC7002
SNJ54HC7002FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS033E – MARCH 1984 – REVISED JULY 2003
FUNCTION TABLE
(each gate)
INPUTS
A
OUTPUT
Y
B
H
X
L
X
H
L
L
L
H
logic diagram (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7002
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
Low-level input voltage
SN74HC7002
MIN
NOM
MAX
MIN
NOM
MAX
2
5
6
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 4.5 V
VCC = 6 V
Input voltage
0
Output voltage
0
0.5
0.5
1.35
1.8
1.8
0
0
V
V
1.35
VCC
VCC
UNIT
VCC
VCC
V
V
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS033E – MARCH 1984 – REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
VT–
VT+ – VT–
MAX
SN74HC7002
MIN
MAX
2V
0.7
1.2
1.5
0.7
1.5
0.7
1.5
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.1
3.3
4.2
2.1
4.2
2.1
4.2
2V
0.3
0.6
1
0.3
1
0.3
1
4.5 V
0.9
1.6
2.45
0.9
2.45
0.9
2.45
6V
1.2
2
3.2
1.2
3.2
1.2
3.2
2V
0.2
0.6
1.2
0.2
1.2
0.2
1.2
4.5 V
0.4
0.9
2.1
0.4
2.1
0.4
2.1
6V
0.5
1.3
2.5
0.5
2.5
0.5
2.5
UNIT
V
V
V
1.998
1.9
1.9
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = –4 mA
IOH = –5.2 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
A
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
3
10
10
10
pF
IOL = 4 mA
IOL = 5.2 mA
VI = VCC or 0
VI = VCC or 0,
MIN
1.9
VI = VIH or VIL
II
ICC
SN54HC7002
2V
VI = VIH or VIL
VOL
TA = 25°C
TYP
MAX
4.5 V
IOH = –20 µA
A
VOH
MIN
IO = 0
6V
Ci
2 V to 6 V
V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC7002
SN74HC7002
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
60
130
195
163
tpd
A or B
Y
4.5 V
18
26
39
33
6V
14
22
33
28
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
tt
Any
MIN
MIN
MAX
MIN
MAX
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
TYP
20
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54HC7002, SN74HC7002
QUADRUPLE POSITIVE-NOR GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS033E – MARCH 1984 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
1.060
(26,92)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
MS-100
VARIATION
AA
BB
AC
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
C
AD
8
0.070 (1,78)
0.045 (1,14)
0.045 (1,14)
0.030 (0,76)
D
D
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
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1
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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