SCLS553 − JANUARY 2004 D Qualification in Accordance With D D D D D D D D D D Temperature-Compensated Threshold AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Operation From Very Slow Input Transitions Levels High Noise Immunity Same Pinouts as ’HC00 D D D OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y † Contact factory for details. Q100 qualification data available on request. description/ordering information Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. The SN74HC132 performs the Boolean function Y = A • B or Y = A + B in positive logic. This circuit is temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. ORDERING INFORMATION −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Reel of 2500 SN74HC132QDRQ1 TSSOP − PW Reel of 2000 SN74HC132QPWRQ1 HC132Q1 HC132Q1 ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004 Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS553 − JANUARY 2004 logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN VCC Supply voltage VIH High-level input voltage 2 VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO MAX 5 6 UNIT V 1.5 3.15 V 4.2 0.5 VCC = 4.5 V VCC = 6 V Low-level input voltage NOM 1.35 V 1.8 Input voltage 0 Output voltage 0 VCC VCC V V TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS553 − JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ VT− 2V 0.7 1.2 1.5 0.7 1.5 4.5 V 1.55 2.5 3.15 1.55 3.15 6V 2.1 3.3 4.2 2.1 4.2 2V 0.3 0.6 1 0.3 1 4.5 V 0.9 1.6 2.45 0.9 2.45 6V 1.2 2 3.2 1.2 3.2 UNIT V V 0.6 1.2 0.2 1.2 0.4 0.9 2.1 0.4 2.1 6V 0.5 1.3 2.5 0.5 2.5 2V 1.9 1.998 1.9 IOH = −20 µA 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 IOH = −4 mA IOH = −5.2 mA 4.5 V 3.98 4.3 3.7 6V 5.48 5.8 5.2 2V 0.002 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V ±0.1 ±100 ±1000 nA 2 40 µA 10 10 pF IOL = 4 mA IOL = 5.2 mA VI = VCC or 0 VI = VCC or 0, MAX 0.2 VI = VIH or VIL II ICC MIN 2V VI = VIH or VIL VOL TA = 25°C TYP MAX 4.5 V VT+ − VT− VOH MIN IO = 0 6V Ci 2 V to 6 V 3 V V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C MIN TYP MAX PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 60 120 186 tpd A or B Y 4.5 V 18 25 37 6V 14 21 32 2V 28 75 110 4.5 V 8 15 22 6V 6 13 19 tt Any MIN MAX UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 20 UNIT pF 3 SCLS553 − JANUARY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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