TI TWL6030B107CMR

TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Fully Integrated Power Management with Switch Mode Charger
Check for Samples: TWL6030
FEATURES
1
•
23
•
•
•
•
•
•
•
•
•
•
Seven highly efficient 6-MHz buck converters
– Two 0.6 to 2.1 V @ 1.6 A
– Five 0.6 to 2.1 V @ 1.0 A
11 General-purpose LDOs
– Six 1.0 to 3.3 V @ 0.2 A with battery or
preregulated supply (One can be used as a
vibrator driver.)
– One 1.0 to 3.3 V @ 50 mA with battery or
preregulated supply
– One low noise 1.0 to 3.3 V @ 50 mA with
battery or preregulated supply
– 3.3 V @ 35 mA USB LDO
– One LDO for TWL6030 internal use
– One LDO for internal and external use
USB OTG module
Backup battery charger
10-bit ADC with 17 input channels
13-bit Coulomb counter with four
programmable integration periods
Low power consumption
– 5 µA in backup mode
– 20 µA in wait-on mode
– 110 µA in deep sleep, with two DCDCs
active
RTC with alarm wake-up mechanism
SIM and MMC card detections
Two digital PWM outputs
Thermal monitoring
– High-temperature warning
– Thermal shutdown
•
•
•
•
Control
– Configurable power-up and power-down
sequences (EPROM programmable)
– Three output signals that can be included
in the start-up sequence
– Two I2C™ interfaces
– All resources configurable by I2C
Clock management
32-kHz output
Battery charger 1.5 A
– Charger for single-cell Li-Ion and
Li-Polymer battery packs
– Switched mode charger with integrated
power FET for up to 1.5-A current
– High-accuracy voltage and current
regulation
– Safety timer and reset control
– Thermal regulation protection
– Input/output overvoltage protection
– Charging indicator LED driver
– Boost mode operation for USB OTG
– Compliant with:
– USB 2.0
– OTG and EH 2.0
– YD/T 1591-2006
– USB battery charging 1.1 and 1.2
– Japanese battery charging requirements
Package 7 mm x 7 mm 187-pin nFBGA
APPLICATIONS
•
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Mobile phones and smart phones
Gaming handsets
Portable media players
Portable navigation systems
Handheld devices
Tablets
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartReflex is a trademark of Texas Instruments.
MIPI is a registered trademark of Mobil Industry Processor Interface.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
DESCRIPTION
The TWL6030 device is an integrated power-management integrated circuit (IC) for applications powered by a
rechargeable battery. The device provides seven configurable step-down converters with up to 1.6A capability for
memory, processor core, I/O, auxiliary, preregulation for LDOs, etc. The device also contains 11 LDO regulators
that can be supplied from a battery or a preregulated supply. Power-up/power-down controller is configurable
and can support any power-up/power-down sequences (EPROM based). The real-time clock (RTC) provides a
32-kHz output buffer, second/minute/hour/day/month/year information, and alarm wake up. The TWL6030
supports 32-kHz clock generation based on a crystal oscillator. The device integrates a switched-mode charger
allowing faster battery charge, higher efficiency, and less power dissipation.
The TWL6030 device generates power supplies for OMAP™ 4 processors and operates together with the
TWL6040 device, which includes all audio and related detection features. For audio IC parameters, see the
TWL6040 datasheet. In addition, the TWL6030 device can be used as a power management multichannel IC
(PMIC) for several other processors, thanks to the programmable startup/shutdown controller and default supply
voltage levels. The TWL6030 is available in an nFBGA package, 7.0 mm x 7.0 mm, with a 0.4-mm ball pitch.
Figure 1 shows the TWL6030 block diagram.
2
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 1. Ordering Information
PART NUMBER
ORDERING
OMAP VERSION
PRIMARY
WATCHDOG
HW CHARGER
WATCHDOG
TRANSPORT MEDIA
QUANTITY
TWL6030
TWL6030B107CMRR
OMAP4430
Disabled
Disabled
Tape and reel, 2500
TWL6030
TWL6030B107CMR
OMAP4430
Disabled
Disabled
Trays, 260
TWL6030
(P)TWL6030B1AECMRR
OMAP4430
Disabled
Enabled
Tape and reel, 2500
TWL6030
(P)TWL6030B1AECMR
OMAP4430
Disabled
Enabled
Trays, 260
TWL6030
(P)TWL6030B1A0CMRR
OMAP4430
Enabled
Enabled
Tape and reel, 2500
TWL6030
(P)TWL6030B1A0CMR
OMAP4430
Enabled
Enabled
Trays, 260
TWL6030
(P)TWL6030B1A4CMRR
OMAP4460/4470
Disabled
Disabled
Tape and reel, 2500
TWL6030
(P)TWL6030B1A4CMR
OMAP4460/4470
Disabled
Disabled
Trays, 260
TWL6030
(P)TWL6030B1AFCMRR
OMAP4460/4470
Disabled
Enabled
Tape and reel, 2500
TWL6030
(P)TWL6030B1AFCMR
OMAP4460/4470
Disabled
Enabled
Trays, 260
TWL6030
(P)TWL6030B1AACMRR
OMAP4460/4470
Enabled
Enabled
Tape and reel, 2500
TWL6030
(P)TWL6030B1AACMR
OMAP4460/4470
Enabled
Enabled
Trays, 260
Copyright © 2010–2011, Texas Instruments Incorporated
3
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
BOOT0
BOOT1
BOOT2
BOOT3
RESPWRON
NRESWARM
PWRON
RPWRON
PREQ1
PREQ2A
PREQ2B
PREQ2C
PREQ3
INT
SYSEN
REGEN1
REGEN2
TESTEN
REFGND
VBG
IREF
VAUX2
VAUX1
Control Ols
VPP
VMMC
VUSIM
REFS
TESTV
VCORE1_IN
VCORE1_SW
VCORE1
VCORE1_FDBK
SR bus
Events bus
VCORE1_GND
VCORE2_IN
VCORE2_SW
Events detect
SRI2C_SCL
SRI2C_SDA
MSECURE
VCORE2
I2C SmartReflex
VCORE2_FDBK
OCP bus
OSC32KIN
OSC32KCAP
OSC32KOUT
VAUX2
VAUX2_IN
VAUX1
VAUX1_IN
VUSIM_IN1
VUSIM
VMMC
VMMC_IN1
VPP
VPP_IN
VIO
GND_DIG_VIO
DEVICE INFORMATION
Xtal
32K
RC
32K
RC
6M
VCORE2_GND
VCORE3_IN
Power control
VCORE3_SW
CLK32KAO
CLK32KG
CLK32KAUDIO
VCORE3
VCORE3_FDBK
ID
USB SRP
CTLI2C_SCL
I2C control
RTC
VCORE3_GND
VMEM_IN
VMEM_SW
CTLI2C_SDA
VMEM
VMEM_FDBK
I2C to OCP
SIM
MMC
BATREMOVAL
PWM1
PWM2
VMEM_GND
V1V8_IN
Card detect
and
PWM
V1V8_SW
V1V8
V1V8_FDBK
MUX
Scalers
GPADC_IN0
GPADC_IN1
GPADC_VREF1
GPADC_IN2
GPADC_IN3
GPADC_IN4
GPADC_VREF4
GPADC_IN5
GPADC_IN6
V1V8_GND
V1V2_IN
Control, data,
and
test logic
10-bit
ADC
V2V1_SW
V 2V1
V2V1_FDBK
GGAUGE_RESN
V2V1_GND
V1V29_IN
GGAUGE_RESP
Auto calib
GPADC_START
13-bit
SD
ADC
Digital
filter
V1V29_SW
V1V29
V1V29_FDBK
Interrupt handler
CHRG_EXTCHRG_ENZ
CHRG_EXTCHRG_STATZ
VAC
Ext
charger
ctl
V1V29_GND
VANA_IN
OSC
3 MHz
VANA
VANA
VBUS
CHRG_PMID
VRTC_IN
VAUX3
CHRG_GND
VRTC
VRTC
VCXIO
CHRG_CSOUT
VDAC
USB
charger
and
VBUS
OTG
VUSB
CHRG_SW
CHRG_CSIN
CHRG_AUXPWR
GND_DIG_VRTC
VAUX3_IN
GND_ANA_B1
GND_ANA_B2
GND_ANA_B3
GND_ANA_B4
GND_ANA_B5
GND_ANA_B6
GND_ANA_B7
VDD_B1
VDD_B2
VDD_B4
VAUX3
VCXIO_IN
VCXIO
VDAC_IN
VDAC
VDD_B3
CHRG_PMID
VUSB
CHRG_LED_IN
CHRG_LED_TEST
CHRG_VREF
CHRG_DET_N
VBAT
SWCS045-001
Figure 1. TWL6030 Block Diagram
4
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2 presents the ball description of the TWL60340 device. Figure 2 shows the ball mapping from the top
view.
Table 2. Ball Description
NAME
DESCRIPTION
CONNECTION IF
NOT USED
PU/PD (2)
I
Switched charger auxiliary power supply,
connected to the battery pack to provide power in
high-impedance mode
Ground
–
Analog
O
Switched charger boot-strapped capacitor for the
high-side MOSFET gate driver
Floating
–
Analog
I
Switched charger current-sense input
Ground
Ground
BALL
TYPE
I/O
CHRG_AUXPWR
E6
Analog
CHRG_BOOT
G2
CHRG_CSIN
E4
(1)
CHARGER
CHRG_CSOUT
D4
Analog
I
Switched charger battery voltage/current sense
input
CHRG_DET_N
E5
Analog
I
USB charging port detection signal from USB
PHY
Ground
CHRG_EXTCHRG_EN
Z
J7
Digital
O
Output control signal to an external VAC charger
Floating
CHRG_EXTCHRG_ST
ATZ
H7
Digital
I
External charger status input pin
CHRG_LED_IN
D6
Power
I
LED indicator input supply
CHRG_LED_TEST
D5
CHRG_PGND_B1
A5
CHRG_PGND_B2
A6
CHRG_PGND_B3
B6
CHRG_PGND_B4
B5
CHRG_PMID_B1
E1
CHRG_PMID_B2
F1
CHRG_PMID_B3
E2
CHRG_PMID_B4
F2
CHRG_SW_B1
A3
CHRG_SW_B2
A4
CHRG_SW_B3
B4
CHRG_SW_B4
B3
CHRG_VREF
F5
VAC
F4
VBUS_B1
C1
VBUS_B2
D1
VBUS_B3
C2
VBUS_B4
D2
External LED driver output/dedicated charger
TEST ball
Floating or tied to
VRTC (fixed
internal pullup to
VRTC)
*PU
70–190 kΩ
Ground
Analog
I/O
Ground
I
Switched charger power ground
Ground
–
Analog
O
Switched charger connection point between
reverse blocking MOSFET and high-side
switching MOSFET
Floating
–
Power
O
Switched charger internal switch to output
inductor connection
Floating
–
Analog
O
Switched charger internal bias regulator voltage
Power
Power
Input supply from an external VAC charger
I/O
VBUS input voltage, USB battery charger power
supply
Ground or floating
Floating
–
Ground (if not
used in BBS)
–
Ground (Must be
connected to
VBUS if VBUS
detection from
PMIC is needed;
for example, for
USB bootupt)
–
POWER SUPPLIES
(1)
(2)
I = Input; O = Output
PU/PD shows the pullup/down resistors on digital input lines. An asterisk indicates the default option.
Copyright © 2010–2011, Texas Instruments Incorporated
5
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2. Ball Description (continued)
NAME
BALL
GND_ANA_B1
N8
GND_ANA_B2
M10
GND_ANA_B3
E11
GND_ANA_B4
L13
GND_ANA_B5
D9
GND_ANA_B6
H4
TYPE
I/O
(1)
DESCRIPTION
CONNECTION IF
NOT USED
PU/PD (2)
Ground
I
Analog power ground
Ground
–
GND_ANA_B7
G7
GND_DIG_VIO
M8
Ground
I
VIO digital ground
Ground
–
GND_DIG_VRTC
G4
Ground
I
VRTC digital ground
Ground
–
PBKG_B11
T1
Substrate
I
Substrate ground
Ground
–
Power
I
Analog input voltage supply
N/A
–
N/A
–
PBKG_B12
T2
PBKG_B13
R1
PBKG_B2
H5
PBKG_B31
T16
PBKG_B32
T15
PBKG_B33
R16
PBKG_B41
A1
PBKG_B42
A2
PBKG_B43
B1
PBKG_B51
A16
PBKG_B53
B16
VDD_B1
N9
VDD_B2
G13
VDD_B3
B9
VDD_B4
L4
VIO
M9
Power
I
The TWL6030 device digital I/O input supply
voltage (1.8 V)
VPROG
G10
Power
I
EPROM programming voltage
Ground
–
Ground (prefered)
or Floating
–
N/A
–
VBACKUP
E10
Analog
I
Backup battery input voltage
VBAT
B13
Power
I
Battery voltage sense line
H10
Digital
O
32-kHz digital output clock always on when VIO
input supply is present
Floating
–
CLK32KAUDIO
E9
Digital
O
32-kHz digital gated output clock toward the audio
device
Floating
–
CLK32KG
J10
Digital
O
32-kHz digital gated output clock controlled by
software
Floating
–
OSC32KCAP
E8
Analog
O
VRTC power supply external filtering cap for the
32-kHz crystal oscillator
Floating
–
OSC32KIN
A10
Analog
I
32-kHz crystal oscillator input or digital clock input
Digital clock
input,analog clock
input
–
Floating when
digital clock input,
capacitor when
analog clock input
–
N/A
–
CLOCKING
CLK32KAO
OSC32KOUT
A8
Analog
O
32-kHz crystal oscillator output or floating in case
of digital clock input
H12
Analog
I/O
Reference current generation
REFERENCES
IREF
6
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2. Ball Description (continued)
NAME
BALL
REFGND_B1
A9
REFGND_B2
F12
VBG
TYPE
I/O
(1)
DESCRIPTION
CONNECTION IF
NOT USED
PU/PD (2)
Ground
–
N/A
–
Ground (fixed
internal pulldown
to ground)
*PD
170–950 kΩ
Ground
I
System reference ground
G12
Analog
O
Band gap output reference voltage
J8
Digital
I
Test mode enable
A15
Analog
O
Internal voltages sense line
CTLI2C_SCL
M4
Digital
I/O
Control I2C serial clock (I2C voltage level is set by
an external pullup.)
N/A
PU
0.46–1.76
kΩ
CTLI2C_SDA
N4
Digital
I/O
Control I2C serial bidirectional data (I2C voltage
level is set by an external pullup.)
N/A
PU
0.46–1.76
kΩ
INT
K10
Digital
O
Maskable interrupt output request to the host
processor
Floating
–
BATREMOVAL
L12
Digital
O
Battery removal indicator
Floating
BOOT0
H8
Digital
I
Boot ball 0 for power-up sequence selection
Ground or VRTC
BOOT1
G8
Digital
I
Boot ball 1 for power-up sequence selection
Ground or VRTC
BOOT2
G9
Digital
I
Boot ball 2 for power-up sequence selection
Ground or VRTC
BOOT3
H9
Digital
I
Boot ball 3 for power-up sequence selection
Ground or VRTC
NRESPWRON
N5
Digital
O
System reset/power on output
NRESWARM
M5
Digital
I
Warm reset input
TESTING
TESTEN
TESTV
Floating
SYSTEM CONTROL
PREQ1
PREQ2A
PREQ2B
PREQ2C
J9
K9
K8
M7
Digital
Digital
Digital
Digital
Copyright © 2010–2011, Texas Instruments Incorporated
I
I
I
I
Floating
*PU
70–190 kΩ
Floating (fixed
internal pullup to
VIO)
PU/*PD
170–950 kΩ
Peripheral 1 power request input
Floating (use of
internal PU/PD) or
tied to common
PU/*PD
ground or VIO
170–950 kΩ
(depending on
selected
sensitivity)
Peripheral 2A power request input
Floating (use of
internal PU/PD) or
tied to common
PU/*PD
ground or VIO
170–950 kΩ
(depending on
selected
sensitivity)
Peripheral 2B power request input
Floating (use of
internal PU/PD) or
tied to common
PU/*PD
ground or VIO
170–950 kΩ
(depending on
selected
sensitivity)
Peripheral 2C power request input
Floating (use of
internal PU/PD) or
tied to common
PU/*PD
ground or VIO
170–950 kΩ
(depending on
selected
sensitivity)
7
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2. Ball Description (continued)
NAME
BALL
TYPE
I/O
(1)
CONNECTION IF
NOT USED
DESCRIPTION
PREQ3
N6
Digital
I
PWM1
M11
Digital
O
PWM2
M12
Digital
O
Pulse width modulation 2
PU/PD (2)
Floating (use of
internal PU/PD) or
tied to common
PU/*PD
ground or VIO
170–950 kΩ
(depending on
selected
sensitivity)
Peripheral 3 power request input
Floating
–
Floating
–
N/A
*PU
55–370 kΩ
PWRON
L5
Digital
I
External on-button switch-on event (primary input
to launch system wakeup)
REGEN1
K7
Digital
O
External regulator enable 1
Floating
–
REGEN2
J5
Digital
O
External regulator enable 2
Floating
–
Floating (fixed
internal pull-up to
VBAT)
*PU
55–370 kΩ
RPWRON
K5
Digital
I
External remote switch-on event (secondary input
to launch system wakeup)
SYSEN
M6
Digital
O
External system enable
Floating
–
Ground or floating
*PD
170–950 kΩ
MSECURE
N2
Digital
I
Secure mode input. Allow I2C access to secure
registers.
SRI2C_SCL
M13
Digital
I/O
SmartReflex™ I2C serial clock (I2C voltage level
is set by an external pullup.)
Internal pullup on
VIO
PU
0.46–1.76
kΩ
SRI2C_SDA
N13
Analog
I/O
SmartReflex I2C serial data (I2C voltage set by an
external pullup.)
Internal pullup on
VIO
PU
0.46–1.76
kΩ
ID
E12
Digital
I/O
USB connector identification signal
Floating (Internal
pull-up to VUSB)
–
MMC
N11
Digital
I
MMC card insertion and extraction detection to
deactivate the VMMC LDO
Internal pullup to
VIO or pulldown to
ground
PU/*PD
70–190 kΩ
SIM
N12
Power
I
SIM card insertion and extraction detection to
deactivate the VUSIM LDO
Internal pullup to
VIO or pulldown to
ground
PU/*PD
70–190 kΩ
VANA
B10
Power
O
Output voltage for VANA regulator
N/A
–
VANA_IN
DETECTION
LDO REGULATORS
D10
Power
I
Supply of output stage of VANA regulator
VAUX1
T8
Power
O
Output voltage for VAUX1 regulator
VAUX1_IN
N7
Power
I
Supply of output stage of VAUX1 regulator
VAUX2
T9
Power
O
Output voltage for VAUX2 regulator
N10
Power
I
Supply of output stage of VAUX2 regulator
O
Output voltage for VAUX3 regulator (vibrator
driver output)
VAUX2_IN
VAUX3
R9
Power
VAUX3_IN
R8
Power
I
Supply of output stage of VAUX3 regulator
VCXIO
F15
Power
O
Output voltage for VCXIO regulator
VCXIO_IN
F13
Power
I
Supply of output stage of VCXIO regulator
VDAC
G15
Power
O
Output voltage for VDAC regulator
VDAC_IN
H13
Power
I
Supply of output stage of VDAC regulator
VMMC
J13
Power
O
Output voltage for VMMC regulator
VMMC_IN
J12
Power
I
Supply 1 of output stage of VMMC regulator
VPP
K4
Power
O
Output voltage for VPP regulator
VPP_IN
J4
Power
I
Supply of output stage of VPP regulator
VRTC
D7
Power
O
Output voltage for VRTC regulator
8
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
Floating
–
VBAT
–
N/A
–
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2. Ball Description (continued)
NAME
BALL
TYPE
I/O
(1)
DESCRIPTION
CONNECTION IF
NOT USED
PU/PD (2)
D11
Power
I
Input voltage supply for VRTC regulator
VBAT
–
VUSB
A7
Power
O
Output voltage for VUSB regulator
Floating
–
VUSIM
B8
Power
O
Output voltage for VUSIM regulator
Floating
–
VUSIM_IN
D8
Power
I
Supply 1 of output stage of VUSIM regulator
VBAT
–
GGAUGE_RESN
D13
Analog
I
Sense resistor input signal negative (ground side)
Ground
–
GGAUGE_RESP
E13
Analog
I
Sense resistor input signal positive (battery
negative side)
Ground
–
GPADC_IN0
D12
Analog
I/O
General-purpose analog-to-digital converter
(GPADC) input 0
Ground/VRTC
–
GPADC_IN1
B11
Analog
I/O
GPADC input 1
Ground
–
GPADC_VREF1
A11
Analog
O
GPADC output reference 1
Floating
–
GPADC_IN2
B14
Analog
I
GPADC input 2
Ground
–
GPADC_IN3
A13
Analog
I
GPADC input 3
Ground
–
GPADC_IN4
B12
Analog
I/O
GPADC input 4
Ground
–
GPADC_VREF4
A12
Analog
O
GPADC output reference 4
Floating
–
GPADC_IN5
A14
Analog
I
GPADC input 5
Ground
–
GPADC_IN6
B15
Analog
I
GPADC input 6
Ground
–
Ground
*PD
170–950 kΩ
VRTC_IN
MONITORING
K12
Digital
I
Trigger hardware request to start GPADC
synchronous conversion
V1V29_FDBK
G16
Analog
I
V1V29 SMPS feedback
Ground
–
V1V29_GND_B1
H16
V1V29_GND_B2
H15
Ground
I
V1V29 SMPS ground
Ground
–
V1V29_IN_B1
K16
V1V29_IN_B2
K15
Power
I
V1V29 SMPS input voltage
VBAT
–
V1V29_SW_B1
J16
V1V29_SW_B2
J15
Power
O
V1V29 SMPS switch
Floating
–
Analog
I
V1V8 SMPS feedback
Ground
–
Ground
I
V1V8 SMPS ground
Ground
–
Power
I
V1V8 SMPS input voltage
VBAT
–
Power
O
V1V8 SMPS switch
Floating
–
Analog
I
V2V1 SMPS feedback
Ground
–
Ground
I
V2V1 SMPS ground
Ground
–
Power
I
V2V1 SMPS input voltage
VBAT
–
Power
O
V2V1 SMPS switch
Floating
–
Analog
I
VMEM SMPS feedback
Ground
–
GPADC_START
SMPS REGULATORS
V1V8_FDBK
L15
V1V8_GND_B1
M16
V1V8_GND_B2
L16
V1V8_GND_B3
M15
V1V8_IN_B1
T13
V1V8_IN_B2
T14
V1V8_IN_B3
R14
V1V8_SW_B1
N16
V1V8_SW_B2
P16
V1V8_SW_B3
P15
V2V1_FDBK
F16
V2V1_GND_B1
E16
V2V1_GND_B2
E15
V2V1_IN_B1
C16
V2V1_IN_B2
C15
V2V1_SW_B1
D16
V2V1_SW_B2
D15
VMEM_FDBK
R13
Copyright © 2010–2011, Texas Instruments Incorporated
9
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 2. Ball Description (continued)
NAME
BALL
VMEM_GND_B1
T12
VMEM_GND_B2
R12
VMEM_IN_B1
T10
VMEM_IN_B2
R10
VMEM_SW_B1
T11
VMEM_SW_B2
R11
VCORE1_FDBK
L2
VCORE1_GND_B1
M1
VCORE1_GND_B2
L1
VCORE1_GND_B3
M2
VCORE1_IN_B1
T4
VCORE1_IN_B2
T3
VCORE1_IN_B3
R3
VCORE1_SW_B1
N1
VCORE1_SW_B2
P1
VCORE1_SW_B3
P2
VCORE2_FDBK
R4
VCORE2_GND_B1
T5
VCORE2_GND_B2
R5
VCORE2_IN_B1
T7
VCORE2_IN_B2
R7
VCORE2_SW_B1
T6
VCORE2_SW_B2
R6
VCORE3_FDBK
G1
VCORE3_GND_B1
H1
VCORE3_GND_B2
H2
VCORE3_IN_B1
K1
VCORE3_IN_B2
K2
VCORE3_SW_B1
J1
VCORE3_SW_B2
J2
TYPE
I/O
(1)
DESCRIPTION
CONNECTION IF
NOT USED
PU/PD (2)
Ground
–
VBAT
–
Ground
I
VMEM SMPS ground
Power
I
VMEM SMPS input voltage
Power
O
VMEM SMPS switch
Floating
–
Analog
I
VCORE1 SMPS feedback
Ground
–
Ground
I
VCORE1 SMPS ground
Ground
–
Power
I
VCORE1 SMPS input voltage
VBAT
–
Power
O
VCORE1 SMPS switch
Floating
–
Analog
I
VCORE2 SMPS feedback
Ground
–
Ground
I
VCORE2 SMPS ground
Ground
–
Power
I
VCORE2 SMPS input voltage
VBAT
–
Power
O
VCORE2 SMPS switch
Floating
–
Analog
I
VCORE3 SMPS feedback
Ground
–
Ground
I
VCORE3 SMPS ground
Ground
–
Power
I
VCORE3 SMPS input voltage
VBAT
–
Power
O
VCORE3 SMPS switch
Floating
–
RESERVED PINS
RESERVED1
N15
Reserved (tied to ground)
Ground (3)
RESERVED2
K13
Reserved (to be left floating)
Floating (4)
RESERVED3
B7
Reserved(to be left floating)
Floating (5)
(3)
(4)
(5)
10
Float is also possible
Connected to VMMC_IN1 is also possible
Connected to VUSIM_IN1 is also possible
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
T
PBKG
_B31
PBKG
_B32
V1V8
_IN
_B2
V1V8
_IN
_B1
VMEM
_GND
_B1
VMEM
_SW
_B1
VMEM
_IN
_B1
VAUX2
VAUX1
VCORE
2_IN
_B1
VCORE
2_SW
_B1
VCORE
2_GND
_B1
VCORE
1_IN
_B1
VCORE
1_IN
_B2
PBKG
_B12
PBKG
_B11
T
R
PBKG
_B33
V1V8
_IN
_B3
VMEM
_FDBK
VMEM
_GND
_B2
VMEM
_SW
_B2
VMEM
_IN
_B2
VAUX3
VAUX
3
_IN
VCORE
2_IN
_B2
VCORE
2_SW
_B2
VCORE
2_GND
_B2
VCORE
2
_FDBK
VCORE
1_IN
_B3
PBKG
_B13
R
P
V1V8
_SW
_B2
V1V8
_SW
_B3
VCORE
1_SW
_B3
VCORE
1_SW
_B2
P
N
V1V8
_SW
_B1
RESERVED
1
SR
I2C
_SDA
SIM
MMC
VAUX
2
_IN
VDD
_B1
GND
_ANA
_B1
VAUX
1
_IN
PREQ3
NRESP
WRON
CTL
I2C
_SDA
MSE
CURE
VCORE
1_SW
_B1
N
M
V1V8
_GND
_B1
V1V8
_GND
_B3
SR
I2C
_SCL
PWM2
PWM1
GND
_ANA
_B2
VIO
GND
_DIG
_VIO
PREQ
2C
SYSEN
NRES
WARM
CTL
I2C
_SCL
VCORE
1_GND
_B3
VCORE
1_GND
_B1
M
L
V1V8
_GND
_B2
V1V8
_FDBK
GND
_ANA
_B4
BAT
RE
MOVAL
PWR
ON
VDD
_B4
VCORE
1
_FDBK
VCORE
1_GND
_B2
L
K
V1V29
_IN
_B1
V1V29
_IN
_B2
J
V1V29
_SW
_B1
V1V29
_SW
_B2
VMMC
H
V1V29
_GND
_B1
V1V29
_GND
_B2
G
V1V29
_FDBK
F
INT
PREQ2A
PREQ2B
REGEN
1
RPWR
ON
VPP
VCORE
3_IN
_B2
VCORE
3_IN
_B1
K
VMMC
_IN
CLK
32K
G
PREQ1
TEST
EN
CHRG
_EXT
CHRG
_ENZ
REGEN
2
VPP
_IN
VCORE
3_SW
_B2
VCORE
3_SW
_B1
J
VDAC
_IN
IREF
CLK
32K
AO
BOOT3
BOOT0
CHRG
_EXT
CHRG_
STATZ
PBKG
_B2
GND
_ANA
_B6
VCORE
3_GND
_B2
VCORE
3_GND
_B1
H
VDAC
VDD
_B2
VBG
VPROG
BOOT2
BOOT1
GND
_ANA
_B7
GND
_DIG
_VRTC
CHRG
_BOOT
VCORE
3
_FDBK
G
V2V1
_FDBK
VCXIO
VCXIO
_IN
REF
GND
_B2
CHRG
_VREF
VAC
CHRG
_PMID
_B4
CHRG
_PMID
_B2
F
E
V2V1
_GND
_B1
V2V1
_GND
_B2
G
GAUGE
_RESP
ID
GND
_ANA
_B3
VBACK
UP
CLK
32K
AUDIO
OSC
32K
CAP
CHRG
_AUX
PWR
CHRG_
DET_N
CHRG
_CSIN
CHRG
_PMID
_B3
CHRG
_PMID
_B1
E
D
V2V1
_SW
_B1
V2V1
_SW
_B2
G
GAUGE
_RESN
GPADC
_IN0
VRTC
_IN
VANA
_IN
GND
_ANA
_B5
VUSIM
_IN
CHRG
_LED_IN
CHRG
_LED
_TEST
CHRG_
CSOUT
VBUS
_B4
VBUS
_B2
D
C
V2V1
_IN
_B1
V2V1
_IN
_B2
VBUS
_B3
VBUS
_B1
C
B
PBKG
_B53
GPADC
_IN6
GPADC
_IN2
VBAT
GPADC
_IN4
GPADC
_IN1
VANA
VDD
_B3
VUSIM
RESERVED
3
CHRG
_PGND
_B3
CHRG
_PGND
_B4
CHRG
_SW
_B3
CHRG
_SW
_B4
PBKG
_B43
B
A
PBKG
_B51
TESTV
GPADC
_IN5
GPADC
_IN3
GPADC
_VREF4
GPADC
_VREF1
OSC
32K
IN
REF
GND
_B1
OSC
32K
OUT
VUSB
CHRG
_PGND
_B2
CHRG
_PGND
_B1
CHRG
_SW
_B2
CHRG
_SW
_B1
PBKG
_B42
PBKG
_B41
A
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESERVED GPADC_
START
2
VRTC
SWCS045-003
Figure 2. TWL6030 Package Top View Ball Mapping
Copyright © 2010–2011, Texas Instruments Incorporated
11
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
All battery-related input balls (LDOs and SMPSs) and supply voltage: VBAT, VDD,
_IN
–0.3
5.5
V
All battery SMPS-related input balls _FDBK
–0.3
VOUTmax + 0.3
V
Backup battery supply voltage VBACKUP
–0.3
5.5
V
I/O digital supply voltage VIO
–0.3
VIOmax + 0.3
V
Battery charger supply voltage VBUS
-0.3
20.0
V
Battery charger supply voltage VAC
–0.3
20.0
V
Battery charger CHRG_PMID
–0.3
20.0
V
Battery charger CHRG_SW, CHRG_BOOT
–0.7
20.0
V
–7
7
V
Battery charger CHRG_VREF
–0.3
6.5
V
Battery charger CHRG_DET_N
–0.3
VUSBmax + 0.3
V
All other charger analog-related input balls, such as CHRG_AUXPWR,
CHRG_CSIN, CHRG_CSOUT, and CHRG_LED_IN
–0.3
5.5
V
Voltage on the USB OTG ID ball
–0.3
5.5
V
Voltage on the VRTC GPADC balls: GPADC_IN0, GPADC_IN1, and GPADC_IN4
–0.3
VRTCmax + 0.3
V
Voltage on the VANA GPADC balls: GPADC_IN2, GPADC_IN3, GPADC_IN5, and
GPADC_IN6
–0.3
VANAmax + 0.3
V
Voltage on the VDD_B3 GPADC balls
–0.3
5.5
V
Voltage on the crystal oscillator OSC32KIN ball
–0.3
VRTCmax + 0.3
V
Voltage on all other analog input balls such as GGAUGE_RESN, GGAUGE_RESP
–0.3
VANAmax + 0.3
V
EPROM supply voltage VPROG
–0.3
20.0
V
Voltage on VRTC digital input balls
–0.3
VRTCmax + 0.3
V
Voltage on VIO digital input balls
–0.3
VIOmax + 0.3
V
Voltage on VBAT digital input balls
–0.3
VBAT + 0.3 ≤ 5.5
V
External buck boost supply voltage
–0.3
5.5
V
Junction temperature range
–45
150
°C
Peak output current on all other terminals than power resources
–5.0
5.0
mA
Voltage difference between CSIN and CSOUT inputs (VCSIN-VCSOUT)
12
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
Main battery supply voltage VBAT
2.5
3.8
4.8
V
All battery-related input balls VDD_B[1..4]
2.5
3.8
4.8
V
Preregulated LDO-related input balls _IN
1.8
3.8
4.8
V
Other LDO-related input balls _IN
2.3
3.8
4.8
V
All battery SMPS-related input balls _IN
All battery SMPS-related input balls _FDBK
Backup battery supply voltage VBACKUP
I/O digital supply voltage VIO
UNIT
2.5
3.8
4.8
V
VCOREmin
1.1
VOUTmax
V
1.9
3.2
4.8
V
VIOmin
VIO
VIOmax
V
Battery charger supply voltage VBUS
0
5.0
6.7
V
Battery charger supply voltage VAC
0
5.0
10.0
V
Battery charger CHRG_PMID
0
5.0
6.0
V
Battery charger CHRG_SW, CHRG_BOOT
0
5.0
6.0
V
Battery charger CHRG_VREF
0
5.0
6.5
V
Battery charger CHRG_DET_N
0
VUSB
VUSBmax
V
All other charger analog-related input balls, such as CHRG_AUXPWR,
CHRG_CSIN, CHRG_CSOUT, CHRG_LED_IN
0
3.8
4.8
V
Voltage on the USB OTG ID ball
0
VUSB
VUSBmax
V
Voltage on the VRTC GPADC balls GPADC_IN0, GPADC_IN1, and
GPADC_IN4
0
VRTC
VRTCmax
V
Voltage on the VANA GPADC balls GPADC_IN2, GPADC_IN3,
GPADC_IN5, and GPADC_IN6
0
VANA
VANAmax
V
Voltage on the VDD_B3 GPADC balls
0
3.8
4.8
V
Voltage on the crystal oscillator OSC32KIN ball
0
VRTC
VRTCmax
V
Voltage on all other analog input balls such as GGAUGE_RESN,
GGAUGE_RESP
0
VANA
VANAmax
V
EPROM supply voltage VPROG
0
8.0
10.0
V
Voltage on VRTC digital input balls
0
VRTC
VRTCmax
V
Voltage on VIO digital input balls
0
VIO
VIOmax
V
Voltage on VBAT digital input balls
0
3.8
4.8
V
External buck boost supply voltage
MAXLDO (TDCOVmax
+ DV)
3.8
4.8
V
Ambient temperature range
–40
27
85
°C
Junction temperature (Tj)
–40
27
125
°C
Storage temperature range
–65
27
150
°C
Lead temperature (soldering, 10 seconds)
°C
260
ESD SPECIFICATIONS
ESD METHOD
STANDARD
LEVEL
Human body model (HBM)
EIA/JESD22-A114D
2 kV
Charge device model (CDM)
EIA/JESD22-C101C
500 V
Copyright © 2010–2011, Texas Instruments Incorporated
13
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.6
4.7
6.5
4
10
15
µF
1
10
20
mΩ
1
1.30
50
100
Switched-mode regulators
CI
CO
LO
DCRL
Input capacitor
Output filter capacitor
Filter capacitor ESR
f = [1–10] MHz
Filter inductor
V1V29, V2V1, VCORE1, VCORE2,
VCORE3, V1V8, VMEM
0.68
At inductor saturation, IDC=Isat
0.30
Filter inductor DC resistance
Filter inductor Q factor
1
>6 MHz
20
µF
µH
mΩ
V1V29, V2V1, VCORE2, VCORE3,
VMEM
–
–
–
ILIMIT[1:0] = 01 (800 mA IOUTmax
mode)
1300
1620
2000
ILIMIT[1:0] = 1X (1000 mA IOUTmax
mode)
1640
2050
2520
ILIMIT[1:0] = 00 (no current limitation)
–
–
–
ILIMIT[1:0] = 01 (1.2 A IOUTmax mode)
1640
2050
2460
ILIMIT[1:0] = 10 (1.5 A IOUTmax mode)
1920
2400
2800
ILIMIT[1:0] = 11 (1.6 A IOUTmax mode)
2540
3100
3600
10
20
30
mA
5.5
V
4.8
V
ILIMIT[1:0] = 00 (no current limitation)
PMOS current limit (high side)
mA
V1V8, VCORE1
PMOS current limit (high side)
Input current limit under
short-circuit conditions
V1V29_FDBK, V2V1_FDBK,
VCORE1_FDBK, VCORE2_FDBK,
VCORE3_FDBK, V1V8_FDBK,
VMEM_FDBK = 0 V
VINF
Input voltage (functional)
max(Vout+
0.4, 2.5)
VINP
Input voltage (performances)
V1V29, V2V1, VCORE2,
VCORE3, VMEM
max(Vout+
MinDOV,
2.5)
3.8
mA
V1V29, V2V1, VCORE2, VCORE3,
VMEM
MinDOV
IOUT
Dropout voltage for performances
(DOV = Vin–Vout)
Rated output current
IOUT = 800 mA
0.65
IOUT = 1000 mA
0.90
IOUT = 1200 mA
0.70
IOUT = 1500 mA
0.90
IOUT = 2000 mA
1.10
PWM mode: V1V29, V2V1, VCORE2,
VCORE3, VMEM (limitation on
maximum temperature) (1)
0
800
PWM mode: VCORE1, V1V8
(limitation on maximum temperature) (2)
0
1500
Pulse-frequency modulation (PFM)
mode: All
(1)
(2)
14
V
VCORE1, V1V8
mA
200
V1V29, V2V1, VCORE2, VCORE3, VMEM at IOUT = 800 mA. Maximum junction temperature for VOUT ≤ 1.4 V: 125°C. Maximum
junction temperature for VOUT > 1.4 V : 115°C.
VCORE1, V1V8 at IOUT = 1500 mA. Maximum junction temperature for VOUT ≤ 1.4 V: 125°C. Maximum junction temperature for VOUT
> 1.4 V: 115°C.
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IOUT
EXT
Extended output current
TEST CONDITIONS
PWM mode: V1V29, V2V1, VCORE2,
VCORE3, VMEM (limitation on
maximum temperature) (3) (4)
PWM mode: VCORE1, V1V8
(limitation on maximum temperature)
(5) (6)
MIN
TYP
0
MAX
UNIT
1000
mA
0
1600
Includes voltage references, DC
load/line regulations in PFM and PWM
modes, process, and temperature
(–1.2%/+2.4%)
TDCOV
VOUT
Total DC output voltage accuracy
0.6 V
0.601
0.608
0.623
1.1 V
1.101
1.114
1.141
1.225 V
1.226
1.241
1.271
1.3 V
1.301
1.317
1.349
1.35 V
1.352
1.368
1.401
1.8 V
1.801
1.823
1.867
1.9 V
1.902
1.925
1.971
2.1 V
2.101
2.127
2.178
Low range (EPROM dependent)
0.6
1.3
High range (EPROM dependent)
0.7
1.4
12.5
mV
Other selectable voltages
1.35
1.5
1.8
1.9
2.1
V
Output voltage, programmable
(3)
(4)
(5)
(6)
Ripple voltage
V
Step size
Extended voltage range, multiplier for
nominal levels (enabled by EPROM)
RV
V
3.0476
PWM mode, IOUT = 0 to IOUTmax
5
10
mVpp
PFM mode, IOUT = 1 mA, ΔVOUT / VOUT
1
2
%
0.25
0.5
%
0.8
1.6
%
DCLDR
DC load regulation
PWM mode, IOUT = 0 to IOUTmax,
ΔVOUT / VOUT
DCLNR
DC line regulation
PWM mode, IOUT = 0 to IOUTmax, VIN =
VINPmin to VINPmax , ΔVOUT / VOUT
V1V29, V2V1, VCORE2, VCORE3, VMEM at IOUT = 1000 mA. Maximum junction temperature for VOUT ≤ 1.4 V: 115°C. Maximum
junction temperature for VOUT > 1.4 V: 105°C.
Able to withstand this maximum current during cumulative stress time of 1900 hours.
VCORE1, V1V8 at IOUT = 2000 mA. Maximum junction temperature for VOUT ≤ 1.4 V: 115°C. Maximum junction temperature for VOUT
> 1.4 V: 100°C.
Able to withstand this maximum current during cumulative stress time of 1900 hours.
Copyright © 2010–2011, Texas Instruments Incorporated
15
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
3
1
1.5
UNIT
V1V29, V2V1, VCORE2, VCORE3,
VMEM at Vout < 0.75 V
IOUT = 0–150 mA, Tr/Tf = 100 ns
IOUT = 50–250 mA, Tr/Tf = 100 ns
IOUT = 150–400 mA, Tr/Tf = 100 ns
V1V29, V2V1, VCORE2, VCORE3,
VMEM at Vout ≥ 0.75 V
IOUT = 0–150 mA, Tr/Tf = 100 ns
TLDR
Transient load regulation, ΔVOUT /
VOUT
IOUT = 50–250 mA, Tr/Tf = 100 ns
%
IOUT = 150–400 mA, Tr/Tf = 100 ns
VCORE1, V1V8 at Vout < 0.75 V
IOUT = 0–150 mA, Tr/Tf = 100 ns
IOUT = 50–250 mA, Tr/Tf = 100 ns
3.3
4.2
2.8
3.6
Vout < 0.75 V
0.7
1.4
Vout ≥ 0.75 V
0.5
1.0
IOUT = 200 mA, VOUT within accuracy
limits, SMPS not frequency locked
350
500
µs
IOUT = 200 mA, VOUT within accuracy
limits, SMPS frequency locked
2
3
ms
IOUT = 350–800 mA, Tr/Tf = 100 ns
VCORE1, V1V8 at Vout >= 0.75 V
IOUT = 0–150 mA, Tr/Tf = 100 ns
IOUT = 50–250 mA, Tr/Tf = 100 ns
IOUT = 350–800 mA, Tr/Tf = 100 ns
TLNR
TON
TOFF
Transient line regulation, ΔVOUT /
VOUT
Off to on
VIN step = ±0.6 V; Tr/Tf = 10 us;
IOUT=IOUTmax
250
500
µs
3
7.5
15
Ω
From VOUTMIN = 0.6 V to VOUTMAX =
1.3 V ±5%, ILOAD = ILOADmax
50
57
65
µs
From VOUTMIN = 0.6 V to VOUTMAX =
1.3 V ±5%, ILOAD = ILOADmax
11
12.7
14
mV/µs
On to off
IOUT = 0 @ VOUT down to 10% x VOUT
Pulldown resistor
Off mode
Output voltage settling time
(normal mode) VCORE1,
VCORE2, VCORE3
Slew rate
Overshoot
3
10
%
6
6.9
MHz
Off mode @ 25°C
0.1
0.25
Off mode
0.2
1
PFM mode, no switching
35
50
Switching frequency
IQOFF
IQ
16
Off ground current
On ground current
%
5.1
V1V29,V2V1,VCORE2,VCORE3,VME
M in PWM Mode, IOUT = 0 mA, VIN =
3.8 V
8000
VCORE1,V1V8 in PWM mode, IOUT =
0 mA, VIN = 3.8 V
12000
µA
µA
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
www.ti.com
Copyright © 2010–2011, Texas Instruments Incorporated
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
17
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Figure 3. 0.8 A and 1.5 A SMPS Regulator Efficiencies (7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Connected from _IN to GND.
Shared input tank capacitance
(depending on platform
requirements and power tree)
0.3
10
For VUSB - Connected from
CHRG_PMID to GND
0.9
4.7
6.5
Output filtering capacitor
Connected from LDO output to GND
0.6
2.2
2.7
µF
Filtering DC capacitor ESR
< 100 kHz
20
100
600
mΩ
Filtering AC capacitor ESR
[1–10] MHz
1
10
20
mΩ
VBATmin
3.8
5.5
VRTC: VBAT during backup mode
1.9
2.1
3.1
VRTC: Vbackup during backup
mode
1.9
3.8
5.5
VAUX1, VAUX2, VAUX3, VCXIO,
VDAC, VMMC, VPP, VUSIM (for
VOUT > 1.5 V)
TDCOV + DV –
0.2
TDCOV +
DV –
0.1
5.5
VAUX1, VAUX2, VAUX3, VCXIO,
VDAC, VMMC, VPP, VUSIM (for
VOUT ≤ 1.5 V)
1.8
3.8
5.5
VANA
2.3
3.8
5.5
VUSB from VBAT
3.5
3.8
5.5
VUSB from CHRG_PMID
3.5
6.0
6.8
LDO REGULATORS
CIN
Input filtering capacitor
COUT
VRTC: VBAT during on mode
VINF
Input voltage (functional)
VRTC
VINP
(7)
18
Input voltage (performance)
µF
V
VBATmin
3.8
5.5
VANA: VBAT input source supply
only supported
2.3
3.8
4.8
VAUX1, VAUX2, VAUX3, VCXIO,
VDAC, VMMC, VPP, VUSIM (for
VOUT > 1.5 V)
TDCOVmax +
DV
3.8
4.8
VAUX1, VAUX2, VAUX3, VCXIO,
VDAC, VMMC, VPP, VUSIM (for
VOUT ≤ 1.5 V)
1.8
3.8
4.8
VUSB: from VBAT
3.6
3.8
4.8
VUSB: from CHRG_PMID
4.3
5.0
5.5
V
Coils used:
(a) For VCORE1: MURATA LQM32PN1R0MG0 3.2x2.5x1
(b) For VCORE2: MURATA LQM2MPN1R0NG0 2x1.6x1
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
TDCOV
TOVA
Total DC output voltage accuracy.
Includes voltage references, DC
load/line regulations, process and
temperature
(except VRTC)
VRTC
1.8V
Total output voltage accuracy.
Includes voltage references, DC
load/line regulations, transient
load/line regulation, process and
temperature
1.0 V
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.7 V
1.8 V
1.9 V
2.0 V
2.1 V
2.2 V
2.3 V
2.4 V
2.5 V
2.75 V
2.8 V
2.9 V
3.0 V
3.3 V
Dropout voltage @VIN_MIN = 2.3 V
DV
Dropout voltage @VIN_MIN =1.8 V
IOUT
TEST CONDITIONS
1.0 V
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
1.7 V
1.8 V
1.9 V
2.0 V
2.1 V
2.2 V
2.3 V
2.4 V
2.5 V
2.75 V
2.8 V
2.9 V
3.0 V
3.3 V
Rated output current
MIN
TYP
MAX
–1.7%
1.018
1.222
1.323
1.425
1.527
1.628
1.730
1.832
1.934
2.036
2.138
2.240
2.341
2.443
2.545
2.800
2.850
2.952
3.054
3.359
+1.2%
V
1.801
1.823
1.890
V
–3.6%
1.018
1.222
1.323
1.425
1.527
1.628
1.730
1.832
1.934
2.036
2.138
2.240
2.341
2.443
2.545
2.800
2.850
2.952
3.054
3.359
+3.1%
V
VCXIO, VDAC, IOUT = IOUTmax
150
VANA, IOUT = IOUTmax
100
VMMC, VUSIM: IOUT = 50 mA
140
VUSB, @IOUT=IOUTmax
200
VAUX1, VAUX2, VAUX3, VMMC,
VPP, VRTC, VUSIM: VINPmin =
TDCOV + DV, @IOUT=IOUTmax
300
VCXIO, VDAC, IOUT = IOUTmax
250
VAUX1, VAUX2, VAUX3, VMMC,
VPP, VUSIM: VINPmin = TDCOV + DV,
@IOUT=IOUTmax
400
VANA, VRTC
25
VUSB
35
VDAC, VPP
50
VAUX1, VAUX2, VAUX3, VCXIO,
VMMC, VUSIM
Range
VOUT
Output voltage, programmable
(except VRTC and VANA)
Copyright © 2010–2011, Texas Instruments Incorporated
mV
mA
200
1.0
Step size
3.3
100
Additional selectable voltage level
Load current limitation
UNIT
V
mV
2.75
V
VANA, VDAC, VPP, VRTC, VUSB
100
250
400
VAUX1, VAUX2, VAUX3, VCXIO,
VMMC, VUSIM
400
650
900
mA
19
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
PARAMETER
www.ti.com
TEST CONDITIONS
TYP
MAX
0.25
0.5
%
VIN = VINPmin to VINPmax
IOUT = IOUTmax
0.1
0.2
%
Turn-on time
IOUT = 0, VOUT = 0.1 V up to VOUTmin
100
500
µs
Turn-off time (except VRTC)
IOUT = 0, VOUT down to 10% x VOUT
250
500
µs
Pulldown resistor (except VRTC)
Off mode
40
60
80
Ω
f = 217 Hz, IOUT = IOUTmax
55
90
f = 50 kHz, IOUT = IOUTmax
35
45
f = 1 MHz, IOUT = IOUTmax
DCLDR
DC load regulation, ∆VOUT/VOUT
IOUT = 0 to IOUTmax
DCLNR
DC line regulation, ∆VOUT/VOUT
Ton
Toff
PSRR
Power supply ripple rejection
IQOFF
Off ground current
IQ0
On ground current
αQ
On ground current coefficient On
mode, IQOUT = IQ0 + αQ * IOUT
MIN
dB
30
35
Off mode @ 25°C
0
0.05
0.15
Off mode
0
0.2
1
IOUT = 0, (except VDAC)
12
18
23
IOUT = 0, VDAC
75
150
175
IOUT < 100 μA
4
100 μA < IOUT < 1 mA
2
IOUT > 1 mA
1
TLDR
Transient load regulation,
∆VOUT/VOUT
TLNR
Transient line regulation,
∆VOUT/VOUT
VIN step = 600 mVpp, Tr = Tf = 10
µs
0.25
0.5
100 < f < 10 kHz
5000
8000
10 kHz < f < 100 kHz
1250
2500
100 kHz < f < 1 MHz
150
300
f > 1 MHz
250
500
100 < f < 5 kHz
Noise (VDAC)
µA
µA
%
On mode, IOUT = 100 µA to
IOUTmax/2,
Tr = Tf = 1 µs
Noise (except VDAC)
UNIT
0.75
1.5
%
%
200
400
5 kHz < f < 400 kHz
62
125
400 kHz < f < 10 MHz
25
50
2.2
2.7
nV/√Hz
nV/√Hz
VAUX3 WHEN USED AS VIBRATOR DRIVER
COUT
Output filtering capacitor
Connected from LDO output to GND
0.6
Output regulated output range
Configurable step of 100 mV
1.0
Vibrator inductive load
Connected from VAUX3 to ground
70
Vibrator load resistance
µF
3.3
V
350
700
µH
15
40
50
Ω
REFERENCE GENERATOR
Filtering capacitor
Connected from VBG to REFGND
30
100
150
nF
Biasing resistor (±1%) @ 25°C
Connected from IREF to REFGND
0.990
1.000
1.010
MΩ
25
50
ppm/°C
V
Biasing resistor (±1%) temperature
coefficient
VINF
Input voltage VINF
Functional
1.9
2.2
2.3
VINP
Input voltage VINP
Performance
2.3
3.8
5.5
V
15
20
40
µA
1
3
ms
ppm
Ground current
Start-up time
CRYSTAL CHARACTERISTICS
Crystal frequency
@ specified load cap value
Crystal tolerance
T = 25°C
Secondary temperature coefficient
Crystal series resistor
Operating drive level
Crystal load capacitor (according to
crystal data sheet)
20
32768
Hz
–20
0
20
–0.04
–0.035
–0.03
@ fundamental frequency
0.1
12.5
ppm/°C2
90
kΩ
0.5
µW
pF
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
TEST CONDITIONS
MIN
Shunt capacitor
Quality factor
TYP
MAX
1.4
2.6
8000
UNIT
pF
80000
CRYSTAL OSCILLATOR EXTERNAL COMPONENTS
VRTC power supply external filtering
OSC32KCAP
cap
Load capacitors on OSC32KIN and
OSC32KOUT (parallel mode,
including parasitic of PCB for
external cap)
Frequency accuracy (considering
crystal tolerance and internal load
capacitors variation)
0.6
Frequency
Duty cycle
1.0
2.7
32.768
40
Rise and fall time (10–90%)
kHz
50
60
%
10
20
ns
1
ms
Setup time
@ 25°C, normal and
high-performance (HP) modes
–30
0
30
@ 25°C, backup mode
–80
0
80
Oscillator capacitor ratio:
COSC32KIN/COSC32KOUT
µF
ppm
1
Frequency temperature coefficient
Oscillator contribution in normal and
HP modes (not including the crystal
variations)
SSB phase noise at a 1-kHz offset
from the carrier
HP mode OSC_HPMODE = 1
–125
dBc/Hz
SSB phase noise at a 100-Hz offset
from the carrier
HP mode OSC_HPMODE = 1
–105
dBc/Hz
Cycle jitter short term (peak-peak)
Normal mode OSC_HPMODE = 0
25
ns
Period-to-period jitter, long-term
100k pulses (peak-peak)
Normal mode OSC_HPMODE = 0
120
ns
20 Hz – 20 kHz flat
0.86
80 Hz – 20 kHz flat
0.43
Startup time on power on
Gm boosted during start-up phase
Shunt capacitor ≤ 1.4 pF
300
Sixth harmonic mode rejection
RS32/RS200
Oscillator ratio between negative
resistance @ 32 kHz and negative
resistance @ 200 kHz (sixth
harmonic)
Integrated jitter (HP mode)
±0.5
ppm/°C
nsRMS
ms
10
Crystal mounted:
– Backup mode (@ 25°C)
Ground current
1.5
– Normal mode: OSC_HPMODE = 0
3
– HP mode: OSC_HPMODE = 1
5
– Start-up (boost) phase
20
Bypass mode: OSC_BYPASS = 1
Duty cycle CLK32KAO/CLK32KG
Logic output signal
Rise and fall time (10–20%)
CLK32KAO/CLK32KG
µA
3
40
50
60
%
5
20
100
ns
32-kHz RC OSCILLATOR
Output frequency
Output frequency accuracy
32
After trimming
–15
0
40
50
Cycle jitter (RMS)
Output duty cycle
Settling time
Active current consumption
4
Power-down current
kHz
+15
%
10
%
60
%
150
µs
8
µA
30
nA
6-MHz RC OSCILLATOR
Output frequency
Output frequency accuracy
Cycle jitter (RMS)
Copyright © 2010–2011, Texas Instruments Incorporated
6
After trimming
–10
0
MHz
+10
%
5
%
21
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
PARAMETER
www.ti.com
TEST CONDITIONS
Output duty cycle
MIN
TYP
MAX
40
50
60
5
µs
50
100
µA
50
nA
Settling time
Active current consumption
Power-down current
UNIT
%
CLK32KAUDIO OUTPUT BUFFER
Settling time
0
25
50
µs
Active current consumption
5
7
10
µA
30
nA
Power down current
High output level (VHOUT)
1.70
1.80
1.90
V
–2
0
2
%
20 Hz–20 kHz flat
0
25
50
80 Hz–20 kHz flat
0
10
20
Duty cycle degradation contribution
Integrated jitter contribution
External output load
psRMS
5
10
50
pF
Output delay time
Output load = 10 pF
0
15
30
ns
Output rise/fall time
Output load = 10 pF
5
7.5
10
ns
Output drive strength
VOL = 0.2 V
±1%
±2%
VOH = VHOUT–0.2 V
mA
BACKUP BATTERY CHARGER
VBACKUP to GPADC input
attenuation
VBACKUP from 2.4 to 4.5 V
Backup battery charging current
VBACKUP = 0 to 2.6 V
BB_CHG_EN = 1
350
650
900
IVBACKUP = –10 µA, BB_SEL = 00
(VBAT > 3.2 V)
2.90
3.00
3.10
IVBACKUP = –10 µA, BB_SEL = 01
(VBAT > 2.7 V)
2.42
2.52
2.60
IVBACKUP = –10 µA, BB_SEL = 10
(VBAT > 3.35 V)
3.05
3.15
3.25
V
IVBACKUP = –10 µA, BB_SEL = 11
(VBAT > 2.5 V)
VBAT–0.3
VBAT
IVBACKUP = –10 µA, BB_SEL = XX
(VBAT < 2.5 V)
VBAT–0.2
VBAT
10
µA
End backup battery charging
voltage: VBBCHGEND
Current consumption
Backup battery series resistance
0.2
BB_CHG_EN = 1, IVBACKUP = 0
µA
Capacitance = 5 to 15 mF
Capacitance = 100 to 2000 mF
V/V
10
1500
5
15
µA
Ω
BATTERY CHARGER
CVBUS
VBUS capacitor (VBUS – PGND)
0 V < VBUS < 5.25 V
1.2
4.7
6.5
µF
0 V < VBUS < 6 V
0.9
4.7
6.5
µF
mΩ
ESR (1–10 MHz)
CPMID
PMID capacitor (PMID – PGND)
Output capacitor (CSOUT – PGND)
Output capacitor (CSIN – PGND)
Bootstrap capacitor (BOOT – SW)
22
1
10
20
0 V < VBUS < 5.25 V
1.2
4.7
6.5
0 V < VBUS < 6 V
0.9
4.7
6.5
ESR (1–10 MHz)
1
10
20
0 V < CSOUT < 4.5 V
3
10
15
µF
20
mΩ
150
nF
400
mΩ
ESR (1–10 MHz)
0 V < CSIN < 4.5 V
20
100
5
10
ESR (100 kHz)
ESR (9 MHz)
Ref voltage capacitor
0 V < VREF < 6.5 V
(VREF – PGND)
ESR (1–10 MHz)
0.7
2.2
µF
mΩ
20
nF
200
mΩ
2.86
µF
20
mΩ
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
Coil (option 1), (SW – CSIN)
Coil (option 2), (SW – CSIN)
TEST CONDITIONS
0 A–1.5 A
IVBUS
VBUS supply current control
TYP
MAX
UNIT
0.7
1
1.45
µH
130
mΩ
0.7
1
DCR
1.3
µH
60
mΩ
68
+1%
mΩ
CHRG_SW
1.5
1.545
A
VBUS > VBUSmin, PWM switching
10
0 A–2.7 A
DCR
Rsense resistor (CSIN – CSOUT)
Output average current
MIN
–1%
VBUS > VBUSmin, PWM not
switching
5
0°C < TJ < 85°C, HZ_MODE = 1,
32S mode
IVBUS_LEAK
30
µA
5
µA
4.76
V
Leakage current from battery to
VBUS ball
0°C < TJ < 85°C, CHRG_AUXPWR
= 4.2 V, high-impedance mode
Nominal output charge voltage,
programmable
20-mV steps
3.50
T = 25°C
–0.5
0.5
0°C < T < 125°C
–1.0
1.0
300
1500
IOCHARGE < 600 mA
–5
5
IOCHARGE ≥ 600 mA
–3
3
ITERM = 50 mA
–33
33
100 mA ≤ ITERM ≤ 250 mA
–25
25
300 mA ≤ ITERM ≤ 400 mA
–5
5
Both rising and falling, 2-mV
overdrive,
TR, TF = 100 ns
30
31
34
VAC_DET positive threshold
2.90
3.00
3.15
V
Hysteresis
100
135
170
mV
VBUS_DET positive threshold
2.90
3.00
3.15
V
Hysteresis
100
135
170
mV
25
30
36
ms
3.6
3.8
4.0
V
4
5
6
ms
VOREG
Voltage regulation accuracy
Nominal output charge current,
programmable
IOCHARGE
Charge current accuracy
Termination charge current
Termination current accuracy
ITERM
Deglitch time for charge termination
VAC detection
VBUS detection
VAC/VBUS detection deglitch time
VVBUS_MIN
mA
3.54
%
mA
%
%
ms
VBUS input voltage lower limit
Input power source detection for
battery charging
Deglitch time for VBUS rising above
VVBUS_MIN
Rising voltage, 2-mV overdrive, TR =
100 ns
Hysteresis for VVBUS_MIN
Input voltage rising
100
200
mV
Collapse threshold
Input current is automatically
reduced, programmable, 80-mV
steps
4.2
4.76
V
–2
+2
%
–4
4
%
Analog DPM loop kick-in threshold
accuracy
Collapse comparator threshold
accuracy
(Digital DPM feature)
Analog anticollapse comparator
hysteresis
50
Input source dV/dt
VBUS falling from collapse threshold
to VINmin
Collapse debounce time
VBUS falling
VBUS rising
Tint detection interval
Input power source detection
Copyright © 2010–2011, Texas Instruments Incorporated
mV
2000
0.0625
100
1.7
2
V/s
ms
2.6
s
23
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
PARAMETER
IIN_LIMIT
www.ti.com
MIN
TYP
MAX
IIN_LIMIT = 100 mA, VBAT >
VBATMIN_LO
84
91
98
IIN_LIMIT = 500 mA, VBAT >
VBATMIN_LO
425
460
495
VREF internal reference voltage
VBUS > VINmin or
CHRG_AUXPWR > VBATMIN,
IVREF = 1 mA, CVREF = 1 µF
1.65
Voltage from BOOT pin to SW pin
During charge or boost operation
VBUS input current limiting threshold
TEST CONDITIONS
Below VOREG
Recharge threshold voltage
UNIT
mA
70
Deglitch time, VCOUT decreasing
below threshold, TF = 100 ns, 10 mV
overdrive
6.5
120
V
6.5
V
160
mV
130
ms
BATTERY CHARGER, BATTERY DETECTION
IDETECT battery detection current
before charge done (sink current)
Begins after termination detected,
CHRG_AUXPWR ≤ VOREG
TDETECT battery detection time
-0.6
–0.45
-0.2
mA
215
262
335
ms
CHRG_
CHRG_AUXP
CHRG_AU
AUXPW
WR+0.0
XPWR+0.1
R+0.04
mV
BATTERY CHARGER, SLEEP COMPARATOR
VSLP
VSLP_
EXIT
SLEEP state entry threshold
VBUS above CHRG_AUXPWR 2.3
V ≤ CHRG_AUXPWR ≤ VOREG,
VBUS falling
SLEEP state exit hysteresis
2.3 V ≤ HRG_AUXPWR ≤ VOREG
Deglitch time for VBUS rising above
VSLP + VSLP_EXIT
Rising voltage, 2-mV overdrive, TR =
100 ns
140
200
260
mV
31
32
34
ms
180
250
mΩ
BATTERY CHARGER, PWM
Internal top reverse blocking
MOSFET on-resistance
Internal top N-channel switching
MOSFET on-resistance
Measured from PMID to SW
120
250
mΩ
Internal bottom N-channel MOSFET
on-resistance
Measured from SW to PGND
150
200
mΩ
3
3.3
MHz
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
2.7
99.5
%
0
%
BATTERY CHARGER, BOOST MODE
Boost output voltage (to pin VBUS)
2.5 V < CHRG_AUXPWR < 4.5 V
Boost output voltage tolerance
Including line, load regulation
IBO1
Maximum output current for boost at
USB connector level
VBUS_B = 5.10 V,
2.5 V < CHRG_AUXPWR < 4.5 V
200
mA
IBO2
Maximum output current for boost at
PMID connector level
VBUS_B = 5.10 V,
2.5 V < CHRG_AUXPWR < 4.5 V
235
mA
IBLIMIT cycle-by-cycle current limit
for boost
VBUS_B = 5.10 V,
2.5 V < CHRG_AUXPWR < 4.5 V
0.5
1.0
1.5
A
Overvoltage protection threshold for
boost (VBUS pin)
Threshold over VBUS to turn off
converter during boost
5.8
6.0
6.2
V
Hysteresis
VBUS falling from above VBUSOVP
90
125
160
mV
Efficiency
CHRG_AUXPWR = 3.6 V, IBO = 200
mA, TA = 25°C, synchronous
operation
70
85
VBUS_B
VBUSOVP
IDDQ
VBATMAX
24
5.05
–3
Quiescent current
Maximum battery voltage for boost
(CSOUT pin)
VCSOUT rising edge during boost
Hysteresis
VCSOUT falling from above
VBATMAX
0
V
3
%
%
2.34
2.7
mA
4.75
4.9
5.05
V
149
200
260
mV
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
VBATMIN
TEST CONDITIONS
MIN
TYP
Minimum battery voltage for boost
(CHRG_AUXPWR pin)
Boost output resistance at HP mode
(from VBUS to PGND)
MAX
2.5
UNIT
V
HZ_MODE = 1
165
kΩ
VBUS OVP threshold voltage
Threshold over VBUS to turn off
converter during charge
6.3
6.5
6.7
V
Hysteresis
VBUS falling from above VOVP_VBUS
120
140
160
mV
Battery OVP threshold voltage
VCSOUT threshold over VOREG to
turn off charger during charge
110
117
121
Hysteresis
Lower limit for VCSOUT falling from
above VOVP_VBAT
BATTERY CHARGER, PROTECTION
VOVP_
VBUS
VOVP_
VBAT
VBAT_
SHORT
IBAT_
%
11
ILIMIT cycle-by-cycle current limit for BUCK_HSLIMI = 0: 2.55 A
charge (1)
BUCK_HSLIMI = 1: 1.90 A default
2.10
2.55
3.30
1.50
1.90
2.60
Short-circuit voltage threshold
CHRG_AUXPWR rising (default)
2.00
2.10
2.20
V
Hysteresis
CHRG_AUXPWR falling from above
VBAT_SHORT
90
100
110
mV
Short-circuit detection current
CHRG_AUXPWR ≤ VBAT_SHORT
20
30
40
mA
VBUS input current
VBUS = 9.7 V, OVP active
4
mA
Charger thermal shutdown
Temperature threshold,
TCHRGSHTDWN
148
Hysteresis, TCHRGHYS
10
SHORT
Thermal regulation threshold TCF
A
°C
°C
125
BATTERY TEMPERATURE MEASUREMENT
RBRI
External pulldown resistor
IBRI
Current source for the detection
VBRIRef
Detection threshold
0
130
Offset of the comparator
1.5
1.6
V
–10
10
mV
10
µA
10
µs
4.8
V
Current consumption of the
comparator
Delay of the comparator
µA
7.5
Threshold
kΩ
With >10-mV overdrive
INDICATOR LED DRIVER
VBAT
CH_LED_CURR[1:0] = 00
LED current
0
0
CH_LED_CURR[1:0] = 01
–15%
1
+15%
CH_LED_CURR[1:0] = 10
–15%
2.5
+15%
CH_LED_CURR[1:0] = 11
–15%
5
+15%
Rise and fall time for the current
Transition on PWM signal, 10–90%
Startup time
CH_LED_CURR[1:0] from 00 →
others
mA
5
µs
20
µs
Disabled
VRTC (backup mode)
VRTC (wait-on/sleep/active modes)
Quiescent current
1
2
VAC (@ 20 V)
70
CHRG_PMID (@ 5.25 V)
20
CHRG_PMID (@ 20 V)
(1)
0.1
µA
70
CH_LED_CURR[1:0] = 01 (1 mA)
200
CH_LED_CURR[1:0] = 10 (2.5 mA)
400
CH_LED_CURR[1:0] = 11 (5 mA)
750
µA
If using a charger with a current charge always lower and equal to 1.25 A, you can use a 1.5-A current rated inductor. If the current
charge is higher than 1.25 A, a 2.1-A current rated inductor must be used.
Copyright © 2010–2011, Texas Instruments Incorporated
25
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
Pulldown resistance
TEST CONDITIONS
CH_LED_CURR[1:0] = 00, can be
disabled by the DIS_PULLDOWN bit
MIN
TYP
MAX
UNIT
50
100
200
kΩ
3.2
V
5.5
V
Voltage at the output for
performance
Voltage at the output for tolerance
CHRG_LED_TEST pin is driven
externally
Dropout voltage
Minimum voltage between
CHRG_LED_IN and
CHRG_LED_TEST
1 mA
0.2
2.5 mA
0.4
5 mA
0.6
VAC voltage
During operation
4.1
V
VBUS voltage
During operation
4.0
V
CHRG_LED_IN voltage
V
2.3
5.5
V
USB OTG ID EXTERNAL RESISTORS SPECIFICATIONS
RID_FLOAT
ID pulldown, when ID pin is floating
Input spec for external ID resistor
220
RID_A
ACA ID pulldown, TWL6030 is
A-Device
kΩ
Input spec for external ID resistor
119
132
kΩ
RID_B
ACA ID pulldown, TWL6030 is
B-Device, but can’t connect
Input spec for external ID resistor
65
72
kΩ
RID_C
ACA ID pulldown, TWL6030 is
B-Device, can connect
Input spec for external ID resistor
35
39
kΩ
RIDGND
ID pulldown when ID pin is grounded Input spec for external ID resistor
1
kΩ
USB OTG PULLUP AND PULLDOWN RESISTORS
RID_PU_100
ID 100k pullup to VUSB
70
100
130
kΩ
ID 220k pullup to VUSB
160
220
280
kΩ
1
10
20
kΩ
K
RID_PU_220
K
RID_GND_D
ID 10k pulldown to ground
RV
RID_
LKG
ID internal leakage without GPADC
(7 V)
350
nA
RID_
LKG
ID internal leakage without GPADC
(2 V)
650
nA
ID external leakage
–1.5
0
1
µA
0.300
0.650
1.150
V
10
100
220
kΩ
USB OTG COMPARATORS
VID_WK
ID wake-up comparator threshold
RID_WK_UP
ID wake-up equivalent threshold
resistance
No hysteresis
VID_CMP1
ID comparator 1 threshold
No hysteresis
0.150
0.200
0.250
V
VID_CMP2
ID comparator 2 threshold
No hysteresis
0.683
0.720
0.757
V
VID_CMP3
ID comparator 3 threshold
No hysteresis
1.300
1.400
1.500
V
VID_CMP4
ID comparator 4 threshold
No hysteresis
2.350
2.500
2.650
V
USB OTG CURRENT SOURCES
IID_WK_SRC
ID wake-up current source
VID < 2.75 V
3.5
9
25
µA
IID_SRC_16u
ID current source (trimmed)
VID < 2.75 V
15.5
16
16.5
µA
IID_SRC_5u
ID current source
VID < 2.75 V
4.5
5
5.5
µA
USB OTG ADP COMPARATORS
VADP_ PRB
ADP probing voltage threshold
No hysteresis
0.6
0.65
0.7
V
VADP_ SNS
ADP sensing voltage threshold
No hysteresis
0.20
0.40
0.55
V
VADP_
ADP discharge voltage
0.15
V
1.65
mA
DSCHRG
USB OTG ADP CURRENT SOURCES/SINKS
VBUS_IAD
ADP source current
P_SRC
26
VBUS < 0.8 V
1.10
1.40
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
VBUS_IAD
ADP sink current
P_SINK
MIN
TYP
MAX
0.5 V < VBUS < 0.8 V
TEST CONDITIONS
1.1
1.5
2
0.15 V < VBUS < 0.8 V
0.5
1.5
2
13
14
15
UNIT
mA
USB OTG ADP TIMINGS
T_ADP_SI
NK
ADP sink time
TA_ADP_
PRB
ADP probing period, A-device
1.25
1.75
1.85
s
TA_ADP_
PRB
ADP probing period, B-device
1.9
2.0
2.6
s
T_ADP_S
NS
ADP sensing time-out
3
ms
s
USB OTG COMPARATORS
VVBUS_W VBUS wake-up comparator
KUP_UP
threshold (up)
2.90
3.00
3.15
V
VVBUS_W
VBUS wake-up comparator
KUP_DW
threshold (down)
N
2.80
2.90
3.05
V
50
100
175
mV
4.4
4.5
4.6
V
VVBUS_W
VBUS wake-up hysteresis voltage
KUP_HYS
VA_VBUS
_VLD
A-device VBUS valid comparator
threshold
VB_SESS
_VLD_UP
B-device session valid comparator
threshold (up)
2.2
2.4
2.6
V
VB_SESS
_VLD_DW
N
B-device session valid comparator
threshold (down)
2.1
2.3
2.5
V
VB_SESS
_VLD_HY
S
B-device session valid hysteresis
voltage
20
80
140
mV
VA_SESS
_VLD_UP
A-device session valid comparator
threshold (up)
0.9
1.1
1.3
V
VA_SESS
_VLD_DW
N
A-device session valid comparator
threshold (down)
0.8
1.0
1.2
V
VA_SESS
_VLD_HY
S
A-device session valid hysteresis
voltage
10
40
70
mV
VB_SESS
_END_UP
B-device session end comparator
threshold (up)
0.3
0.5
0.8
V
VB_SESS
B-device session end comparator
_END_DW
threshold (down)
N
0.2
0.4
0.7
V
VB_SESS
_END_HY
S
B-device session end hysteresis
voltage
10
40
70
mV
VOTG_SE
SS_VLD_
UP
OTG session valid comparator
threshold (up)
2.90
3.10
3.40
V
VOTG_SE
SS_VLD_
DWN
OTG session valid comparator
threshold (down)
2.80
3.00
3.30
V
VOTG_SE
SS_VLD_
HYS
OTG session valid hysteresis
voltage
20
80
140
mV
VOTG_OV OTG overvoltage comparator
V_UP
threshold (up)
6.3
6.5
6.8
V
VOTG_OV OTG overvoltage comparator
V_DWN
threshold (down)
6.2
6.4
6.7
V
Copyright © 2010–2011, Texas Instruments Incorporated
No hysteresis
27
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
PARAMETER
www.ti.com
TEST CONDITIONS
VOTG_OV
OTG overvoltage hysteresis voltage
V_HYS
MIN
TYP
MAX
UNIT
40
110
180
mV
–6.2
0
6.2
A
0
0
0
0
Vmeas*1%
+0.11
+0.28
+0.74
+2.15
GAS GAUGE
Current measurement range
10-mΩ sense resistor
Measurement accuracy after
calibration
Tolerance of the sense resistor not
included
Includes reference, temperature,
offset CG_PERIOD[1:0] = 00
CG_PERIOD[1:0] = 01
CG_PERIOD[1:0] = 10
CG_PERIOD[1:0] = 11
Offset before autocalibration
Offset after autocalibration
–Vmeas*1%
–0.11
–0.28
–0.74
–2.15
CG_PERIOD[1:0] = 00
200
CG_PERIOD[1:0] = 01
200
CG_PERIOD[1:0] = 10
200
CG_PERIOD[1:0] = 11
450
CG_PERIOD[1:0] = 00
10
CG_PERIOD[1:0] = 01
10
CG_PERIOD[1:0] = 10
100
CG_PERIOD[1:0] = 11
Input clock frequency
Current consumption
32-kHz crystal oscillator
Power on; FG_EN = 1
50
DNL
Integral nonlinearity
Differential nonlinearity
62
µV
mV
kHz
70
0.2
µA
250
01: 62.5 ms
62.5
10: 15.625 ms
15.625
11: 3.90625 ms
3.90625
ms
10
CG_PERIOD[1:0] = 00
1 + 13
CG_PERIOD[1:0] = 01
1 + 11
CG_PERIOD[1:0] = 10
1+9
CG_PERIOD[1:0] = 11
INL
0
Power off; FG_EN = 0
External sense resistor
Integrator data size (two’s
complement)
`
32.768
00: 250 ms
Integration period (sample counter
uses 32-kHz crystal oscillator)
µV
450
–62
Usable input voltage range
mV
mΩ
Bit
1+7
CG_PERIOD[1:0] = 00
-3.5
0
+3.5
CG_PERIOD[1:0] = 01
-2.5
0
+2.5
CG_PERIOD[1:0] = 10
-2.0
0
+2.0
CG_PERIOD[1:0] = 11
-1.5
0
+1.5
CG_PERIOD[1:0] = 00
-4.0
0
+4.0
CG_PERIOD[1:0] = 01
-2.5
0
+2.5
CG_PERIOD[1:0] = 10
-1.5
0
+1.5
CG_PERIOD[1:0] = 11
-1.0
0
+1.0
Accumulator data size
Offset data size
Sample counter data size
LSB
LSB
1 + 31
Bit
1+9
Bit
24
Bit
GPADC
Current consumption
GPADC_EN = 1
Off – mode current
GPADC_EN = 0
Running frequency F
Clock period T = 1/F
Resolution
28
750
1400
1
0.85
Duty cycle 50/50
900
1
1.15
µA
µA
MHz
1
µs
10
Bit
Number of external inputs
7
Number of internal inputs
10
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
TEST CONDITIONS
N = number of analog inputs to
convert in one sequence
MIN
TYP
0
GPADC_EN 0 to 1 or GPADC_EN 1
to 0
MAX
UNIT
17
0
50
100
µs
–3.5
0
3.5
%
–20
0
20
LSB
Offset (inputs using resistive scalar)
–9
0
9
LSB
Offset (other inputs without scalar)
–9
0
9
LSB
LSB
Turn on/off time
Gain error (without scalar)
Offset (inputs using opamp-based
scalar)
Channel 11 (ICHG)
Offset drift (after trimming)
Temperature and supply
–1
0
1
Gain error drift (including reference
voltage)
Temperature and supply
–0.6
0
0.2
Integral nonlinearity
Best fitting
–2
0
2
LSB
–2
0
2
LSB
Differential nonlinearity
GPADC_IN# input impedance
100
Input capacitor Cbank
MΩ
12
Maximum source input resistance
RS (for all internal or external inputs)
pF
100
GPADC voltage reference
1.25
Input range (SAR)
0
–1
Gain error of the scalar
%
0
kΩ
V
1.25
V
1
%
GPADC_IN0 current source
±5%
7
µA
GPADC_IN0 additional current
source
±5%
15
µA
THERMAL MONITORING
IQOFF
Off ground current (two sensors on
the die, specification for one sensor)
Off mode
0.1
@ 25°C off mode
0.5
IQO
On ground current (two sensors on
the die, specification for one sensor)
On mode, standard mode
On mode, GPADC measurement
7
15
25
40
µA
µA
Rising temperature
104
117
127
Falling temperature
95
108
119
Rising temperature
109
121
132
Falling temperature
99
112
123
Rising temperature
113
125
136
Falling temperature
104
116
128
Rising temperature
118
130
141
Falling temperature
108
120
132
Rising temperature
136
148
160
Falling temperature
126
138
150
POR rising-edge threshold
2.00
2.15
2.50
V
POR falling-edge threshold
1.90
2.00
2.10
V
40
150
350
mV
00 (first hot-die threshold)
01 (second hot-die threshold)
10 (third hot-die threshold)
11 (fourth hot-die threshold)
Thermal shutdown
°C
°C
°C
°C
°C
SYSTEM CONTROL THRESHOLDS
POR hysteresis
Rising edge – falling edge
VBATMIN
_LO
Threshold of switch-off (configurable
by 50-mV steps)
2.0
3.1
V
VBATMIN
_HI
Threshold of switch-on (configurable
by 50-mV steps)
2.5
3.55
V
5
8
µA
11
16
µA
CURRENT CONSUMPTION, BACKUP MODE
VBACKUP, supplied on VBACKUP
VBAT = 0 V
VBACKUP = 3.2 V
VBAT, supplied on VBAT
VBACKUP = 0 V
VBAT = 2.7 V
Copyright © 2010–2011, Texas Instruments Incorporated
29
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
30
UNIT
CURRENT CONSUMPTION, WAIT-ON STATE
VBAT = 3.8 V
µA
CURRENT CONSUMPTION, SLEEP STATE
V1V8 and VMEM enabled, no load
VBACKUP = 0 V, VBAT = 3.8V
VANA = 0 V, VAUX1 = 0 V, VAUX2
= 0 V, VAUX3 = 0 V, VCXIO = 0 V,
VDAC = 0 V VMMC = 0 V, VPP = 0
V, VBRTC = 1.8 V, VRTC = 0V,
VUSB = 0 V, VUSIM = 0 V, V1V29 =
0 V, V1V8 = 1.8 V, V2V1 = 0 V,
VCORE1 = 0 V, VCORE2 = 0 V,
VCORE3 = 0 V, VMEM = 0 V
RC6MHZ = OFF, CLK32KG = OFF,
CLK32KAUDIO = OFF VBG = ON,
VBATMIN_HI = OFF, TMP = OFF,
FG = OFF EPROM Features:
BSI_ISOURCE = OFF,
BAT_DET_EN = OFF, VMEM = 1.35
V
µA
110
The following table describes the digital input signal electrical parameters.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–0.3
0
0.35 × VBAT
V
0.65 × VBAT
VBAT
VBAT + 0.3 ≤
5.5
V
PWRON, RPWRON
Low-level input voltage VIL-related
to VBAT/VDD
High-level input voltage VIH-related
to VBAT/VDD
BOOT0, BOOT1, BOOT2, BOOT3, CHRG_EXTCHRG_STATZ, GPADC_START, MMC, MSECURE, NRESWARM, OSC32KIN, PREQ1,
PREQ2A, PREQ2B, PREQ2C, PREQ3, SIM, TESTEN
Low-level input voltage VIL-related
to VIO or VRTC
–0.3
0
0.35 × VR
V
0.65 × VR
VR
VR + 0.3
V
–0.3
0
0.3 × VIO
V
High-level input voltage VIH-related
to VIO
0.7 × VIO
VIO
VIO + 0.3
V
Hysteresis
0.1 × VIO
High-level input voltage VIH-related
to VIO or VRTC
CTLI2C_SCL, CTLI2C_SDA, SRI2C_SCL, SRI2C_SDA
Low-level input voltage VIL-related
to VIO
V
1.2-V SPECIFIC RELATED I/Os: PREQ3 (1) (2)
Low-level input voltage VIL-related
to VIO
High-level input voltage VIH-related
to VIO
(1)
(2)
–0.3
0
0.3 × VIO
V
0.7 × VIO
VIO
VIO + 0.3
V
PREQ3 can be programmed for two different input supplies (1.2/1.8 V) and, as such, has a configurable input threshold.
Applying 1.8-V input logic on the PREQ3 ball when the 1.2-V supply mode is selected does not damage the PREQ3 input buffer.
Nevertheless, because the threshold is reduced to its 1.2-V configuration, the input buffer is more sensitive to the low 1.8-V logic level.
The following table describes the digital output signal electrical parameters.
PARAMETER (1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REGEN1, REGEN2
Low-level output voltage VOL
IOL = 100 µA
0
0.1 × VBAT
0.2 × VBAT
V
High-level output voltage VOH
IOH = 100 µA
0.8 × VBAT
0.9 × VBAT
VBAT
V
BATREMOVAL, CLK32KAO, CLK32KG, INT, CHRG_EXTCHRG_ENZ, NRESPWRON, PWM1, PWM2, SYSEN
(1)
All output signals are guaranteed low when VRTC is not available, especially REGEN1, REGEN2, and SYSEN, all three of which control
some external power resources.
30
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PARAMETER (1)
MIN
TYP
MAX
UNIT
Low-level output voltage VOL-related
IOL = 2 mA
to VIO or VRTC
TEST CONDITIONS
0
0.18
0.45
V
Low-level output voltage VOL-related
IOL = 100 µA
to VIO or VRTC
0
0.09
0.2
V
VR – 0.45 (2) VR – 0.18 (2)
VR
V
VR – 0.2 (2) VR – 0.09 (2)
VR
V
V
High-level output voltage
VOH-related to VIO or VRTC
IOH = 2 mA
High-level output voltage
VOH-related to VIO or VRTC
IOH = 100 µA
CTLI2C_SDA, SRI2C_SDA
(2)
Low-level output voltage VOL-related
3-mA sink current
to VIO
0
0.1 × VIO
0.2 × VIO
Output current
0
1
3
VOL = 0.4 V
mA
VR replaces either VRTC or VIO.
The following table describes the digital output signal timing characteristics.
BALL NAME/OUTPUT BUFFER
LOAD (pF)
RISE/FALL TIME (ns)
MAX
MIN
NOM
MAX
CHRG_EXTCHRG_ENZ
35
5
10
15
INT
35
5
10
15
BATREMOVAL
35
5
10
15
NRESPWRON
35
5
10
15
PWM1
35
5
10
15
PWM2
35
5
10
15
REGEN1
35
5
15
25
REGEN2
35
5
15
25
SYSEN
35
5
10
15
5
1
6
20
4
11
35
5
15
50
8
20
VR supply output buffer
VBAT supply output buffer
CLK32KAO output buffer
CLK32KG output buffer
Copyright © 2010–2011, Texas Instruments Incorporated
5
1
9
20
3
17
35
5
25
50
6
34
5
5
15
20
8
30
35
10
45
50
15
100
31
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
OPERATION
REAL-TIME CLOCK
The RTC is driven by the 32-kHz oscillator and it provides the alarm and timekeeping functions. The RTC is
supplied by the backup battery (when available) if the main battery fails and if no external power is applied.
The main functions of the RTC block are:
• Time information (seconds/minutes/hours) in binary-coded decimal (BCD) code
• Calendar information (day/month/year/day of the week) in BCD code up to year 2099
• Programmable interrupts generation. The RTC can generate two interrupts: a timer interrupts periodically
(1s/1m/1h/1d period) and an alarm interrupt at a precise time of the day (alarm function). The timer interrupt
can be masked during the SLEEP period to prevent the host processor from waking up.
• Oscillator frequency calibration and time correction
• Other features are:
– Time mode switching between 12 h or 24 h at any time without disturbing the RTC (Read or write are
always performed with the current mode.)
– Shadow registers that can store time and date content and make it available and stable for reading
For security purpose, the registers related to time and calendar information are protected by restricting their write
access to software running in the secure mode of the host (MSECURE). Read access is always allowed even in
no secured mode.
NOTE
•
•
IT_ALARM can generate a wake-up of the platform.
IT_TIMER cannot generate a wake-up of the platform.
Date and Calendar Settings
All the time and calendar information are available in these dedicated registers, called TC registers. The TC
registers values are written in BCD code.
1. Year data ranges from 00 to 99:
– Leap years ≈ Years divisible by 4 (2008, 2012, etc.).
– Common years = other years.
2. Month data ranges from 01 to 12.
3. Day value ranges from:
– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
– 1 to 30 when months are 4, 6, 9, 11
– 1 to 29 when month is 2 and year is a leap year
– 1 to 28 when month is 2 and year is a common year
4. Week value ranges from 0 to 6.
5. Hour value ranges from 00 to 23 in 24-hour mode and from 1 to 12 in AM/PM mode.
6. Minutes value ranges from 0 to 59..
7. Seconds value ranges from 0 to 59.
To modify the current time, software writes the new time into TC registers to fix the time/calendar information
(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEARS_REG, and
WEEKS_REG). The DBB can write into TC registers without stopping the RTC. In addition, software can stop the
RTC by clearing the STOP_RTC bit of the RTC_CRTL_REG control register and check the RUN bit of the
RTC_STATUS_REG status register to ensure that the RTC is frozen. Then update the TC values, and restart the
RTC by setting the STOP_RTC bit.
32
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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NOTE
The 32-kHz second primary counter is not reset when the RTC restarts with the
STOP_RTC bit. Therefore, a maximum inaccuracy of 1s is stored in the RTC, depending
on the instant the second primary counter is stopped.
Example: Time is 10H54M36S PM (AM/PM mode set), 2008 September 5. Previous registers values are:
Table 3. Real-Time Clock Registers Example
REGISTER
VALUE
SECONDS_REG
0x36
MINUTES_REG
0x54
HOURS_REG
0x10
DAYS_REG
0x05
MONTHS_REG
0x09
YEARS_REG
0x08
Rounding
The user can round to the closest minute, by setting the ROUND_30S bit of the RTC_CTRL_REG register. TC
values are set to the closest minute value at the next second. ROUND_30S bit will be automatically cleared
when the rounding time is performed (See calendar registers, such as SECONDS_REG, MINUTES_REG, etc.,
and RTC_CTRL_REG).
Example:
• If the current time is 10H59M45S, rounding changes the time to 11H00M00S.
• If the current time is 10H59M29S, rounding changes the time to 10H59M00S.
Get Time
The GET_TIME feature loads the RTC counter in shadow registers and makes the content of the shadow
registers available and stable for reading. Shadowed registers, linked to the GET_TIME feature, are a parallel set
of calendar static registers, at the same I2C addresses as the calendar dynamic registers. The GET_TIME bit is a
self-clearing bit. Once the copy to shadow registers is executed, it is reset to 0. If the time is read without
GET_TIME, the read value comes directly from the RTC counter and software must manage the counter change
during the reading. Time reading remains always at the same address, with or without using the GET_TIME
feature.
Compensation Registers
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must respect the available access period.
These registers must be updated before each compensation process. For example, software can load the
compensation value into these registers after each hour event, during an available access period.
Figure 4 shows compensation scheduling for the RTC.
Copyright © 2010–2011, Texas Instruments Incorporated
33
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
Hours
3
Seconds
58
4
59
0
Load compensation register
Compensation event
Hours
www.ti.com
1
58
2
59
0
1
2
Load compensation register
Compensation event
3
4
Compensation
enable
Seconds
59
0
1
Hour event
Load compensation register
Compensation event
swcs045-026
Figure 4. RTC Compensation Scheduling
To compensate for inaccuracy in the 32-kHz oscillator, it is possible to balance this drift. Software must calibrate
the oscillator frequency, calculate the drift compensation versus a 1-hour period, and then load the compensation
registers with the drift compensation value. If the AUTO_COMP bit in RTC_CTRL_REG is enabled, the
RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value (in 2's complement) is added to the RTC 32-kHz counter
at each hour and 1 second. When RTC_COMP_MSB_REG/RTC_COMP_LSB_REG is added to the RTC 32-kHz
counter, the duration of the current second becomes (32768 – RTC_COMP_M/LSB_REG) / 32768 seconds;
therefore, it is possible to compensate the RTC with a 1/32768-s time unit accuracy by hour.
NOTE
The compensation is taken into account once written in the registers. When the TWL6030
device enters backup mode, the host IC must write the previously correct compensation
value.
Interrupts
Table 4. RTC Interrupts
INTERRUPT
DESCRIPTION
RTC_ALARM
RTC alarm event: Occurs at programmed date and time.
RTC_PERIOD
RTC periodic event: Occurs at programmed period of time (each
second or minute, etc.).
The RTC can generate two types of interrupts:
• Timer interrupt (RTC_PERIOD) can be generated periodically; that is, each second, minute, hour, or day
(RTC_INTERRUPTS_REG EVERY[1:0] bits). This interrupt is enabled by the IT_TIMER bit of the
RTC_INTERRUPTS_REG interrupts register. It is a negative edge-sensitive interrupt. The
RTC_STATUS_REG[5:2] bits (1D_EVENT, 1H_EVENT, 1M_EVENT, 1S_EVENT) are updated only at each
new interrupt. They present which type of events occur.
• Alarm interrupt (RTC_ALARM) can be generated when the time set into the TC alarm registers
(ALARM_SECONDS_REG,
ALARM_MINUTES_REG,
ALARM_HOURS_REG,
ALARM_DAYS_REG,
ALARM_MONTHS_REG, ALARM_YEARS_REG) is the same as in the TC registers (SECONDS_REG,
MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG, WEEKS_REG). This interrupt is
then generated if the IT_ALARM bit of the RTC_INTERRUPTS_REG interrupts register is set. This interrupt is
34
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
low-level sensitive; it indicates that an alarm interrupt occurred. This interrupt is disabled by writing 1.
NOTE
•
•
•
Both alarm (RTC_ALARM) and timer (RTC_PERIOD) interrupts can occur at the same time.
Both the primary handler and RTC IT_ALARM/IT_TIMER bits must be cleared; otherwise, they
hide new interrupt events.
Only the RTC alarm (RTC_ALARM) can wake up the TWL6030 device (see the STRT_ON_RTC
bit in the PHOENIX_START_CONDITION register).
CLOCKS
The TWL6030 device is independent of any high-frequency system clock: It provides only a 32-kHz clock to the
platform (see Figure 5). The oscillator can use an external crystal unit to generate the clock or use an external
32-kHz oscillator, in which case the internal oscillator module is bypassed.
To provide a high-performance, 32-kHz clock for the audio device (TWL6040), a dedicated output buffer is
implemented on the CLK32KAUDIO ball. This audio buffer uses the VRTC regulator as an input supply source.
The CLK32KAUDIO clock might not always be available, and its associated register configuration depends on
the platform requirements.
Higher frequencies are required for the different functions of the TWL6030 device and are generated from an
internal 6-MHz resistor-capacitor (RC) oscillator.
Copyright © 2010–2011, Texas Instruments Incorporated
35
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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32 kHz
32 kHz
crystal
oscillator
6 MHz
6 MHz
1 MHz
16 Hz
HFCLKEN
32 kHz
RC
oscillator
32 kHz
Power control
CLK32KAO
6 MHz
RC
oscillator
CLK32KG
CLK32AUDIO
Clock
generator
TCK (multiplexer or INT functionalpd)
OCP-CLK(6 MHz)
G PADC-CLK(1 MHz)
S MPS-CLK(6 MHz
3 MHz
RC
oscillator
CHG-CLK (3 MHz)
CGAUGE-CLK(32 kHz)
VIB-CLK(16 Hz)
SWCS045-027
Figure 5. Clock System Functional Description
The RC 32-kHz oscillator provides the clock during the crystal oscillator start-up phase. A 250-ms timer clocked
by the 32-kHz crystal clock controls the switching phase from RC to crystal oscillator. The crystal clock starts in
50 ms maximum. The total crystal oscillator start-up sequence is less than 300 ms. The crystal oscillator
incorporates an analog detection mechanism of the presence of the crystal. When the crystal is not visible for a
nominal period of 500 µs, the crystal oscillator is reset and the multiplexer reselects the RC 32-kHz input. The
TWL6030 device is reset with a power-on reset (POR). A crystal start-up sequence phase is reinitialized as soon
as the crystal is detected
The RC 6-MHz oscillator is principally required for the SMPS and OCP buses. If all TWL6030 groups are
configured in sleep, the TWL6030 device enters the SLEEP state. In the SLEEP state, the RC 6-MHz oscillator is
off; otherwise, the RC 6-MHz oscillator remains active. Still, if required, there is some flexibility to maintain the
6-MHz active when the TWL6030 device enters SLEEP state.
The clock generator delivers the following clocks from the RC 6-MHz oscillator:
• 6 MHz for the internal OCP bus
• 6 MHz for the seven SMPSs
• 1 MHz for the GPADC
• 32 kHz for the digital vibrator
36
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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•
16 Hz for the analog vibrator
The clock generator delivers the following clock from the 32-kHz multiplexer output (RC32K or OSC32K): 32 kHz
for the gas gauge.
NOTE
The 3-MHz charger clock is directly generated in the charger module and not from the
common clock generator.
POWER RESOURCES
The power resources provided by the TWL6030 device include inductor-based SMPSs and linear LDO voltage
regulators. These supply resources provide the required power to the external processor cores and external
components as well as to the modules embedded in the TWL6030 device.
Short-Circuit Protection
The short-circuit current limits for all LDOs and SMPS regulators embedded in the TWL6030 device are
approximately twice their respective maximum load current. For specific LDO use cases, when the output of the
module is shorted to ground, the power dissipation can exceed the 1.7-W power dissipation requirement, if there
is no continuous preventive action engaged.
The short-circuit protection scheme compares an LDO/SMPS output voltage to a reference voltage and detects a
short circuit if the regulator voltage drops slightly below its minimum output voltage (1 V for the LDO and 0.55 V
for the SMPS). A short-circuit protection scheme is included in each power resource of the TWL6030 device to
ensure that, if the output of an LDO or SMPS is short-circuited, the power dissipation does not increase
drastically.
All LDOs/SMPSs include this short-circuit protection that monitors the regulator output voltage and generates an
interrupt when a short circuit is detected (see interrupt mapping). The VRTC regulator is the unique power
resource that cannot generate an interrupt when shorted. Therefore, this regulator includes a different analog
short-circuit mechanism that does not require a switch off of the regulator.
The TWL6030 device waits for the application processor to clear the short-circuit interrupt and turn off the
associated power resource within the 10-ms default time. The short-circuit counter is configurable with 6 EPROM
bits loaded during the power-up sequence. The possible programming range is 0–640 ms in 10-ms steps. If the
interrupt is not cleared before the counter expires, the TWL6030 device switches off automatically. In parallel, the
primary watchdog can shut down the device, if the watchdog expires.
In normal use conditions, when the TWL6030 device is turned off, all LDO/SMPS resources (except
VRTC/VBRTC) are turned off and their corresponding short-circuit mechanisms are reset. If a short-circuit
condition persists in which all power resources should normally be off, the TWL6030 device does not power up
again.
SMPS Regulators
The TWL6030 device includes seven SMPSs. Three of these SMPSs have DVS capability and are SmartReflex
class 3 compatible. These three SmartReflex SMPSs provide independent core voltage domains to the host
processor. The four remaining SMPSs provide supply voltages for the host processor I/Os. Each SMPS is a
high-frequency, synchronous, step-down DCDC converter allowing the use of low-cost chip inductors and
capacitors.
Each SMPS operates at 6-MHz fixed-switching frequency and enters the power-save mode operation at light
load currents to maintain high efficiency over the entire load current. The PFM mode extends the battery life by
reducing the quiescent current to 30 µA (typical) during light load and standby operation. For noise-sensitive
applications, the required SMPS can be forced into fixed-frequency PWM mode. In shutdown mode, the current
consumption is reduced to less than 1 µA.
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TWL6030
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Each SMPS is a synchronous step-down converter operating with a 6-MHz, fixed-frequency PWM at
moderate-to-heavy load currents. At light load currents, the converter operates in power-save mode with PFM.
The converter uses a unique frequency locked-ring oscillating modulator to achieve best-in-class load and line
response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of
each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up, raising the
output voltage until the main comparator trips. The control logic then turns off the switch.
When a SMPS is not used, the SMPS input and ground must still be provided (SMPS_IN at VBAT level). The
switching node SMPS_SW can be left unconnected, but SMPS_GND and SMPS_FDBK must be tied to ground.
One key advantage of the nonlinear architecture is the absence of a traditional feedback loop. The loop response
to change in VO is essentially instantaneous, which explains its extraordinary transient response. The absence of
a traditional, high-gain compensated linear loop means that the regulator is inherently stable over a wide range of
L and CO. Each SMPS integrates two current limits, one in the P-channel MOSFET and another in the
N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel
MOSFET is turned off and the N-channel MOSFET is turned on for at least 150 ns.
With decreasing load current, the device automatically switches into pulse-skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintaining high efficiency. The converter
will position the DC output voltage approximately 1 percent above the nominal output voltage. This
voltage-positioning feature minimizes voltage drops caused by a sudden load step. When in PFM mode, the
converter resumes its operation when the output voltage trips below the nominal voltage. It ramps up the output
voltage with a minimum of three pulses and goes into PFM mode when the inductor current return to a zero
steady state. Because of the dynamic voltage positioning, in PFM mode the average output voltage is slightly
higher than its nominal value in PWM mode. During PFM operation, the converter operates only when the output
voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into PFM
mode when the output voltage exceeds the nominal output voltage.
For each SMPS, all output voltages can be selected, regardless the external devices connected to them. There is
no hardware protection to prevent software from selecting an improper output voltage that would damage the
related external equipments. The output voltage codes are described by the following equation.
Nominal voltage value = (0.6077 V + OFFSET_RW × SMPS_OFFSET bit × 0.1013V + 0.01266 V × (binary value –
00000001)) × (MULT_RW × SMPS_MULT bit × 43/21 + 1)
(1)
An extended output voltage selection mode as well as an offset application can be enabled through EPROM.
The extended output voltage codes with and without offset application are presented in Table 7 and in the
SMPS_MULT and SMPS_OFFSET registers.
The slew rate of voltage changes is controlled using a step register. For non-SmartReflex supplies, the voltage
register is used for voltage selection (for supplies having programmable output voltages). A SmartReflex
command does not change the group state.
•
•
•
•
•
NOTE
The OFFSET_RW and SMPS_OFFSET bit are part of the SMPS_OFFSET register.
The MULT_RW and SMPS_MULT bit are part of the SMPS_MULT register.
Binary code stands for the SMPS VSEL[5:0] bits.
This formula applies to all SMPSs, instantiating the same IP, for all codes from 000001
to 111001.
For the remaining codes, it is specified dedicated discrete output voltages:
– 000000 sets the output voltage to 0 V.
– 111010 to 111110 set the output voltages in the range of 1.35 – 2.1 V.
– 111111 code is reserved and must not be used.
Table 5 lists the SMPS output voltage selection code in standard mode without offset.
38
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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Table 5. SMPS Output Voltage Selection Code (Standard Mode Without Offset)
CODE
VOUT (mV)
CODE
VOUT
(mV)
CODE
VOUT (mV)
CODE
VOUT (mV)
000000
0
010000
797.6
100000
1000.2
110000
1202.7
000001
607.7
010001
810.3
100001
1012.8
110001
1215.4
000010
620.4
010010
822.9
100010
1025.5
110010
1228.0
000011
633.0
010011
835.6
100011
1038.1
110011
1240.7
000100
645.7
010100
848.2
100100
1050.8
110100
1253.4
000101
658.3
010101
860.0
100101
1063.5
110101
1266.0
000110
671.0
010110
873.6
100110
1076.1
110110
1278.7
000111
683.7
010111
886.2
100111
1088.8
110111
1291.3
001000
696.3
011000
898.92
101000
1101.4
111000
1304.0
001001
709.0
011001
911.5
101001
1114.1
111001
1316.7
001010
721.6
011010
924.2
101010
1126.8
111010
1367.4
001011
734.3
011011
936.9
101011
1139.4
111011
1519.3
001100
747.0
011100
949.5
101100
1152.1
111100
1823.1
001101
759.6
011101
962.2
101101
1164.7
111101
1924.4
001110
772.3
011110
974.8
101110
1177.4
111110
2127.0
001111
785.0
011111
987.5
101111
1190.1
111111
Reserved
•
•
•
NOTE
The VOUT values listed in this table represent nominal voltages. The total output
accuracy is –4.1% (±3.8%).
0.600 – 1.300 V voltage steps are normally used by the SmartReflex SMPS.
SMPS can be configured to any output selection code, without restriction.
The offset application feature can be unlocked by an EPROM bit and in this case the output voltage values are
as described in Table 6:
Table 6. SMPS Output Voltage Selection Code (Standard Mode With Offset)
VOUT (mV)
CODE
VOUT
(mV)
CODE
VOUT (mV)
CODE
VOUT (mV)
000000
0
010000
898.9
100000
1101.5
110000
1304.0
000001
709.0
010001
911.6
100001
1114.1
110001
1316.7
000010
721.7
010010
924.2
100010
1126.8
110010
1329.3
000011
734.3
010011
936.9
100011
1139.4
110011
1342.0
000100
747.0
010100
949.5
100100
1152.1
110100
1354.7
000101
759.6
010101
962.2
100101
1164.8
110101
1367.3
000110
772.3
010110
974.9
100110
1177.4
110110
1380.0
000111
785.0
010111
987.5
100111
1190.1
110111
1392.6
001000
797.6
011000
1000.2
101000
1202.7
111000
1405.3
001001
810.3
011001
1012.8
101001
1215.4
111001
1418.0
001010
822.9
011010
1025.5
101010
1228.1
111010
1367.4
001011
835.6
011011
1038.2
101011
1240.7
111011
1519.3
001100
848.3
011100
1050.8
101100
1253.4
111100
1823.1
001101
860.9
011101
1063.5
101101
1266.0
111101
1924.4
001110
873.6
011110
1076.1
101110
1278.7
111110
2127.0
001111
886.2
011111
1088.8
101111
1291.4
111111
Reserved
CODE
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39
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
An EPROM bit unlocks the extended output voltage feature, as listed in Table 7. In this mode, the SMPS voltage
level step is 38.1 mV. Some trimming adjustments can shift those levels up or down by one or two settings,
meaning ±9.5 mV or 19.05 mV. The resistor divider ratio is 21/64 versus the original configuration set
(SMPS_MULT).
Table 7. SMPS Output Voltage Selection Code (Extended Mode Without Offset)
CODE
VOUT (V)
CODE
VOUT (V)
CODE
VOUT (V)
CODE
VOUT (V)
000000
0
010000
2.431
100000
3.048
110000
3.665
000001
1.852
010001
2.469
100001
3.087
110001
3.704
000010
1.891
010010
2.508
100010
3.125
110010
3.743
000011
1.929
010011
2.547
100011
3.164
110011
3.781
000100
1.968
010100
2.585
100100
3.202
110100
3.820
000101
2.006
010101
2.624
100101
3.242
110101
3.858
000110
2.045
010110
2.662
100110
3.280
110110
3.897
000111
2.084
010111
2.701
100111
3.318
110111
3.936
001000
2.122
011000
2.739
101000
3.357
111000
3.974
001001
2.161
011001
2.778
101001
3.395
111001
4.013
001010
2.199
011010
2.817
101010
3.434
111010
2.084
001011
2,238
011011
2.855
101011
3.473
111011
2.315
001100
2.276
011100
2.894
101100
3.511
111100
2.778
001101
2.315
011101
2.932
101101
3.550
111101
2.932
001110
2.354
011110
2.971
101110
3.588
111110
3.241
001111
2.392
011111
3.010
101111
3.627
111111
Reserved
NOTE
The VOUT values listed in Table 8 represent nominal voltages. The total output accuracy
is –4.1% (±3.8%).
Table 8. SMPS Output Voltage Selection Code (Extended Mode With Offset)
CODE
VOUT (V)
CODE
VOUT (V)
CODE
VOUT (V)
CODE
VOUT (V)
000000
0
010000
2.739
100000
3.357
110000
3.974
000001
2.161
010001
2.778
100001
3.395
110001
4.013
000010
2.199
010010
2.817
100010
3.434
110010
4.051
000011
2.238
010011
2.855
100011
3.473
110011
4.090
000100
2.277
010100
2.894
100100
3.511
110100
4.128
000101
2.315
010101
2.932
100101
3.550
110101
4.167
000110
2.354
010110
2.971
100110
3.588
110110
4.206
000111
2.392
010111
3.010
100111
3.627
110111
4.244
001000
2.431
011000
3.048
101000
3.665
111000
4.283
001001
2.469
011001
3.087
101001
3.704
111001
4.321
001010
2.508
011010
3.125
101010
3.743
111010
4.167
001011
2.547
011011
3.164
101011
3.781
111011
2.315
001100
2.585
011100
3.202
101100
3.820
111100
2.778
001101
2.624
011101
3.241
101101
3.858
111101
2.932
001110
2.662
011110
3.280
101110
3.897
111110
3.241
001111
2.701
011111
3.318
101111
3.936
111111
Reserved
40
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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Soft Start
Each SMPS has an internal soft-start circuit that limits the inrush current during start up. This limits input voltage
drops when a battery or a high-impedance power source is connected to the input of the converter. The soft-start
system progressively increases the ON-time from a minimum pulse-width of 30 ns as a function of the output
voltage. This mode of operation continues for 140 µs after enable. If the output voltage does not reach its
targeted value by this time, such as in the case of heavy load, the soft-start transitions to a second mode of
operation. The converter then operates in a current-limit mode, specifically the P-MOS current limit is set to half
the nominal limit and the N-channel MOSET remains on until the inductor current is reset. After an additional 100
µs, the device ramps up to full current limit operation, providing the output voltage rises above approximately 0.7
V. Therefore, the start-up time depends primarily on the output capacitor and load current.
Inductor Selection
All step-down converters are designed to operate with an effective inductance value from 0.30 to 1.30 µH and
with output capacitors from 4 to 15 µF. The output capacitor maximum value is normally used during the start-up
phase, when the capacitor is still unbiased. The internal compensation is optimized to operate with an output
filter of L = 1 µH and CO = 10 µF. Larger or smaller inductor values can be used to optimize the performance of
the device for specific operation conditions.
The inductor value affects the following:
• Peak-to-peak ripple current
• PWM-to-PFM transition point
• Output voltage ripple
• Efficiency
The selected inductor must be rated for its DC resistance and saturation current. The ripple current of the
inductor decreases with higher inductance and increases with higher VI or VO.
In high-frequency converter applications, the efficiency is mostly affected by the inductor AC resistance (quality
factor) and, to a smaller extent, by the inductor DCR value. To achieve high-efficiency operation, special care
must be taken to select inductors featuring a quality factor above 20 at the switching frequency. Increasing the
inductor value produces lower RMS currents, but degrades the transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance and the following frequency-dependent
components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
Output Capacitor Selection
SMPS advanced fast-response voltage mode control allows the use of tiny ceramic capacitors. Ceramic
capacitors, with low ESR values, provide the lowest output voltage ripple. The output capacitor requires either an
X7R or an X5R dielectric.
NOTE
Aside from their wide variation in capacitance overtemperature, Y5V and Z5U dielectric
capacitors become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor
reactance.
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output
capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays.
Copyright © 2010–2011, Texas Instruments Incorporated
41
TWL6030
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Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR input capacitor must prevent large voltage
transients that can cause misbehavior of the device or interferences with other circuits in the system. Although a
2.2-µF capacitor is sufficient for most applications, a 4.7-µF capacitor is recommended to improve input noise
filtering.
CAUTION
Exercise caution when using ceramic input capacitors. When a ceramic capacitor is
used at the input and the power is being supplied through long wires, such as from a
wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing
can couple to the output and can be mistaken as loop instability or even damage the
part. In this circumstance, additional bulk capacitance (electrolytic or tantalum) must be
placed between CI and the power source lead to reduce ringing that can occur
between the inductance of the power source leads and CI.
VCORE1, VCORE2, VCORE3
The TWL6030 device includes three SMPS converters (VCORE1, VCORE2, and VCORE3) intended to provide
three independent core voltage domains to the host processor. All three SMPSs are buck converters with a
configurable output voltage. Default output voltage at power up is 0.95 V (EPROM settings). These three
converters are SmartReflex class 3 compliant; their output voltages are independently controlled using the
SmartReflex I2C dedicated interface (SR-I2C) or control I2C (CTL-I2C) thru registers.
VMEM
The TWL6030 device includes an SMPS buck converter VMEM dedicated to memory supply. For example, the
output voltage of this SMPS can be 1.8 V, 1.35 V, or 1.2 V.
V2V1
One SMPS V2V1 is dedicated to step the battery voltage down to a preregulated voltage of either 1.8 V or 2.1 V,
essentially to supply the TWL6040 (audio) device but also as an input for some LDOs (for example, VCXIO and
VDAC) to improve overall platform power efficiency.
V1V29, V1V8
V1V29 operates at a fixed output voltage to supply an external modem or an RF transceiver and/or 1.2-V I/Os.
V1V8 SMPS is dedicated to a 1.8-V general-purpose supply (standard I/Os, external peripheral, etc.).
When used as system 1.8-V I/Os, the TWL6030 device I/O supply (VIO ball) must be connected to V1V8.
LDO REGULATORS
All LDOs are integrated so that they can be connected to an internal preregulator, to an external buck boost
SMPS, or to another preregulated voltage source.
All LDOs output voltages can be selected, regardless of the LDO input voltage level VIN. There is no hardware
protection to prevent software from selecting an improper output voltage if the VIN minimum level is lower than
TDCOV (total DC output voltage) + DV (dropout voltage). In such conditions, the output voltage would be lower and
nearly equal to the input supply. For example, in electrical tables, only the possible input supplies, which fulfill the
electrical performances in all their ranges, are mentioned at each selected output. Software must not select the
2.5-V output voltage if the VBAT supply is used as the input voltage and VBAT is lower than TDCOV + DV.
The regulator output voltage cannot be modified on the fly, from the 1.0–2.1 V voltage range to the other 2.2–3.3
V voltage range and vice versa. The regulator must be restarted in these cases.
If an LDO is not needed and not turned-on by software or a switch-on sequence, the external components can
be removed. The TWL6030 device is not damaged by this configuration, and the other functions do not depend
on the unmounted LDOs and continue to work.
42
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
LDOs are controlled by I2C access and their output voltage can be selected in a wide range of values. The
following equation describes the relationship between the LDO output voltage and the register value.
Absolute voltage value = 1.0 V + 0.1 V × (binary value – 00000001)
•
•
(2)
NOTE
This formula applies to all general-purposes LDOs, for all codes from 00000001 to
00011000.
For the remaining codes, it is specified dedicated output voltages:
– 00000000 sets the output voltage to 0 V.
– 00011001 to 00011110 codes are reserved.
– 00011111 code sets the output voltages at 2.75 V.
Table 9. LDO Output Voltage Selection Code
CODE
VOUT(V)
CODE
VOUT(V)
CODE
VOUT(V)
CODE
VOUT(V)
00000000
0
00001000
1.7
00010000
2.5
00011000
3.3
00000001
1.0
00001001
1.8
00010001
2.6
00011001
Reserved
00000010
1.1
00001010
1.9
00010010
2.7
00011010
Reserved
00000011
1.2
00001011
2.0
00010011
2.8
00011011
Reserved
00000100
1.3
00001100
2.1
00010100
2.9
00011100
Reserved
00000101
1.4
00001101
2.2
00010101
3.0
00011101
Reserved
00000110
1.5
00001110
2.3
00010110
3.1
00011110
Reserved
00000111
1.6
00001111
2.4
00010111
3.2
00011111
2.75
•
•
•
•
•
•
•
•
NOTE
Depending on the output voltage selection code selected, the core section of the LDO
is supplied either by the VBAT level (associated VDD_B# ball) or by the LDO_IN input
supply
For all codes in the range of [1.0 - 2.1]V, the VBAT battery level is used to supply the
LDO core section
For all other codes, from 2.2V up to 3.3V, the LDO_IN power source is used to supply
the LDO core section
When Software disables the LDO, the regulator does not present any leakage, even if
there is 0V at the LDO_IN input supply ball and the output voltage selected is ≥ 2.2V
Disabling the LDO does not interact on the core supply switch selection, only linked to
the output voltage code
The output voltage selection, which also affects the core supply switch control, has to
be programmed before the regulator turn on event
The regulator output voltage cannot be modified on the fly, from the [1.0 - 2.1]V voltage
range to the other [2.2 - 3.3]V voltage range and vice-versa. The regulator must be
restarted
TWL6030 does not prevent SW for enabling the LDO, even if the LDO_IN input supply
is not present
VANA
The VANA voltage regulator is dedicated to supply the analog functions of the TWL6030 device, such as the
GPADC, gas gauge, and other analog circuitry.
VANA can be enabled and disabled individually or when associated with a power group. This power resource
control optimizes the overall SLEEP state current consumption. This regulator can be used at platform level to
supply other applications, provided they do not generate noise to the supply line and the maximum current is less
than 15 mA.
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TWL6030
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VRTC
The VRTC regulator supplies always-on functions, such as RTC and wake-up functions. This power resource is
active as soon as a valid energy source is present.
This resource has two modes:
• Normal mode when supplied from main battery and able to supply all digital part of the TWL6030
• Backup mode when supplied from either a backup battery or a main battery and able to supply only
always-on parts
VRTC supplies the digital part of the TWL6030 device. In BACKUP state, the VRTC regulator is in low-power
mode (VBRTC) and is supplied from a backup battery or main battery; the digital activity is reduced to the RTC
parts only and maintained in retention registers of the backup domain. The rest of the digital is under reset and
the clocks are gated.
In WAIT-ON state, the turn-on events and detection mechanism are also added to the previous RTC current load
and still supplied on VRTC or VBRTC.
In ACTIVE state, VRTC switches automatically into ACTIVE state (inside analog backup battery IP). The reset is
released and the clocks are available.
In SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. Still, to reduce
power consumption, VBRTC can be used instead of VRTC.
VAUX1, VAUX2, VAUX3, VMMC, VUSIM
The VMMC LDO is a programmable linear voltage converter used to power a multimedia card (MMC) slot. On
top of the normal control by the power controller, it can be turned off when card removal is detected (the
VMMC_AUTO_OFF bit in the MMCCTRL register). VMMC is based on the same GPLDO architecture as the one
used for the VAUX regulators.
Voltage regulator VUSIM is dedicated to supply removable USIM memory. In addition to the normal control by
the power controller, it can be turned off when card removal is detected (the VSIM_AUTO_OFF bit in the
SIMCTRL register).
The TWL6030 device includes three general-purpose resources (VAUX1, VAUX2, and VAUX3) to supply
external peripherals, such as camera sensors, display drivers, memories (embedded multimedia cards [eMMCs]),
and others. When not used as a supply, VAUX3 can deliver a PWM supply to drive a vibrator motor.
VCXIO, VDAC, VPP, VUSB
The VCXIO and VDAC regulators supply noise-sensitive functions; for example, the VCXIO supplies the PLLs
and MIPI® D-PHY; and VDAC can be used to supply the video DAC. Both LDOs can be preregulated by the
V2V1 SMPS.
VUSB supplies the USB PHY from the PMID node of the USB charger or from battery.
VPP supplies the host processor eFuse circuitry. The default value is 1.9 V output supply.
BACKUP BATTERY CHARGER
The TWL6030 device provides a backup mode in which a backup battery is used to power the RTC and other
secure registers when no other energy source is available. The backup battery is optional and can be
nonrechargeable or rechargeable. The rechargeable battery can be charged from the main battery using the
backup battery charger.
The backup battery charger includes two control loops (CC/CV). A current loop limits the charging current when
backup battery voltage is low and a voltage loop that gradually reduces the charging current as backup battery
voltage approaches its final value. The charge current limit is fixed and the end of charge voltage is
programmable.
The backup battery charger is enabled by software and the charging starts if the main battery voltage is 100 mV
above backup battery voltage; charging is stopped when backup battery voltage equals either the selected end of
the charge voltage level or the main battery voltage, if it is below the end of the charge level programmed. The
backup battery charge cannot start if main battery voltage is lower than VBATMIN_LO. The backup battery
switch controls when the system enters in backup mode (supplied by the backup battery).
44
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Figure 6 shows a block diagram of the backup battery charger.
VBAT
Vref
I_lim
VBACKUP
Voltage
selection
SWCS045-010
Figure 6. Block Diagram of the Backup Battery Charger
POWER MANAGEMENT
The power-management system can independently drive the power state of three different subsystems or a
combination of the three. The power-management state-machine manages the state of the different resources
included in the TWL6030 device depending on system activity and energy availability. It ensures the detection of
external or internal triggering events that initiate a change of system power state. It controls the transition
sequences required to change the system from current power state to a new power state by configuring the
resources according to the desired final power state. Configuration registers are accessible through application
software by the general-purpose I2C interface (CTL-I2C). Figure 7 shows a block diagram of the
power-management system.
Copyright © 2010–2011, Texas Instruments Incorporated
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
PREQ1
PREQ2B
PREQ2A
PREQ2C
PREQ3
BOOT[3:0]
www.ti.com
Hardware
groups
commands
PWRON
RPWRON
Phoenix
group
RTC-ALARM
VAC_DET
VBUS_DET
Hardware events
detection
Sequence arbitration
THERM_DET
Internal POR
debouncing
emergency
MBAT_PLUG
APE
group
BBAT_PLUG
Sequence
tables
NRESWARM
SDA
SCLK
Software
commands
I2C control
FSM
Modem
group
Commands
controller
Periph
group
SR_SDA
SR_SCLK
SmartReflex
software
commands
I2C
SWCS045-009
Figure 7. Power Management Architecture
46
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Resources
A resource is an element that provides the requirements to a system or subsystem to operate. Typical resources
are supplies, clocks, resets, references, and bias. Each resource can be addressed with its unique I2C address
or with the I2C-shared addresses (broadcast).
Two configurable attributes can be associated to each resource:
• A subsystem group attribute (GRP) specifying to which subsystem group the resource is associated
• A resource category attribute (CAT) specifies the category of the resource among power-providers,
power-references or clocks, resets, and comparators. This attribute is hard coded.
Each resource can be associated to one or more subsystems. Resource attributes can be hard coded or
configurable. The state of each group to which the resource belongs is stored in the group state register. A state
arbitration is made to define the current state of shared resources. The resource state versus group state can be
remapped. For example, a resource can be set ON or OFF when the group state is SLEEP.
Table 10 lists the different resource operating modes.
Table 10. Resource Operating Modes
RESOURCE
MODE
Power on
OFF: Disabled
AUTO: Enabled, adapts to load current
FORCE: Forced to active mode
REGEN1/REGEN2/SYSEN signals
DISABLE: Logic low
ENABLE: Logic high
SMPS regulators
OFF: Disabled
AUTO: Enabled (PFM/PWM operation)
FORCED PWM: Enabled, forced to operate in PWM mode
Main band gap
OFF: Disabled
ON ACCURATE: Enabled, high on accuracy
LOW POWER: Enabled, lower accuracy, low power
FAST: Enabled, filtering bypassed (used only during BOOT or
WAKEUP)
Comparators
OFF: Disabled
Thermal shutdown
ACTIVE: Enabled
System reset
ACTIVE: NRESPWRON signal active (logic high)
ON: Enabled
OFF: Disabled
RELEASED: NRESPWRON signal inactive (logic low)
Clocks and PWM1/PWM2 drivers
DISABLE: Signal delivery is gated.
ACTIVE: Signal is delivered.
Configuration registers are intended for resource configuration, while state registers are intended to manage the
resource state transition; finally, SmartReflex registers are intended to provide dynamic voltage control through
the SR-I2C. Configuration and state registers contribute to determine resource behavior. The state register
defines to which state the resource must switch and the timing for the transition. The configuration register
defines the resource behavior in a defined state. Although both types of registers can be accessed by the FSM
and the CTL-I2C, it is preferable to reserve I2C access to configuration registers and FSM access to state
registers. SmartReflex registers are accessed exclusively through the SR-I2C in applications using SmartReflex
capability.
These registers can be accessed in different ways: individual access allows the registers to be accessed through
their physical address (ID), and broadcast messages are interpreted by individual resources in function of their
configuration.
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TWL6030
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Groups
Group Definition
The ensemble of resources associated with a subsystem is a group. A subsystem is an engine running a specific
application in an independent way. In the TWL6030 device, four groups are defined: one for each subsystem and
one for the device itself:
• Group 1: Application processor group (APP)
• Group 2: Peripherals group—connectivity devices (CON)
• Group 3: Cellular modem group (MOD)
• Group 4: Phoenix power device group
The power resources can be allocated to any of the four groups by hardware or software, depending on the
resources.
NOTE
•
•
•
•
The Phoenix power device group (group 4) includes the resources common to all other groups.
Group 4 is not considered a group by itself, as are groups 1, 2, and 3, with all of the associated
register bits.
If a resource is not used, it must be unassigned from its default associated groups.
A SLEEP-to-ACTIVE transition wakes up all assigned resources of a group.
Modifying the default value of the CFG_TRANS register allows a specific resource of one group
to act differently from the other resources of the same group.
Table 11. Groups and Resources Association
RESOURCE
GROUP1 (APP)
GROUP2 (CON)
GROUP3 (MOD)
GROUP4 (PHOENIX)
SMPS REGULATOR RESOURCES
V1V29
Yes (software)
Yes (software)
Yes (software)
V1V8
Yes (software)
Yes (software)
Yes (software)
V2V1
Yes (software)
Yes (software)
Yes (software)
VCORE1
Yes (software)
Yes (software)
Yes (software)
VCORE2
Yes (software)
Yes (software)
Yes (software)
VCORE3
Yes (software)
Yes (software)
Yes (software)
VMEM
Yes (software)
Yes (software)
Yes (software)
VAUX1
Yes (software)
Yes (software)
Yes (software)
VAUX2
Yes (software)
Yes (software)
Yes (software)
VAUX3
Yes (software)
Yes (software)
Yes (software)
VCXIO
Yes (software)
Yes (software)
Yes (software)
VDAC
Yes (software)
Yes (software)
Yes (software)
VMMC
Yes (software)
Yes (software)
Yes (software)
VPP
Yes (software)
Yes (software)
Yes (software)
VUSB
Yes (software)
Yes (software)
Yes (software)
VUSIM
Yes (software)
Yes (software)
Yes (software)
LDO REGULATOR
RESOURCES
VANA
Yes (hardware)
VRTC
Yes (hardware)
CLOCK RESOURCES
CLK32DAO
Yes (hardware)
CLK32KG
Yes (software)
Yes (software)
Yes (software)
CLK32KAUDIO
Yes (software)
Yes (software)
Yes (software)
Clock resources
48
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TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 11. Groups and Resources Association (continued)
RESOURCE
GROUP1 (APP)
GROUP2 (CON)
GROUP3 (MOD)
REGEN1
Yes (software)
Yes (software)
Yes (software)
REGEN2
Yes (software)
Yes (software)
Yes (software)
SYSEN
Yes (software)
Yes (software)
Yes (software)
GROUP4 (PHOENIX)
OTHER EXTERNAL
CONTROLLED
RESOURCES
INTERNAL RESOURCES
NRESPWRON
Yes (hardware)
BIAS
Yes (hardware)
RC6MHZ
Yes (hardware)
TMP
Yes (hardware)
VBATMIN_HI
Yes (software)
Yes (software)
Yes (software)
Power States of Groups and Subsystem Groups
• NO SUPPLY state (Phoenix group only):
– Description: The system is not powered by any energy source.
– Condition: VUPR > VPOR
• BACKUP state (Phoenix group only):
– Description: The system is powered only by a backup battery.
– Activity: Minimum supply is available to maintain only the keep-alive functions in the Phoenix power device
group, such as RTC and other critical data registers and no other activity in the system.
• WAIT-ON/OFF state (Phoenix group and subsystem groups):
– Description: The system is powered by a valid energy source.
– Activity: Minimum supply is available to maintain only the keep-alive supply for the RTC and other critical
data registers. Power-management controller reset is released and the Phoenix power device group
accepts and treats triggering events (WAIT-ON); all other groups are in the OFF state.
• ACTIVE state (all groups):
– Description: The system is powered by a valid energy source.
– Activity: The Phoenix group is ACTIVE. The resources required for the group running the application are
enabled and the required power supplies are active full current capable (the other groups can remain in
SLEEP or OFF state). The system reset is released.
• SLEEP state (all groups):
– Description: The system is powered by a valid energy source. The Phoenix power device group switches
to SLEEP state when all other groups are in SLEEP state.
– Activity: Resources associated with the group are configured in low-power mode to maintain group
context.
NO SUPPLY and BACKUP are global states; that is, they correspond to a unique state of the power resources.
ACTIVE, WAIT-ON, and SLEEP are not global states and can be divided in substates; each substate
corresponds to a different state configuration of the power resources.
Transitions from the current power state to the next power state are initiated by triggering events. Triggering
events can result from user action, system activity, or a change in environmental conditions. Triggering events
are enabled or disabled, depending on the triggering conditions.
Subsystem Hardware Commands
Partial-on or partial-off events coming from subsystems (ACTIVE or SLEEP) are transmitted to the TWL6030
device using hardware signals (PREQ1, PREQ2A, PREQ2B, PREQ2C, PREQ3). The FSM conveys this
information to the resources of the subsystem group to set each resource in a state based on the subsystem
state.
Each subsystem is associated with at least one hardware signal:
• Group 1: Application processor group (APP) → PREQ1
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TWL6030
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•
•
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Group 2: Peripherals group—connectivity devices (CON) → Logical OR between PREQ2A, PREQ2B, and
PREQ2C
Group 3: Cellular modem group (MOD) → PREQ3
PREQ signals can be masked by register bits PREQ2A, PREQ2B, and PREQ2C sharing the same mask bit.
PREQ1, PREQ2A, PREQ2B, PREQ2C, and PREQ3 are supplied on the VIO voltage domain. The default
polarity of the signals is active high (group is active) and it can be selected by the register bit.
SmartReflex Software Commands
Only SMPS SmartReflex-compliant resources can be accessed by the SR-I2C. In addition to hardware
commands, SmartReflex-compliant power resources receive additional commands with the SR-I2C. These
commands affect the voltage setting of the SMPS, depending on the related voltage domain state. The slew rate
of voltage changes is controlled with a step register. For non-SmartReflex supplies, the voltage register is used
for voltage selection (for supplies having programmable output voltages). A SmartReflex command does not
change the state of the group.
Boot Pins
The TWL6030 device has four input balls (Boot[3:0]) to select boot sequence executed at startup. These balls
provide an indication on the following parameters to select the correct value for the supply voltages and detection
thresholds:
• BOOT0: Battery chemistry (cut-off voltage)
• BOOT1: LPDDR2 (voltage/sequence)
• BOOT2: eMMC (voltage)
• BOOT3: Platform (sequence)
Table 12. BOOT[3:0]
BOOT
STATE
EFFECT
0
High thresholds are selected for
VBATMIN_LO and VBATMIN_HI.
1
Low thresholds are selected for
VBATMIN_LO and VBATMIN_HI.
BOOT0
0
OMAP4430 PMIC: S4A LPDDR2 memories
are used. VMEM supplies the LPDDR2 core
at 1.35 V.
OMAP4460/4470 PMIC: VMEM is not
controlled by startup sequence.
BOOT1
1
OMAP4430 PMIC: S4B LPDDR2 memories
are used. VMEM supplies the LPDDR2 core
at 1.2 V.
OMAP4460/4470 PMIC: VMEM is turned ON
by startup sequence. Output voltage is 1.2 V
BOOT2
0
VAUX1 is used to supply eMMC at 2.8 V.
1
VAUX1 is used to supply eMMC at 1.8 V.
0
VAUX1 is disabled during power-up
sequence (pulldown asserted).
1
VAUX1 is enabled during power-up
sequence (BOOT2 configuring the voltage).
For example, see the OMAP4 power-up
sequence.
BOOT3
NOTE
•
•
OMAP4430 PMIC part numbers are TWL6030B107, TWL6030B1AE, and TWL6030B1A0.
OMAP4460/4470 PMIC part numbers are TWL6030B1A4, TWL6030B1AF, and TWL6030B1AA.
Battery Comparator Thresholds
Three thresholds of battery voltage condition the system state transitions:
50
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SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
•
•
•
POR
– Released when the energy source can supply the digital resources
– POR threshold is the minimum voltage below which the TWL6030 device is reset.
VBATMIN_LO
– Threshold of hardware switch-off
– Two values, depending on the battery technology, are stored in EPROM and selected by boot mode.
– The comparator falling-edge threshold (VBATMIN_LO) is configurable from 2.00 to 3.100 V in 50-mV
steps.
– The equivalent comparator hysteresis range is from 150 to 500 mV.
VBATMIN_HI
– Threshold of switch-on
– Checked as condition to initiate any sequence to ACTIVE state
– Two values, depending on the battery technology, are stored in EPROM and selected by boot mode.
– The comparator rising-edge threshold (VBATMIN_HI) is configurable from 2.50 to 3.55 V in 50-mV steps.
– The equivalent comparator hysteresis range is from 150 to 500 mV.
– For correct system behavior, the VBATMIN_HI threshold value must not be programmed higher than the
default charging voltage. Otherwise, the TWL6030 device does not switch on after a charger plug with
empty battery.
Depending on the battery technology used, the Phoenix power device must be configured appropriately with the
battery chemistry BOOT pin. The corresponding EPROM bits of the main battery comparators thresholds are
loaded during the Phoenix power device start-up sequence:
• The comparator rising edge threshold (VBATMIN_HI) is configurable from 2.50 to 3.550 V in 50-mV steps.
• The comparator falling edge threshold (VBATMIN_LO) is configurable from 2.00 to 3.100 V in 50-mV steps.
• The equivalent comparator hysteresis range is thus from 150 to 500 mV in 50-mV steps.
The EPROM bits stored are:
• Rising edge 16-step code for the current battery generation (6 bits)
• Rising edge 16-step code for the next battery generation (6 bits)
• Falling edge 23-step code for the current battery generation (6 bits)
• Falling edge 23-step code for the next battery generation (6 bits)
Table 13 lists the parameters for the rising edge of the VBATMIN_HI threshold.
Table 13. VBATMIN_HI Threshold
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage threshold
<001010>
2.460
2.500
2.580
V
Voltage threshold
<001011>
2.510
2.550
2.630
V
Voltage threshold
<001100>
2.560
2.600
2.680
V
Voltage threshold
<001101>
2.610
2.650
2.730
V
Voltage threshold
<001110>
2.655
2.700
2.785
V
Voltage threshold
<001111>
2.705
2.750
2.835
V
Voltage threshold
<010000>
2.755
2.800
2.885
V
Voltage threshold
<010001>
2.805
2.850
2.940
V
Voltage threshold
<010010>
2.855
2.900
2.990
V
Voltage threshold
<010011>
2.905
2.950
3.040
V
Voltage threshold
<010100>
2.955
3.000
3.090
V
Voltage threshold
<010101>
3.000
3.050
3.145
V
Voltage threshold
<010110>
3.050
3.100
3.195
V
Voltage threshold
<010111>
3.100
3.150
3.245
V
Voltage threshold
<011000>
3.150
3.200
3.300
V
Voltage threshold
<011001>
3.200
3.250
3.350
V
Copyright © 2010–2011, Texas Instruments Incorporated
51
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 13. VBATMIN_HI Threshold (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage threshold
<011010>
3.250
3.300
3.400
V
Voltage threshold
<011011>
3.295
3.445
3.455
V
•
•
•
•
•
•
NOTE
Minimum values are defined at –[1.50, 1.75]% of the nominal value.
Maximum values are defined at +[3.00, 3.25]% of the nominal value.
There is no hysteresis implemented between the rising and falling edges of the battery
monitoring comparator.
The default value is generally 3.200 V nominal (see the VBATMIN_HI_THRESHOLD
register).
For a correct system behavioral, the VBATMIN_HI threshold value must not be
programmed above 3.350 V nominal (3.455 V maximum); otherwise the Phoenix power
device will not switch on after a charger plug, battery charged up to VOREGmin =
3.465 V (3.50 V – 1%)
It is possible to configure the VBATMIN_HI threshold with the same values as
VBAT_MONITORING, if it fits the system requirements.
Table 14 lists the parameters for the falling edge of the VBATMIN_LO threshold.
Table 14. VBATMIN_LO Threshold
52
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage threshold
<000000>
2.265
2.300
2.370
V
Voltage threshold
<000001>
2.015
2.050
2.115
V
Voltage threshold
<000010>
2.065
2.100
2.165
V
Voltage threshold
<000011>
2.115
2.150
2.215
V
Voltage threshold
<000100>
2.165
2.200
2.270
V
Voltage threshold
<000101>
2.215
2.250
2.320
V
Voltage threshold
<000110>
2.265
2.300
2.370
V
Voltage threshold
<000111>
2.310
2.350
2.425
V
Voltage threshold
<001000>
2.360
2.400
2.475
V
Voltage threshold
<001001>
2.410
2.450
2.525
V
Voltage threshold
<001010>
2.460
2.500
2.580
V
Voltage threshold
<001011>
2.510
2.550
2.630
V
Voltage threshold
<001100>
2.560
2.600
2.680
V
Voltage threshold
<001101>
2.610
2.650
2.730
V
Voltage threshold
<001110>
2.665
2.700
2.785
V
Voltage threshold
<001111>
2.705
2.750
2.835
V
Voltage threshold
<010000>
2.755
2.800
2.885
V
Voltage threshold
<010001>
2.805
2.850
2.940
V
Voltage threshold
<010010>
2.855
2.900
2.990
V
Voltage threshold
<010011>
2.905
2.950
3.040
V
Voltage threshold
<010100>
2.955
3.000
3.090
V
Voltage threshold
<010101>
3.000
3.050
3.145
V
Voltage threshold
<010110>
3.050
3.100
3.195
V
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
•
•
•
•
•
NOTE
Minimum values are defined at –[1.50, 1.75]% of the nominal value.
Maximum values are defined at +[3.00, 3.25]% of the nominal value.
An hysteresis is implemented between the rising and falling edges, varying from 100
mV (VBAT = 2.050 V nominal) to 600 mV (VBAT = 3.100 V nominal).
The analog IP duplicates the VBATMIN_LO default value: <000000> and <000110>
selection codes are identical (2.300 V nominal).
Because VBAT minimum level is defined as 2.3 V through the Phoenix power IC
specification, all codes between <000001> and <000101> must not be used for the
correct operation of the device.
Reset Signals, Reset Triggers, Reset Domains
This section describes the different reset triggers and the signals related to resets.
• Power-on reset: It is triggered when a low battery and a low backup battery condition occurs. This activates
a POR that remains active until a valid energy source is detected. The POR release initiates the boot
sequence of the TWL6030 device. A delayed version of POR is used in the charger and released during boot
sequence when the resources required by the charger are available. During a POR, the TWL6030 device is in
a NO SUPPLY state.
• Warm reset (NRESWARM): The TWL6030 device detects a request for a warm reset on the NRESWARM
ball. The effect of the warm reset is to restart the system without turning off the supplies. After a warm reset,
the system is configured as it is after a first switch-on (default configuration), except that the states of all
resources are unchanged and all supply voltage values can be preserved, depending on the warm reset
sensitivity bit value (WR_S SMPS_CFG_VOLTAGE/LDO_CFG_VOLTAGE):
– All resources not included in the switch-on sequence keep the state (ON or OFF) they have just before the
warm reset.
– Depending on the sensitivity bit, those resources either keep the value they had before the warm reset or
are set to their default value.
– All resources included in the start-up sequence are restarted in any case.
During the power-on sequence, the TWL6030 device ignores the warm reset until the host processor releases
it.
Warmreset affects the POWER and CHARGER registers. Registers for other modules like the USB, FUEL
GAUGE, GPADC, and PWM are not affected by warmreset
• Software reset: A cold reset can be initiated by software through the I2C control interface. The effect of this
software reset (the SW_RESET bit in the PHOENIX_DEV_ON register) forces the TWL6030 device to
perform a switch-off sequence (go to the WAIT-ON/OFF state). This is followed by a switch-on sequence
(WAIT-ON to ACTIVE).
• Long key press: The long key press on PWRON generates a reset, thus forcing the TWL6030 device to go
into WAIT-ON/OFF state. The 10-second length is not configurable.
• Primary watchdog reset: The TWL6030 device includes a primary watchdog timer, which generates a reset
of the system in case of a software anomaly (no response, infinite loop) (the DEVOFF_WDT bit in the
PHOENIX_LAST_TURNOFF_STS register). The primary watchdog PRIMARY_WATCHDOG_CFG is
programmable from 1 to 127 seconds with a default value of 32 seconds. In case the primary watchdog
expires, it generates a reset forcing the TWL6030 device to go into the WAIT-ON/OFF state. The watchdog is
initialized to its default value when the system is in WAIT-ON/OFF state and starts when leaving the
WAIT-ON/OFF state to the ACTIVE/SLEEP states. Software cannot disable the primary watchdog, which is
possible only through EPROM for testing purposes.
• Thermal shutdown: If the die temperature gets too high, the thermal shutdown generates a reset, forcing the
TWL6030
device
into
the
WAIT-ON/OFF
state
(the
DEVOFF_TSHUT
bit
in
PHOENIX_LAST_TURNOFF_STS). See also the associated thermal shutdown registers: TMP_CFG_GRP,
TMP_CFG_TRANS, TMP_CFG_STATE, and TMP_CFG.
• NRESPWRON: The NRESPWRON output signal is the reset signal delivered to the host processor at the end
of the power-on sequence. It is released when all TWL6030 supply voltages (core and I/Os) are correctly set
up. In addition, the NRESPWRON signal can be gated until the 32-kHz crystal oscillator becomes stable
(configured through an EPROM bit). The polarity of the NRESPWRON signal is active low.
Copyright © 2010–2011, Texas Instruments Incorporated
53
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
•
•
•
•
www.ti.com
PWRON: The PWRON ball is connected to a push button to control system power on/off. An internal pullup
on the battery domain is implemented on this input. Three timers are associated with this input duration:
– A short timer of 15 ms to confirm the key press detection. This confirmation initiates a power-on sequence
or generates an interrupt, depending on the system state.
– A long timer, programmable from 50 ms to 1.55 seconds, that measures the key press. A register bit is set
if the key press duration exceeds the timer duration.
– A very long timer of 10 seconds that causes a hardware switch-off of the system PWRON detection is
performed on falling and rising edges (one interrupt line, 1 interrupt status bit). The polarity of the PWRON
signal is active-low (key pressed).
RPWRON: Similar to PWRON, RPWRON controls system power on/off. An internal pullup on the battery
domain is implemented on this input. A short timer of 15 ms is implemented to confirm detection. Confirmation
initiates either a power-on sequence or a generation of an interrupt, depending on the system state. Detection
of RPWRON is performed on falling and rising edges. The polarity of RPWRON is active low (key pressed).
REGEN1, REGEN2: The power-management FSM controls these output signals. These balls are activated
during the power-on/off sequences. The timing of activation depends on the power sequence (EPROM).
REGEN1 and REGEN2 can be used to control two different external power supplies. The polarity of these
signals is active high.
SYSEN: This output signal is controlled by the power-management FSM and is activated during the
power-on/off sequences. The timing of activation depends on the power sequence. SYSEN can be used to
control an external power supply or a slave PM device. The polarity of SYSEN is active high.
Power State-Machine
The TWL6030 FSM controls boot sequences, Phoenix group state changes, and subsystems group initialization.
The power sequencing is made through broadcast commands (several resources accessed simultaneously
through broadcast commands or individual access to a resource. The power sequences are stored in a
hard-coded table (EPROM). The FSM reacts on events, which initiates power state transitions.
•
•
Hardware events
– Starting events (going into ACTIVE state)
– Power on button (PWRON ball)
– Remote power on (accessories) (RPWRON ball)
– Battery plug (VBAT ball)
– VAC detection
– USB VBUS detection
– USB ID detection
– RTC alarm
– Stopping events (going to OFF state)
– Short PWRON key press (interrupt to host IC, which initiates switch-off)
– Long PWRON key press (hardware switch-off)
– Remote power on (RPWRON) (interrupt to host IC, which initiates switch-off)
– Primary watchdog (hardware switch-off)
– Thermal shutdown (hardware switch-off)
– Backup events (going into NO SUPPLY or BACKUP state)
– Removal of main and/or backup battery
– Low main and/or backup battery
Software events
– Stopping events (going to OFF state)
– Group DEVOFF instruction (all groups are OFF)
– Software reset (SW_RESET) (going to OFF state and then restart to ACTIVE)
Internal hardware monitors the different energy sources (main and backup) and charging sources (VAC or
VBUS). A set of comparators is dedicated to energy source selection to generate an uninterrupted power supply
(UPR) which exists as soon as a valid energy source is present. The backup battery is considered to be a valid
energy source after the first power up of the device. POR is released when UPR rises above to POR threshold
54
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
and the voltage regulator VBRTC provide a supply for the digital control, the 32-kHz oscillators and the
low-power band gap. When the main battery voltage rises above the VBATMIN_LO threshold, the digital control
enables the checks of the startup events. When a startup event is detected, a final check of the battery voltage is
done versus the VBATMIN_HI threshold to pursue the power-up sequence. When the system is active, the
comparator is available to perform checks on battery voltage. It then compares battery voltage versus a
programmable value and generates interrupts when voltage rises above and drops below the programmed
threshold. The comparator can be programmed from 2.3 to 4.6 V level in 50-mV steps. Hysteresis is
implemented between the rising and falling edges, varying from 100 mV (VBAT = 2.3 V) to 600 mV (VBAT = 4.6
V).
NOTE
•
•
•
UPR = VBAT if: (VBAT > VBATMIN_LO) + (VBAT > VBACKUP) . (VCHARGER <
VCHARGERmin)
UPR = VBACKUP if: {[(VBAT < VBATMIN_LO) . (VBAT < VBACKUP - 0.1V)] . (VCHARGER <
VCHARGERmin)} . PORZ
UPR = VCHARGER if: (VBAT < VBATMIN_LO) . (VCHARGER > VCHARGERmin)
Figure 8 shows a block diagram of the analog power control.
VAC
VBUS
Shunt
register
VEXT
VPOR
POR
Source
select
VSHUNT_MIN
UPR
DIG SUPPLY
VBRTC
VBACKUP
VREF
Backup
battery
BG
Digital powermanagement
controller
VBATMIN_LO
VBATMIN_HI
VBATMIN_LO
VBATMIN_HI
VBAT
VRTC
Main
battery
SWCS045-006
Figure 8. Block Diagram of the Analog Power Control
The boot sequence is shown in Figure 9. This monitoring validates the current state and the transitions between
the states.
Copyright © 2010–2011, Texas Instruments Incorporated
55
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
ENABLE
VBRTC
RELEASE
POR
Load boot
mode
(Boot pins)
VUPR>VPOR
NO
SUPPLY
Backup
condition
VBAT>VBATMIN_LO
or
VSHUNT>VSHUNT_MIN
VBAT>VBATMIN_LO
or
VSHUNT>VSHUNT_MIN
SET BCI
RESET
VUPR<VPOR
Load trim
data
(EPROM)
BACKUP
Backup
condition
VBAT<VBATMIN_LO
VUPR<VPOR
Backup
condition
Backup
condition
VBAT>VBATMIN_HI
WAIT-ON
RELEASE
BCI
RESET
If under
reset
LOW
SUPPLY
VBAT>VBATMIN_LO
SWCS045-007
Figure 9. Boot Sequence
NOTE
•
•
Backup condition means VBAT < VBATMIN_LO and VSHUNT < VSHUNT_MIN.
The system is in NO SUPPLY state when VUPR < VPOR.
Figure 10 shows a diagram of the power-state transition.
56
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PHOENIX
group
From any
state
T2
NO
SUPPLY
BACKUP
T1
T1
T8
WAIT-ON
OFF
All group
From any
state
T4
T4
T3
ACTIVE
Any group
T6
SLEEP
All group
T5
T7
GROUPj
Subsystem
groupi
OFF
GROUP
CMD
ACTIVE
SLEEP
SWCS045-008
Figure 10. Power-State Transition Diagram
•
Power-on transitions: T1
– System is in NO SUPPLY or BACKUP state. Connection of a valid energy source initiates the transition to
Copyright © 2010–2011, Texas Instruments Incorporated
57
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
•
•
•
•
•
•
•
58
www.ti.com
WAIT-ON state.
– Triggering event: VBAT > VBATMIN_LO
– Insertion of a charged main battery
– Precharge is active, main battery voltage rises
– Condition: VUPR > VPOR
Power-off transition: T2
– The system is in any state. Removal of all energy sources initiates a transition to NO SUPPLY state.
– Triggering event: VUPR < VPOR
– Main battery discharge or removal
– Backup battery discharge or removal
– Charger unplugged
– Condition: No more valid energy source
Switch-on transition: T3
– The system is in WAIT-ON state, able to accept a hardware switch-on condition, which initiates a
transition to ACTIVE state.
– Triggering event:
– Push button pressed and released (PWRON)
– Charging source plug (USB or external)
– RTC alarm
– Accessory plug (RPWRON)
– Insertion of a charged main battery or battery charge running (enabled by default)
– Software reset (following transition T4)
– USB ID plug insertion (disabled by default)
– Condition: VBAT > VBATMIN_HI and no thermal shutdown active
Switch-off transition: T4
– System is powered and in ACTIVE or SLEEP state. A hardware condition may initiate a transition to reach
WAIT-ON state.
– Triggering event:
– Group DEVOFF command (software) (if all other subsystems groups are OFF)
– Thermal shutdown
– Primary watchdog timer expired
– Software reset (followed by transition T3)
– Long key press (10 seconds) on PWRON
Sleep-on transition: T5
– System is powered and in ACTIVE state. A hardware condition initiates a transition to SLEEP state.
– Triggering event: Subsystem group sleep command (hardware) (PREQ# balls)
– Condition: All other subsystem groups are SLEEP or OFF.
Sleep-off transition: T6
– System is powered and in SLEEP state. A hardware condition initiates a transition to ACTIVE state.
– Triggering event:
– Subsystem group active command (hardware) (PREQ# balls)
– Warm reset (reinitialization of the TWL6030 device)
Active reset transition: T7
– System is powered and in ACTIVE state. A hardware condition initiates a reset, system remains in
ACTIVE state.
– Triggering event: Warm reset (reinitialization of the TWL6030 device)
Backup-on transition: T8
– System is powered and in ACTIVE, SLEEP, or WAIT-ON state. The detection of a low main battery
initiates the transition to BACKUP state.
– Triggering event: Battery voltage < VBATMIN_LO (discharge/removal)
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
– Condition: VUPR > VPOR
BATTERY CHARGING
The TWL6030 device has an integrated switch-mode charger to charge the battery from the USB connector.
Figure 11 shows a block diagram of the USB charging electronics.
CHRG_LED_TEST
Attach
detection
protocol
USB OTG
VBUS
Q1
CHRG_PMID
VBUS
detector
+
OVV
detector
Thermal
protector
CHRG_BOOT
Control
Q2
Ichar FB
Vsense FB
IVBUS limit
Thermal FB
CHRG_SW
CHRG_CSIN
CHRG_CSOUT
VBAT
Q3
CHRG_PGND
Charging
control and
watchdog
CHRG_AUXPWR
CHRG_VREF
Battery
temp
BSI
USB LDO
0.6 V
VUSB
DP
USB
PHY
DM
USB
charger
detection
control
CHRG_DET_N_PROG
TWL6030
power IC
Accessory
charger
adapter
detection
and ID
detection
100 mA
0.32 V
2V
ID
USB PHY
SWCS045-011
Figure 11. Block Diagram of the Battery Charger
The main features of the charger are:
• High-efficiency battery charger from the USB connector
• Interface
to
support
external
customer-specific
charger
and
to
CHRG_EXTCHRG_STATZ pin) the status of the external charge path (VAC)
• Built-in input current limiting
• Charging source voltage operating range: 4.0 to 6.3 V
• Integrated power FETs up to 1.5 A charging current
• Tolerate a voltage from –0.3 to 20 V on charger input related balls
• Programmable charge parameters:
Copyright © 2010–2011, Texas Instruments Incorporated
monitor
(through
the
59
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
•
•
•
•
•
•
•
•
•
•
www.ti.com
– Input current limit
– Fast-charge/termination current
– Charge voltage
– Input voltage collapse
– Safety timer
– Termination enable
Synchronous fixed-frequency PWM controller operating at 3 MHz with 0% to 99.5% duty-cycle
High-accuracy voltage and current regulation
Automatic high-impedance mode for low power consumption
Safety timer with reset control
Reverse leakage protection prevents battery drainage
Thermal regulation and protection
I/O overvoltage protection
Output for charging LED indicator
Automatic charge current setting (preventing charge input from collapsing) as charge time optimization
Boost mode operation for USB OTG supply (VBUS supply at 5 V/200 mA current)
The TWL6030 device supports a wide variety of rechargeable lithium-based battery technologies. Recent battery
technologies, such as Li-SiAn and LiFePo4, present a flat discharge region in the range of 3.2–3.3 V;
technologies such as LiCoO2 and LiNiMnCoO2 present a flat discharge region in the range of 3.6–3.7 V. To
support the different battery chemistries effectively, the TWL6030 device has programmable VBATMIN
thresholds.
The charging procedure consists of hardware-controlled preconditioning and precharging phases and
software-controlled full-charging phase. The charger also performs monitoring functions:
• AC charger detection
• VBUS detection
• Battery presence detection
• VBUS overvoltage detection
• Battery overvoltage detection
• Battery end-of-charge detection
• Thermal protection
• Watchdogs
Charging Phases
Preconditioning
Preconditioning is automatically enabled as soon as the charging source is detected and operates in a constant
current charging mode. During preconditioning the battery voltage is below 2.1 V (VBAT_SHORT) and the
charging current is limited to 30 mA (IBAT_SHORT). In this mode, the charger uses a linear charging operation
mode. This phase detects a defective (shorted) battery. As soon as the battery voltage is above 2.1 V, a
precharging phase is entered automatically.
Precharge Phase (Hardware Controlled)
The precharging phase is entered when battery voltage is above 2.1 V (VBAT_SHORT) and the charging source
is detected. If the charging source collapses during the precharge phase, the precharge current is automatically
reduced to a value that keeps the input voltage high enough to ensure proper operation of the precharge
circuitry.
The TWL6030 device supports two precharging modes:
• Slow constant current precharging for 2.1 V < VBAT < 3.54 V (VBUS current is limited to 92 mA from USB
standard downstream port)
• Fast constant current precharging for 2.1 V < VBAT < 3.54 V (VBUS current is limited to 470 mA and battery
charging current set to default charging current value when USB charging port detected)
60
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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Full-Charge Phase (Software Controlled)
Full-charge can start only when the battery voltage is above VBATMIN_HI, because this phase is under the
control of the host processor, and it stops when the battery voltage is below VBATMIN_LO. During this phase,
the following resources are available to control the charge process.
• Charge current set point register VICHRG[3:0] (constant current mode)
• Charge voltage set point register VOREG[5:0] (constant voltage mode)
• End of charge current set point register VITERM[2:0] (minimum current when in constant voltage mode)
• Input limit current set point register CIN_LIMIT[3:0] (maximum current drawn from charging source)
• Input voltage set point register BUCK_VTH[2:0] (VBUS voltage collapsing level)
• Charge watchdog set point (programmable up to 127 s, 32 s by default)
If the charging source collapses during the full-charge phase, the full-charge current is automatically reduced to a
value keeping the input voltage higher than the preset value, to ensure proper operation of the charge circuitry.
If the charging current termination is enabled, the charging is stopped if the current decreases below the preset
limit during constant voltage charging. This indicates the end of the charge period.
Figure 12 shows the battery thresholds.
5
System
active and
battery
full-charge
4
VBAT_MAX
VPRCH_MAX
VBATMIN_HI
Battery
precharge
3
VBATMIN_LO
Input: 92/470 mA limitation
Output: Default 3.54 V/ 500 mA
2
1
VBAT_SHORT
Battery preconditioning
30 mA
SWCS045-012
Figure 12. Battery Thresholds
Charger Controller Operation
If VAC or VBUS is detected when the battery voltage is above VPRCH_MAX, charging is enabled by the charger
controller, but gated by the USB charger and VAC charger because the voltage is above the default charging
Copyright © 2010–2011, Texas Instruments Incorporated
61
TWL6030
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www.ti.com
voltage. The TWL6030 device initiates startup and indicates the reason for the startup in a register. If the battery
voltage is between VBATMIN_HI and VPRCH_MAX, charging is started and the TWL6030 device initiates
startup. If the battery voltage is below VBATMIN_HI, charging is started and the TWL6030 device initiates startup
when the battery voltage crosses the VBATMIN_HI level. If the device is already powered on when the charger is
attached, the TWL6030 device only generates an interrupt for the software.
The simplified state transitions during charging are presented in Table 15. The gating of the charging means that
the charging is disabled but continues if the reason for the gating disappears. The charging termination means
that the charging is stopped. To continue charging, the charger must reconnect or software must enable the
charging by writing a software bit. The WD column indicates the operation of charging watchdog. The INT
column indicates the generation of the interrupt, R signifying rising edge and F signifying falling edge. In addition,
the interrupt generation can be masked for different reasons by register bits. The REGISTER RESET column
indicates which register groups are reset.
During startup charging, the charging state-machine controls the charging until software takes control over
charging by updating watchdog operation or by changing the USB charging-related current or voltage values.
The default watchdog times are selectable by EPROM bits. The watchdog time during full charge is selected by
register bits.
Table 15. Simplified State Transitions During Charging
PRECONDITIONING
OR PRECHARGE
NRESPWRON = 0
REASON
BIT/SIGNAL
PARAMETER
Charger
insertion
VBUS_DET
VAC_DET
(rising)
Charging
enabled
Charger
insertion (other
one already
attached)
VBUS_DET
VAC_DET
(rising)
VBUS charger
undervoltage
WD
INT
HW
mode
No
Charging
source
selected by
priority
Run
POOR_SRC
Gated
VBUS charger
overvoltage
VBUS_OVP
VBUS charger
overtemperature
Battery invalid
temperature
Waiting for
software
enable
SW mode
Yes
None
Charger insertion
No
Charging
continues
from the
first one
Run
Yes
None
Charger insertion,
software selects the
priority if NRESPWRON
= 1.
Run
No
Gated
Run
R/F
None
If NRESPWRON = 0,
VAC charger is enabled
after 2.5 s, if attached.
Gated
Run
No
Gated
Run
R/F
None
If NRESPWRON = 0,
VAC charger is enabled
after 2.5 s, if attached.
TH_SHUTD
Gated
Run
No
Gated
Run
R/F
None
BAT_TEMP_
OVRANGE
Gated
Run
No
Gated
Run
R/F
None
Suspend bit
SUSPEND
_BOOT = 1
62
COMMENTS
INT
BRIComp = 1
(1)
REGISTE
R RESET
WD
GPADC_IN0
line floating
VBUS
termination
current triggers
(enabled by bit)
FULL CHARGE
NRESPWRON = 1
VITERM [2:0]
TERM = 1
Gated
Run
No
N/A
Gated
Run
No
Gated
Run
Yes (1)
None
Battery pack removal
detected. If battery
voltage falls below
VBATMIN_LO,
NRESPWRON is set to
low.
Gated
Run
No
None
Applies to VBUS charger
only
Gated
Run
Yes
None
End-of-charge indication;
disabled by default by
EPROM.
BATREMOVAL also.
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 15. Simplified State Transitions During Charging (continued)
PRECONDITIONING
OR PRECHARGE
NRESPWRON = 0
REASON
BIT/SIGNAL
PARAMETER
Error in external
charging
Charging
source
changed after
2.5 s if the
other one is
CHRG_VAC_S
available;
TATZ = 1
otherwise,
charging is
gated by the
external
charger.
Charger
removal (one
charger
attached)
VBUS_DET or
VAC_DET
Terminated
(falling)
Charger
removal (both
chargers
attached, the
enabled one is
removed)
Charging
VBUS_DET or continues
VAC_DET
from the
(falling)
remaining
charger
Charger
removal (both
chargers
attached, the
enabled one is
removed)
VBUS_DET or
Charging
VAC_DET
continues
(falling)
NRESPWRON
falling edge
WD
FULL CHARGE
NRESPWRON = 1
INT
WD
No
Gated by
external
charger
No
Run
Run
Run
COMMENTS
INT
Software checks the
reason and determines
the operation. The error
can be:
- VAC overvoltage
- SLEEP state
- Bad adaptor
- Battery overvoltage
- Thermal shutdown
- Timer fault
- No battery
Yes
None
Terminated
Yes
Charge
group
Charger removal
No
Terminated
Yes
Charge
group
To continue charging
from the other charger,
software must enable it.
No
Charging
continues
Yes
None
NRESPWRON
N/A
(falling)
Run
REGISTE
R RESET
Run
Terminated
No
All
Primary
watchdog
expires
N/A
32-kHz crystal
oscillator stops
Terminated
No
Terminated
No
All
Charging
watchdog
expires
Terminated
No
Terminated
Yes
Charge
group
The reasons can be:
- Shutdown (software
initiated)
- Software reset
- Battery voltage
dropping below
VBATMIN_LO
- Primary watchdog
expiration
- TWL6030 thermal
shutdown
- Long key press
Sets NRESPWRON to
low
N/A
Battery voltage
dropping below
VBATMIN_LO
VBATMIN_LO
N/A
(falling)
Sets NRESPWRON to
low
TWL6030
thermal
shutdown
THPROT = 1
N/A
Sets NRESPWRON to
low
Warm reset
NRESWARM
N/A
Terminated
Watchdog reset
WDG_RST or
WDT [6:0]
N/A
Continued
Copyright © 2010–2011, Texas Instruments Incorporated
WDT[6:0]
No
All
Is loader software
executed here? Limit
register reset.
No
None
Watchdog in software
mode. Software takes
control over charging.
63
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 15. Simplified State Transitions During Charging (continued)
PRECONDITIONING
OR PRECHARGE
NRESPWRON = 0
REASON
BIT/SIGNAL
PARAMETER
VBUS
current/voltage
setting change
VICHRG [3:0]
or VOREG
[5:0]
N/A
Enable charging
by software
EN_CHARGE
R=1
Disable
charging by
software
EN_CHARGE
R=0
WD
FULL CHARGE
NRESPWRON = 1
INT
REGISTE
R RESET
WD
INT
Continued
Run
No
None
N/A
Charging
enabled
WDT[6:0]
No
None
N/A
Terminated
No
Charge
group
COMMENTS
Watchdog in software
mode. Software takes
control over charging.
Anticollapse Loop
The analog anticollapse loop operates so that the input voltage is monitored continuously and the charging
current is set by analog loop to maintain the defined input voltage.
Battery Temperature Measurement
The battery temperature is measured using an external NTC resistor. The measurement is enabled before the
charging starts and the temperature is constantly monitored during charging. If the battery temperature is outside
the valid range, the charging is gated; if the temperature returns inside the valid range, the charging continues. If
a battery dies, the battery temperature is monitored so that the charging does not start if the temperature is
outside the valid range. The gating of the charging can be disabled with an EPROM bit if needed.
The module is enabled if VBUS or an external charger is detected. An interrupt is always generated when the
battery temperature crosses the temperature limits in both directions. The interrupt generation can be masked if
needed.
Figure 13 shows the battery temperature measurement circuitry.
64
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
VBG
GPADC_VREF1
Register (loaded
from EPROM) and
decoding
Ratio-TLO
Mux
TLO
RX
GPADC_IN1
Ratio-THI
Mux
THI
VREF_ADC
RY
RTH
GPADC
GPADC_GND
SWCS045-013
Figure 13. Battery Temperature Measurement
Because the NTC characteristic is highly nonlinear, it is combined with two resistors allowing linearization of its
characteristic and making the sensitivity of the system more constant over a wide temperature range. The
resulting voltage at GPADC_IN0 can be measured using the GPADC and is also monitored by two comparators
that enable the charge of the battery only when the temperature is within a specified window, typically 0°C to
60°C. Resistors RX and RY are used to set the desired temperature threshold levels.
Charging Watchdog
The charging watchdog time depends on the charging control mode and on the USB charger detection result.
During hardware-controlled charging, the watchdog time for the USB charging port is approximately 6 minutes for
the USB standard downstream port and approximately 14 minutes for a customer-specific charger. Longer values
can be selected with the EPROM bit: 11 minutes instead of 6 minutes and 29 minutes instead of 14 minutes.
Charger source dependency on WDG values can be enabled and disabled by EPROM. If disabled, the WDG
value is always set as for the USB standard downstream port and for the customer-specific charger (longer WDG
value). During software-controlled charging, software can select the watchdog time up to 127 seconds. The
transition from hardware-controlled charging to software-controlled charging occurs when software updates the
WDG_RST, WDT[6:0], VICHRG[3:0], or VOREG[5:0] bits. The different watchdog times are summarized in the
following table.
Copyright © 2010–2011, Texas Instruments Incorporated
65
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
EPROM
(CHARGING
SOURCE
DEPENDENCY)
CHARGING
SOURCE
CHARGING
CONTROL
EPROM
(WDG VALUE)
WATCHDOG TIME
1
USB charging port
Hardware
0
5 min 4 s
5 min 36 s
1
Others
Hardware
0
13 min 13 s
14 min 15 s
1
USB charging port
Hardware
1
10 min 10 s
11 min 12 s
1
Others
Hardware
1
26 min 26 s
28 min 29 s
0
Hardware
0
13 min 13 s
14 min 15 s
0
Hardware
1
26 min 26 s
28 min 29 s
Software
(programmable)
X
0
127 s
All
MIN
MAX
Limit Registers
During full-charge phase, software sets the charging voltage and current. However, the TWL6030 device limits
the current and voltage to a level that is defined in the limit registers. The limit registers in the TWL6030 device
must be written just after the startup. Software must check the battery type and define the maximum charging
current and voltage for the battery being used, write the limit values, and lock the limit registers with the
LOCK_LIMIT register bit, so that these cannot be changed when the device is powered on. The limit values are
reset during power off by the NRESPWRON signal and they must be written by software during every power up.
This ensures that third-party software or a virus cannot set a charging current or voltage that is too high.
Battery Presence Detector
The TWL6030 device supports battery detection. The presence of the battery can be detected with the
GPADC_IN0 input signal. The interface has two different functions:
• Detect battery removal/presence
• Measure the size of the resistor connected to the GPADC_IN0 line in the battery pack using the GPADC
Battery pack removal is detected by a comparator that monitors GPADC_IN0. The battery pack must have a
pulldown resistor (RBRI) and the TWL6030 device has a current source (IBRI) in the line. If the battery pack is
removed, GPADC_IN0 rises above the comparator threshold level, the battery removal is detected, and the
TWL6030 device sends an indication to the host processor. In addition, battery charging is terminated if the
battery is not present. Battery removal is detected with a comparator and a current source is supplied on the
VRTC supply domain. This supply scheme allows the detection in a dead battery case configuration, because the
VRTC can be supplied from the VBUS or VAC lines. The battery presence detection module is enabled during
the charging and during the ACTIVE and SLEEP states.
Figure 14 shows a block diagram of the battery presence detection module.
VRTC
GPADC_IN0
IBRI
VBRIRef
BATREMOVAL
RBRI
SWCS045-014
Figure 14. Battery Presence Detector
Indicator LED Driver
The TWL6030 device has an indicator LED driver that indicates charging is ongoing during hardware-controlled
66
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
www.ti.com
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
charging. During hardware-controlled charging, the LED driver is enabled only if the USB charger or external
charging IC is charging the battery, and it is turned off if the battery is not charged (for example, because of
charger overvoltage). The supply for the charging indicator LED driver is generated from CHRG_PMID or VAC,
depending on the active charging path. The CHRG_PMID pin is used instead of the VBUS line so that the LED
indicator current is included into the VBUS input current limit.
During power on, software can control the indicator LED regardless of the charging. The supply for the LED can
be selected as CHRG_PMID, VAC, or CHRG_LED_IN. The current level can also be selected and the dimming
function can be used. Dimming is done with a 128-Hz PWM signal, which has 255 linear steps. The LED output
pin has a selectable pulldown when the module is disabled; the pulldown is enabled by default.
BOOST mode
For OTG operation, the TWL6030 device can supply VBUS (5 V) in boost mode. In this mode, the TWL6030
device delivers up to 200 mA current to the USB connector. Boost mode can be enabled through register access
by writing OPA_MODE in the CHARGERUSB_CTL1 register. In VBUS supply generation mode, the TWL6030
device can detect a short circuit in the VBUS line. If a short circuit is detected, the VBUS voltage generation
stops and an interrupt is generated to the host processor.
Supported Batteries
TWL6030 supports the following battery technologies:
• Li-Ion
• Li-Ion polymer
• Cobalt-Ni-Manganese
• LiCoO2
• LiNiMnCoO2
• Li-SiAn
• LiFePo4
Recent battery technology such as Li-SiAn and LiFePo4 presents a flat discharge region in the range of 3.2–3.3
V; technologies such as LiCoO2 or LiNiMnCoO2 presents a flat discharge region in the range of 3.6–3.7 V. This
results in different VBATMIN thresholds, depending on the type of battery used in the system. As a
consequence, the VBATMIN thresholds are programmable.
Supported Charging Sources
The following chargers are supported with the integrated switch-mode charger from the USB connector:
• Dedicated charging port
• Charging downstream port
• Charger full-filling specification YD/T 1591-2006
To configure the charger for proper operation mode depending on the charging source characteristics, the
charging source type must be detected and identified. The detection of the charger attached to the USB
connector is made inside the TWL6030 device by detecting a voltage greater than VINmin on charger input.
To minimize the capacitance of the data lines, the type of the charger connected to the USB connector can be
identified by the USB PHY, and the information of the maximum current drawn from the charging source must be
transmitted to the TWL6030 device with a dedicated signal. The TWL6030 device enables detection by delivering
VUSB supply. The charger detection circuitry must deliver a CMOS level (VUSB) signal to the TWL6030 device,
CHRG_DET_N, by default a high logic level indicating that USB charging port is detected. The polarity of the
charger detection signal can be selected with an EPROM bit. The identification of the accessory charger adapter
(ACA) occurs in the TWL6030 device.
The TWL6030 device can be interfaced with an ACA (external to the terminal) to support the charging from the
USB charger and USB communication to other USB devices from the USB port. See the USB OTG section for a
description of ACA detection.
Copyright © 2010–2011, Texas Instruments Incorporated
67
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Support for External Charging IC
The TWL6030 device can be interfaced with an auxiliary stand-alone charger device to support the following use
cases:
• Simultaneous battery charge from a non-USB charger (different connector) and OTG operating mode (the
TWL6030 device internal USB charger used as VBUS supply)
• Charging from the sources not connected to USB connector
Figure 15 shows an example of an external charging IC supported by the TWL6030 device.
Application
processor
VAC
INT
Charging
control and
watchdog
I2C
VAC
detector
Battery
temp
VAC
detector
+
OVV
detector
NRESPWRON
Thermal
protector
Control
Ichar FB
Vsense FB
Thermal FB
Isense
CHRG_EXTCHRG_ENZ
BDET
TWL6030
power IC
CHRG_EXTCHRG_STATZ
Vsense
Control
and
watchdog
VBAT
External charging IC
BQ24156
SWCS045-015
Figure 15. External Charger Interface
The external charging IC is enabled with 1.8-V CMOS level signal, CHRG_EXTCHRG_ENZ. Low logic level
indicates that charging is enabled. Charging status is indicated with the CHRG_EXTCHRG_STATZ signal. The
external charging IC pulls the signal down during charging.
The integrated USB charger can be associated with an external VAC (wall) charger. For that reason, VAC wall
charger input is connected to the TWL6030 device to define the charge priorities:
• When the VBUS is detected and the VAC is not detected, the USB charge starts.
• When the VAC is detected and the VBUS is not detected, the external charging starts.
• When the VBUS and VAC are detected, the USB charge starts only if the CHRG_DET_N pin is set high so
the USB charge has a 475-mA input current limitation.
– When CHRG_DET_N = 0 (100-mA input current USB limitation), the VAC wall charger is expected to be
better (or equivalent) and thus is chosen as the default charge path.
– When CHRG_DET_N = 1 (500-mA input current USB limitation), the precharge associated with a USB is
expected to be sufficient for battery-level quick recovery if the USB charge path is chosen.
If there is fault condition on a charger during hardware-controlled charging and the fault condition continues at
least 2.5 s, the charging source is changed for lower-priority charger. The change into lower-priority charger only
prevents the infinite looping between chargers. If only one charger is attached, the charger is not disabled in fault
condition and if the fault condition does not disappear, the charging is terminated when the watchdog expires.
USB OTG
The TWL6030 device supports the Battery Charging Specification Revision 1.1 and both OTG 1.3 and OTG 2.0
standards. The OTG revision number is hardware predefined by an EPROM bit.
68
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
www.ti.com
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
The TWL6030 device embeds all hardware analog mechanisms associated to VBUS and ID lines. The other
aspects of the OTG system, such as the OTG controller (hardware/software) or the USB data line (DP/DM) with
HNP and SRP signaling, are embedded in the USB PHY, which can be either integrated into application
processor or there is stand-alone USB OTG PHY. Equally, the other aspects of Battery Charging Specification
Revision 1.1 relative to DP and DM pins are embedded in the USB PHY.
The TWL6030 device supports the following functions:
• OTG Revision 1.3:
– USB VBUS detections (comparators and associated interrupts):
– OTG A-device (VA_VBUS_VLD, VA_SESS_VLD)
– OTG B-device (VB_SESS_VLD, VB_SESS_END)
– OTG A-device 5-V VBUS power supply provider
– OTG B-device USB Session Request Protocol (SRP) – VBUS pulsing method:
– VBUS charge mode (VBUS_CHRG_VBAT, VBUS_CHRG_PMID)
– VBUS discharge mode (VBUS_DISCHRG)
– USB ID detections (comparators and associated interrupts):
– OTG A-device (ID_GND)
– OTG B-device (ID_FLOAT)
• OTG Revision 2.0:
– USB VBUS detection (comparators and associated interrupts):
– OTG A-device/OTG B-device (VOTG_SESS_VLD)
– OTG A-device (VA_VBUS_VLD)
– OTG A-device 5-V VBUS power supply provider
– Embedded attach detection protocol (ADP) mechanism (comparators and associated interrupts):
– OTG A-device/OTG B-device ADP probing:
– VBUS charge mode (VBUS_IADP_SRC)
– VBUS discharge mode (VBUS_IADP_SINK)
– VBUS probe measurement (VADP_PRB)
– OTG B-device ADP sensing (VADP_SNS)
– USB ID detections (comparators and associated interrupts):
– OTG A-device (ID_GND)
– OTG B-device (ID_FLOAT)
• Battery Charging Specification Revision 1.1:
– USB ID detections for ACA (comparators and associated interrupts):
– OTG A-device (ID_GND)
– ACA pulldown, OTG A-device (ID_A)
– ACA pulldown, OTG B-device cannot connect (ID_B)
– ACA pulldown, OTG B-device can connect (ID_C)
– OTG B-device (ID_FLOAT)
– ID ACA mechanism available in both precharge (hardware) and SLEEP/ACTIVE states (software)
• TWL6030 additional features:
– VBUS wake-up detection (VBUS_WKUP) (maskable/rising edge)
– VBUS overvoltage detection (always on, combined with charger IP)
– VBUS precharge (combined with charger IP)
– ID wake-up detection (ID_WKUP) (programmable, disabled by default)
– ID pulldown (ID_GND_DRV), pullups (ID_PU_220K, ID_PU_100K)
– ID current sources (ID_SRC, ID_WKUP_SRC)
– GPADC VBUS monitoring (VBUS_MEAS)
– GPADC ID monitoring (ID_MEAS)
Copyright © 2010–2011, Texas Instruments Incorporated
69
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
There are two types of VBUS and ID comparators, referred to throughout this section as wake-up (normally used
in TWL6030 SLEEP state) and active comparators (generally activated in TWL6030 ACTIVE state). Use of these
comparators is not exclusive to TWL6030 SLEEP and ACTIVE states, but can also serve in additional use cases.
Indeed, the wake-up comparators target low power consumption, whereas the active comparators are intended
for accurate level detection:
• The wake-up comparators operate in TWL6030 PRECHARGE, WAIT-ON, SLEEP and ACTIVE states. These
comparators can wake up the device from a SLEEP state but can also switch on the device from a WAIT-ON
state. VBUS wake-up comparator can also start the precharge, providing that all other precharging conditions
are met.
• The active comparators operate in TWL6030 SLEEP and ACTIVE states. When operating in SLEEP state, all
required power and clock resources should remain active. ID active comparators, used for ACA detection, are
automatically enabled in precharge mode; VBUS active comparators remain off.
Table 16. OTG IP Features vs Register Bits/Modes/Supplies
FUNCTION/FEATURE
REGISTER/REGISTER
BIT
OTG
REV.
TWL6030
MODE/STATE
SUPPLIES
NEEDED
Vendor ID
USB_VENDOR_ID_LSB
USB_VENDOR_ID_MSB
–
ACTIVE
VRTC
Product ID
USB_PRODUCT_ID_LSB
USB_PRODUCT_ID_MSB
–
ACTIVE
VRTC
SRP – Pulsing method
VBUS charge on VBAT
VBUS_CHRG_VBAT
1.3
ACTIVE
VRTC
VBAT
SRP – Pulsing method
VBUS charge on PMID
VBUS_CHRG_PMID
1.3
ACTIVE
VRTC
CHRG_PMID
SRP – Pulsing method
VBUS discharge
VBUS_DISCHRG
1.3
ACTIVE
VRTC
ADP – Probing
VBUS charge
VBUS_IADP_SRC
2.0
ACTIVE
VRTC
VANA
ADP – Probing
VBUS discharge
VBUS_IADP_SINK
2.0
ACTIVE
VRTC
VBUS detection
VBUS_ACT_COMP
1.3
2.0
SLEEP
ACTIVE
VRTC
VANA
Always enabled if VBUS
or VAC is present
–
PRECHARGE/OFF
SLEEP/ACTIVE
VRTC
VBUS GPADC
measurement
VBUS_MEAS
–
ACTIVE
VRTC
VANA
ID 220-kΩ pullup on
VUSB
ID_PU_220K
–
ACTIVE
VRTC
VUSB
ID 100-kΩ pullup on
VUSB
ID_PU_100K
–
ACTIVE
VRTC
VUSB
ACTIVE
VRTC
VBUS wake-up detection
ID ground drive
ID_GND_DRV
ID 16-µA source current
ID_SRC_16U
BC
1.1
PRECHARGE
SLEEP/ACTIVE
VRTC
VUSB
ID 5-µA source current
ID_SRC_5U
–
ACTIVE
VRTC
VUSB
ID_ACT_COMP
BC
1.1
PRECHARGE
SLEEP/ACTIVE
VRTC
VUSB
ID_WK_UP_COMP
–
OFF
SLEEP/ACTIVE
VRTC
ID_MEAS
–
ACTIVE
VRTC
VANA
ID detection
ID wake-up detection
ID GPADC measurement
70
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
NOTE
•
•
•
•
•
•
•
•
•
•
•
The VBUS and ID wake-up comparators are a start event condition when the TWL6030 device is
in WAIT-ON state. If VBUS wake-up enable is fixed, ID wake-up enable is configurable and
disabled by default. Those comparators can also make the TWL6030 device leave SLEEP state
and enter ACTIVE state. An interrupt is always sent to the host processor, but only if the masks
are not applied.
In PRECHARGE state, the VBUS wake-up comparator, the VUSB regulator, the ID comparators,
and the 16-µA current source are enabled automatically by both OTG and PM state-machines.
The ACA identification is required by the charger FSM for the allowed current charges whether
an ACA is attached or not.
The OTG_REV bit unlocks the respective VBUS detection features and associated electrical
parameters specific to each OTG revision 1.3 and revision 2.0 (see the VBUS_ACT_COMP bit).
For all USB OTG registers, two informative additional rows (OTG 1.3/OTG 2.0) describe if the
bits have an application use for each OTG revision.
All TWL6030 OTG registers are unlocked and operate either with a read/write (R/W) access or
with a read/set/clear (R/S/C) process.
VBUS_ACT_COMP (USB_VBUS_CTRL_SET/USB_VBUS_CTRL_CLR) is the only R/W bit that
relies on the OTG_REV EPROM value. This bit enables the needed VBUS comparators,
reducing the power consumption of the OTG VBUS analog section. Therefore, all deactivated
comparators have their corresponding source and latch registers fixed at 0.
For some of the analog electrical parameters that are not backward-compatible between OTG
revision 1.3 and OTG revision 2.0 but also are not manageable through the OTG_REV
preselection bit, it is assumed throughout this section that the OTG revision 2.0 characteristic
limits supersede the OTG revision 1.3 electrical limits and, thus, OTG 2.0 is the reference.
OTG revision 1.3 devices have just emerged on the electronic market and should be
outnumbered shortly by OTG revision 2.0 devices.
In addition, the USB-IF consortium suggests a fast-forward transition to OTG revision 2.0 to
solve current incompatibilities and limitations between OTG revision 1.3 devices.
All electrical parametric deviations from OTG revision 1.3 are explicitly highlighted through this
section.
The full list of nonbackward-compatible electrical parameters is available on the USB-IF website
in the developer forum section.
ID Line
The USB Battery Charging Specification describes the operation of ACA detection. This refers to detection of
external RID_A, RID_B, and RID_C resistors on ID pin. ID ground ®ID_GND) and ID float ®ID_FLOAT) are related to
the connections of the USB OTG standard plugs. Note that when any one of the RID_A, RID_B, or RID_C
resistances is presented at the ID pin, this implies that VBUS supply is provided by the ACA. Thus after wake up
from VBUS or ID plug detection (due to VBUS or ID wake-up comparators controlled by ID_WK_UP_COMP,
VBUS_WK_UP_COMP register bits), software can then enable the ID active comparators to correctly identify
which of the different RID values is present. In addition, an interrupt is generated if the resistance on the ID ball
changes.
During hardware-controlled charging, the TWL6030 device monitors if an ACA is connected and sets the
corresponding VBUS input current limit.
The following pullup and pulldown resistors and current sources can be connected to the ID line:
• ID_PU_220K register bit enables an ID 220-kΩ pullup to VUSB supply.
• ID_PU_100K register bit enables an ID 100-kΩ pullup to VUSB supply.
• ID_GND_DRV register bit enables an ID 10-kΩ pulldown.
• ID_SRC_16U register bit enables an ID 16-µA current source on VUSB supply.
• ID_SRC_5U register bit enables an ID 5-µA current source on VUSB supply.
• ID_WK_UP_COMP enables an ID 9-µA current source (IID_WK_SRC) on VRTC supply.
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The ID wake-up comparator is used when the TWL6030 device is in WAIT-ON or SLEEP state. It allows the start
up of the TWL6030 device when a USB cable A-plug is attached; that is, when a pulldown resistor to ground
(ROTG_A) is present on the ID line.
Four comparators, supplied by the VUSB regulator, are implemented to evaluate the external ID resistance.
Additional logic between those comparators allows the generation of five debounced interrupts (with fixed 30-ms
debouncing) as shown in Figure 16.
VUSB
ID_SRC_16UA
ID_FLOAT
ID
Comp #4
VID_COMP3
Comp #3
VID_COMP2
Comp #2
VID_COMP1
Decoder/Debounce
VID_CMP4
ID_A
ID_B
ID_C
ID_GND
Comp #1
RID
OTG_ID
Figure 16. ID Resistance Detection
Interrupts are generated based on the conditions listed in Table 17.
Table 17. Interrupt Generation Conditions
ID PIN LEVEL
GENERATED INTERRUPT
ID_GND
ID_C
ID_B
ID_A
ID_FLOAT
VID < VID_CMP1
1
0
0
0
0
VID_CMP1 < VID < VID_CMP2
0
1
0
0
0
VID_CMP2 < VID < VID_CMP3
0
0
1
0
0
VID_CMP3 < VID < VID_CMP4
0
0
0
1
0
VID > VID_CMP4
0
0
0
0
1
It is possible to use the GPADC to monitor the voltage on the ID line (channel 14). A 6.875-V maximum voltage
on the ID line corresponds to a 1.25-V maximum dynamic at the input stage of the GPADC converter, allowing a
6.0-V maximum measurement.
VBUS Line
The VBUS wake-up comparator is used when the TWL6030 device is in PRECHARGE, WAIT-ON, SLEEP, or
ACTIVE state. It allows startup of the TWL6030 device when a USB cable plug is attached; that is, when a VBUS
voltage level of 3.6 V minimum is present on the VBUS line.
The VUSB regulator can be enabled or disabled by the VBUS wake-up comparator until the first I2C write access
to the VUSB resource state register (VUSB_CFG_STATE). Note that the VUSB regulator is controlled by the
VBUS wake-up comparator only when the NRESPWRON signal is low.
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The ACA comparators and 16-µA current source can be enabled or disabled by the VBUS wake-up comparator
until the first I2C write access to the OTG corresponding registers. Note that ACA feature is controlled by the
VBUS wake-up comparator only when NRESPWRON signal is low.
The following pullup and pulldown resistors and current sinks/sources can be connected to the VBUS line:
• VBUS_CHRG_VBAT bit enables a VBUS 2-kΩ pullup to the VBAT supply.
• VBUS_CHRG_PMID bit enables a VBUS 2-kΩ pullup to the CHRG_PMID supply.
• VBUS_DISCHRG bit enables a VBUS 10-kΩ pulldown.
• VBUS_IADP_SRC bit enables a VBUS 1.4-mA current source on the VANA supply.
• VBUS_IADP_SINK bit enables a VBUS 1.5-mA current sink.
• RA_BUS_IN resistor is present permanently and is a combination of all parallel resistor bridges implemented
on VBUS in the various IPs such as backup battery, OTG, and charger.
• RVBUS_LKG represents the TWL6030 internal leakage.
Related to the OTG 1.3 revision, four comparators supplied on the VANA regulator are implemented to detect
VBUS line voltage level.
In the OTG 2.0 revision, only one comparator is required for the session valid detection (VOTG_SESS_VLD)
supplied also on the VANA domain. In addition the VA_VBUS_VLD comparator can be used to detect a possible
VBUS short-circuit condition.
The TWL6030 device embeds the OTG 2.0 optional features related to the VBUS ADP probing and sensing, via
two additional comparators supplied on VANA (VADP_PRB, and VDAP_SNS).
Seven comparators allow detection of the four OTG 1.3 and the three OTG 2.0 debounced interrupts:
• VA_VBUS_VLD (OTG 1.3/OTG 2.0) – fixed 30 ms debouncing
• VB_SESS_VLD (OTG 1.3) – fixed 30 ms debouncing
• VA_SESS_VLD (OTG 1.3) – fixed 30 ms debouncing
• VB_SESS_END (OTG 1.3) – fixed 30 ms debouncing
• VOTG_SESS_VLD (OTG 2.0) – fixed 30 ms debouncing
• VADP_PRB (OTG 2.0) – fixed 2x 30 µs debouncing
• VADP_SNS (OTG 2.0) – fixed 2x 30 µs debouncing
It is possible to use the GPADC to monitor the voltage on the VBUS line (channel 10). A 6.875-V maximum
voltage on the VBUS line corresponds to a 1.25-V maximum dynamic at the input stage of the GPADC converter,
allowing a 6.0-V maximum measurement. For more information, see GENERAL-PURPOSE ADC .
NOTE
•
•
•
•
•
•
•
•
If the system switches off, VUSB stays on if VBUS is still connected.
When NRESPWRON is released, only software accesses enable the regulator, if not previously
enabled by the VBUS wake-up comparator in PRECHARGE state.
The VUSB regulator is a dual input supply LDO. The VUSB regulator enable is independent of
the overvoltage condition.
When a VBUS overvoltage condition occurs, the CHRG_PMID input switch is automatically
opened, protecting the VUSB LDO from possible overvoltage stresses.
When neither the VBAT nor PMID input supply is selected, the VUSB LDO cannot output a
proper voltage, even if its control enable is set (see the VUSB_CFG_TRANS register).
Software should keep monitoring the VBUS overvoltage condition and turn off the VUSB
regulator when necessary.
The VBUS detection mechanism works only when VANA supply is present:
– TWL6030 SLEEP state – VANA should remain active.
– TWL6030 ACTIVE state – VANA is always on.
For ADP detection, software can use the TWL6030 embedded mechanism or directly use the
output of the comparators with their associated interrupts.
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ADP on VBUS Line
The ADP feature allows the device to detect when a remote device is attached or detached. The ADP detects the
change in VBUS capacitance that occurs when two devices are attached or detached. The capacitance is
detected by first discharging (VBUS_IADP_SINK) the VBUS line and then measuring the time it takes for VBUS
to charge to a VADP_PRB voltage level with a VBUS_IADP_SRC current source. The change in the capacitance
is detected by looking for a change in the T_ADP_RISE charge time. This operation is called ADP probing, which
is allowed only for an A-device.
If an A-device is attached to a B-device, and both support ADP features, the A-device performs ADP probing and
the B-device performs ADP sensing. During ADP sensing, the B-device searches for ADP probing activity on the
VBUS line. If ADP probing activity is detected, the B-device determines that the A-device is still attached.
As shown in Figure 17, the ADP module has timing register bits (T_ADP_HIGH, T_ADP_LOW, T_ADP_RISE),
control logic, a current source (VBUS_IADP_SRC), a current sink (VBUS_IADP_SINK), and two comparators:
ADP probing (VADP_PRB) and ADP sensing (VADP_SNS).
VBUS_IADP_SRC
Upper
limit
T_ADP_HIGH[7:0]
Lower
limit
T_ADP_LOW[7:0]
Time interval
measurement
VBUS
VADP_PRB
T_ADP_RISE[7:0]
VBUS_IADP_SINK
VADP_SNS
ADP probing and sensing
control
ADP interrupt
32.768-kHz crystal clock
ADP_MODE[1:0]
SWCS045-016
Figure 17. Attach Detection Protocol Scheme
Figure 18 shows the ADP timing diagram.
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SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
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VBUS
voltage
T_ADP_RISE
TA_ADP_PRB or TB_ADP_PRB
VADP_PRB
VADP_SNS
VADP_DSCHRG
Time
T_ADP_SINK
SWCS045-017
Figure 18. ADP Timing Diagram
ADP_MODE[1:0]
OPERATION
00
ADP digital module is disabled.
01
ADP digital module is enabled.
10
ADP probing mode as an A-device is enabled.
During ADP sensing mode, the VADP_SNS comparator is used. The digital module monitors the comparator
output to ensure that it toggles and the time duration between the rising edge of the comparator output signal is
shorter than T_ADP_SNS. If there is no new rising edge within the T_ADP_SNS period, the module generates
an ADP interrupt.
Figure 19 shows the ADP sensing timing diagram.
T_ADP_SNS
32.768-kHz crystal clock
ADP interrupt
ADP_MODE[1:0]
00
01
Comp (VADP_SNS)
SWCS045-018
Figure 19. ADP Sensing Timing Diagram
During ADP probing, the VADP_PRB comparator is used. The time interval measurement counter is reset, the
comparator is enabled and the VBUS_IADP_SINK current sink is turned on for T_ADP_SINK. The T_ADP_SINK
time is long enough to discharge the VBUS voltage below VADP_DSCHG (guaranteed by design). After that, the
current sink is turned off, the current source VBUS_IADP_SRC is turned on, and the time interval measurement
counter starts to count 32.768-kHz crystal clock cycles. When the VBUS voltage reaches VADP_PRB or the
counter value reaches 255 cycles, the current source is turned off, the time interval measurement counter is
stopped, and the comparator is disabled. If the measured time interval value is lower than T_ADP_LOW[7:0] or
higher than T_ADP_HIGH[7:0], an interrupt is generated. Software sets the limit values so that the operation
fulfills requirements of the OTG 2.0 specification. Figure 20 shows the ADP probing timing diagram.
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TWL6030
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>T_ADP_HIGH or 255*Tclk
TA_ADP_PRB or TB_ADP_PRB
32.768-kHz crystal clock
ADP interrupt
ADP_MODE[1:0]
10/11
00
00
10/11
EnaComp
T_ADP_SINK
T_ADP_SINK
VBUS_IADP_SINK
T_ADP_RISE
VBUS_IADP_SRC
Asynchronous
Comp (VADP_PRB)
SWCS045-019
Figure 20. ADP Probing Timing Diagram
GAS GAUGE
The gas gauge, also called the current gauge, measures the current from the battery or the current into the
battery. An analog-to-digital converter (ADC) (Coulomb counter) is required to measure the voltage over the
external Rsense sense resistor. This resistor is connected to the negative side of the battery. The integration
period of the ADC is programmable from 3.9 to 250 ms. The gas gauge works continuously, which means that
the new measurement starts immediately after the previous result becomes available. The averaging and the
compensation are done by the TWL6030 digital module but requires software controls.
The main features of the gas gauge are:
• Current range: ±6.2A (with 10-mΩ sense resistor)
• ADC clock frequency: 32.768 kHz
• Data size: 13 result bits + 1 sign bit, 2’s complement format (with 250-ms integration period)
• Integration periods: 250 ms (default), 62.5 ms, 15.6 ms, 3.9 ms
• Battery discharging gives negative result (sign bit = 1)
• External sense resistor is needed (will be connected the negative side of battery)
Figure 21 shows a block diagram of the gas gauge.
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TWL6030
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Battery
Li-Ion
or
Li-Pol
Autocalibration switches
GGAUGE_RESP
Digital control
Accumulator
DS Coulomb counter
13 bits
Rs
Digital filter
1 bit
13 bits+Sign
Integrator
Registers
Sample counter
GGAUGE_RESN
Calibration
Analog
Digital
SWCS045-020
Figure 21. Gas Gauge Block Diagram
Autocalibration
Autocalibration is enabled by software. During autocalibration, the gas gauge performs eight measurements so
that the inputs for the ADC are short-circuited. The result indicates the offset error of the gas gauge. The result is
stored in the CC_OFFSET[9:0] register bits and the completion of the measurement procedure is indicated with
the CC_AUTOCAL interrupt. Software must read the offset error result and use that to compensate the actual
measurement results. The CC_CAL_EN bit self clears when the calibration completes. The gas gauge must be
enabled while calibration runs. The temperature variation changes the offset error, so the recalibration is
preferred during operation.
Auto-Clear and Pause
The auto-clear function is used in the sequence of changing from one integration period to another one. Before
changing the integration period, the CC_PAUSE bit must be set to 1. Setting the CC_AUTOCLEAR bit to 1
clears the CC_OFFSET[9:0], CC_SAMPLE_CNTR[23:0], and CC_ACCUM[31:0] registers. The
CC_AUTOCLEAR bit is self-cleared once the registers are reset.
Setting the CC_PAUSE bit to 1 keeps the analog from updating the integrator, accumulator, and sample counter
registers. The integrator continues to run. If an integration period ends while the CC_PAUSE bit is 1, the value
that is normally written to these registers is lost because the next integration period starts automatically.
Dithering
The FGDITHS bit is set to 1 to enable dithering in the ADC, which keeps idle tones from being generated with a
DC input value. The FGDITHS bit is not affected by the CC_AUTOCLEAR bit. Use the FGDITHR bit to disable
the dithering. The dithering feature status is available in the FGDITH_EN bit.
Operation with Software
Software must first set the correct integration period, enable the gas gauge, and perform the calibration to derive
the offset error and use the error to make corrections to the measurement results. The gas gauge enters normal
operation automatically when calibration completes. After that, software can read the sample counter and
accumulator results and calculate the energy accordingly.
To record the current consumption waveform, software must set a timer of the integration period to read every
integration sample result. Integration register CC_INTEG[13:0] always stores the result of the last measurement.
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GENERAL-PURPOSE ADC
The GPADC consists of a 10-bit ADC combined with a 17-input analog multiplexer. The ADC implementation
consists of a successive approximation conversion. The GPADC enables the host processor to monitor a variety
of analog signals using analog-to-digital conversion on the input source. After the conversion completes, the host
processor reads the results of the conversion through the I2C interface.
The GPADC supports 17 analog inputs: 7 of these inputs are available on external balls and the remaining are
dedicated to internal resource monitoring. Three of the seven external inputs are associated with current sources
or reference voltages allowing measurements of resistive elements (battery type and temperature or other
thermal sensor). The reference voltages are available when the GPADC is enabled. The reference voltage
GPADC_REF4 can be disabled by register bit.
GPADC_IN0 is associated with a current source of 7 µA. An additional 15-µA current source can be enabled by
register bit. A comparator connected to this input is intended to detect the presence or absence of the battery
(resistance to ground < 130 kΩ). The detection result is available at the BATREMOVAL ball.
GPADC_IN1 and GPADC_IN4 are associated with a voltage reference equal to the ADC reference and are
intended to measure temperature with an NTC sensor. In addition, a detection module is connected to
GPADC_IN1 to permanently monitor the temperature and gate the charge for the battery.
The monitored internal analog parameters are:
• Main battery voltage (VBAT)
• Backup battery voltage (VBKP)
• VAC/VBUS charging source voltage
• Main battery charge current (ICHG)
• Thermal monitoring mechanisms (HOTDIE1, HOTDIE2)
• USB OTG ID voltage level
The three external inputs associated to the current sources are:
• GPADC_IN0: Main battery type detection (identification resistor in battery pack)
• GPADC_IN1: Main battery temperature measurement (thermistor in battery pack)
• GPADC_IN4: Other resistive sensor
The conversion requests are initiated by the host processor, either by software through the I2C or by hardware
through a dedicated external ball GPADC_START. This last mode is useful when real-time conversion is
required. An interrupt signal is generated at the end-of-sequence of the conversions.
There are two kinds of conversion requests:
• Real-time conversion request (SRT)
• Asynchronous conversion request (SW)
Real-Time Conversion Request (SRT)
The GPADC is activated when GPADC_START is asserted. When this occurs, the GPADC digital control fetches
the real-time selection register to determine which channels must be sampled and converted. A sequence of
conversion consists of 1 to 17 channels to convert and processes all queued, selected channels one after
another, starting with channel 0 and ending with channel 16. At the end of each conversion, the GPADC writes
the conversion result into the corresponding results register. An INT interrupt is generated at the end of the
sequence of conversions.
If a GPADC_START real-time request occurs while a software-initiated conversion sequence is running, the
ongoing software conversion is aborted, the real-time conversion sequence is started, and a new
software-initiated conversion is rescheduled at the end of the GPADC_START sequence.
Asynchronous Conversion Request (SW)
Software can also require conversions asynchronously with respect to the GPADC_START ball for
general-purpose use. These conversion cases are not critical in terms of start-of-conversion positioning.
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General-purpose conversions do not require a result granularity in time lower than the duration of the
all-channels conversion sequences. While requiring a general-purpose conversion, there is no need to specify
channels: all channels are converted. This request is active when a write access to the toggle bit SP1 in the
GPADC register occurs, and an INT interrupt is generated after the conversion sequence. A
GPADC_START-initiated conversion (SRT) has a higher priority than the software-initiated conversions.
If a software request occurs while a GPADC_START-initiated sequence (SRT) is running, the software request is
placed on hold and the ongoing real-time sequence continues until it completes and the converted data is stored
in the real-time dedicated registers. An INT interrupt is then generated and sent to the processor. The digital
control executes the software request when the real-time sequence of conversions completes. An INT interrupt is
then generated.
Channels description
The different ADC channels are summarized in the following table.
CH
TYPE
POWER DOMAIN
SCALER
0
External
VRTC
No
Battery type, resistor value
1
External
VRTC
No
Battery temperature, NTC resistor value
2
External
Special
1.875/1.25 V
3
External
VANA
No
General purpose
4
External
VANA
No
Temperature measurement/general
purpose
5
External
VANA
No
General purpose
6
External
VANA
No
General purpose
7
Internal
8
Internal
6.25/1.25 V
Backup battery
9
Internal
11.25/1.25 V
External charger input
10
Internal
6.875/1.25 V
VBUS
11
Internal
1.875/1.25 V
VBUS charging current
12
Internal
No
Die temperature
13
Internal
No
Die temperature
14
Internal
6.875/1.25 V
USB ID line
15
Internal
6.25/1.25 V
Test network
16
Internal
4.75/1.25 V
Test network
5/1.25 V or 6.25/1.25 V
OPERATION
Audio accessory/general purpose
Main battery
NOTE
•
•
•
•
Channel 11 scalar (ICHG) is placed in the analog charger and always enabled.
Channel 11 operational amplifier and path switch is located in the analog GPADC and
controllable with the GPADC_SCALER_EN_CH11 register bit.
VANA must be on to avoid leakage on GP inputs 3, 4, 5, and 6.
It is currently not possible to measure GPADC_IN2 up to 1.25 V, without enabling the scalar first
(up to 1.875 V).
The following equation provides the relationship between TWL6030 IC die junction temperature and the GPADC
registers read data: Tj(°C) = (GPADC10CODE–671) × 0.465 + 27
with the following parameters:
• GPADC10CODE is the decimal code read from the GPADC register.
• 671 is the decimal code read from the GPADC register when the junction temperature is 27°C.
• 0.465 is the linear temperature – GPADC code coefficient.
Examples:
• Tj(–40°C) = (525-671) × 0.465 + 27 = –40.89°C
• Tj(+125°C) = (878-671) × 0.465 + 27 = 123.25°C
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VIBRATOR DRIVER AND PWM SIGNALS
Vibrator
Instead of using the VAUX3 LDO for a generic voltage supply, it can be used as a vibrator motor driver. The
output voltage of this regulator is programmable, based on a nominal 4-Hz cycle. A 16-Hz input clock is received
from the clock generator (32.768-kHz crystal clock resynchronized on the RC 6-MHz clock). The output voltage
level is through registers and the LDO can provide up to 200 mA.
The duty cycle of the nominal 4-Hz frequency is controlled through register and can be 25%, 50%, 75%, and
100%. This vibrator driver allows a soft turn on (500 µs maximum) and turn off (2 ms maximum).
Figure 22 shows a block diagram of the vibrator motor driver.
VAUX3_IN
(from the battery)
V PWL
+
–
VAUX3
SWCS045-021
Figure 22. Block Diagram of Vibrator Motor Driver
PWMs
The PWM1 and PWM2 digital outputs provide PWM signals on the 1.8-V I/O domain. Those outputs can be
active also when the system is in SLEEP state. The current drive capability of each PWM buffer is 4 mA.
Each of the PWMx ON/OFF positions is determined by the register values (PWMxON, PWMxOFF) within the
range 0–127 or 0–63.
The number of clock cycles in a PWM period has two available values:
• 64 clock cycles
• 128 clock cycles
This is controlled with the PWMx_LENGTH bit in the PWMxON register.
The clock is received only when the control bit PWMxEN is set in the TOGGLE3 register. This clock enable is
necessary for current saving when PWM is not used.
To get a clean OFF state (with reset on registers when PWM is disabled), first the PWMxR bit must be set and
then the clock can be disabled with PWMxEN.
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•
•
NOTE
The PWMx output signal is constantly ON by setting PWMxON[6:0] equal to
PWMxOFF[6:0].
The following conditions are prohibited:
– PWMx_ON[6:0] > PWMx_OFF[6:0]
– 00H ON timing setting
I28 CLK
CLK
0
1
3
2
4
5
124
125
126
127
0
1
2
3
PWM1OFF = 0x7C
PWM1ON = 0x05
OFF
ON
OFF
PWM1
PWM2ON = 0x02
PWM2OFF = 0x7F
ON
OFF
PWM2
OFF
SWCS045-028
Figure 23. PWM Timings With 128 Clock Cycles Setting
When a new ON/OFF change is applied during blinking:
• If the PWM period is programmed on 64 clock cycles and changed to get 128 clock cycles, the ongoing
counter goes up to 128, and the next PWM periods is 128 clock cycles.
• If the PWM period is programmed on 128 clock cycles, changed to get 64 clock cycles, and the counter is
below 64, the PWM period stops at 64 clock cycles. The next periods are 64 clock cycles.
• If the PWM period is programmed on 128 clock cycles, changed to get 64 clock cycles, and the counter is
above 64, the PWM period is aborted. The next periods are 64 clock cycles.
DETECTION FEATURES
The TWL6030 device supports the following detection functions:
• Detection of SIM card insertion/extraction with debouncing capability, automatic power shutdown on
extraction detection (configurable)
• Detection of MMC card insertion/extraction with debouncing capability, automatic power shutdown on
extraction detection (configurable)
• Detection of battery presence/removal
Cards Detection: SIM/MMC
The TWL6030 device provides the regulated supply voltage (VUSIM) for the SIM card and VMMC for the MMC
card and the circuitry to detect the insertion or extraction of the SIM card or MMC card. An interrupt is generated
when there is a plug/unplug detection. When the SIM card or MMC card is inserted, a mechanical contact
connected to the TWL6030 device terminal SIM or MMC is tripped and after debouncing an interrupt is
generated. The SIM card and MMC card presence detection logic must be active even when the system is in idle
mode, and then the debouncing logic (programmable) is based on the 32-kHz low-activity clock. The signal from
SIM or MMC is preprocessed depending on the detection system and on the internal pullup/pulldown
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configuration. When a card insertion is detected, the regulator VUSIM or VMMC must be enabled by software.
When a card is extracted, the corresponding regulator is turned off automatically. This functionality is still
configurable (enabled or disabled) by software. The SIM or MMC card plug is detected from any state of the chip
(WAIT-ON, SLEEP, or ACTIVE). Both card detections are always enabled and their respective interrupt can be
masked or unmasked.
Battery Removal Detection
The TWL6030 device provides the means to detect the presence or removal of the battery. The presence of the
battery is detected by a comparator associated with a current source connected to the GPADC_IN0 by sensing
the voltage on this ball (resistor to ground or open circuit R > 130 kΩ). The BATREMOVAL signal is activated
when the presence or removal of the battery is detected. Debouncing occurs on the battery detection circuitry.
This debouncing can be bypassed by a register bit (the default value is bypass). Battery detection circuitry can
be enabled or disabled by a register bit. The battery detection (default configuration) can be combined with the
SIM detection. Depending on the state of 2 register bits, the BATREMOVAL ball indicates the presence of the
battery only, the presence of SIM only, or the presence of both SIM and battery. By default, the 2 register bits are
set to indicate the battery presence only.
The polarity is defined as following:
• High level: Battery and/or SIM present
• Low level: Battery and/or SIM removed
THERMAL MONITORING
A thermal protection module monitors the temperature of the device. It generates a warning to the system when
excessive power dissipation occurs and shuts down the TWL6030 device if the temperature rises to a value at
which damage can occur.
Thus, there are two protection levels:
• Hot-die (HD) function, which sends an interrupt to software to close the noncritical running tasks
• Thermal shutdown (TS) function, which directly starts the TWL6030 device switch-off
The silicon technology used to build the TWL6030 device supports a maximum operating temperature of 150 °C.
Regarding packaging technology, a continuous operation above 125°C would require special packaging and
must be avoided to meet 100k hours lifetime.
By default, thermal protection is always enabled except in BACKUP or OFF state. It is not possible to disable it
by software in the SLEEP state.
The TWL6030 device integrates two hardware detection mechanisms to monitor and alert software that the
junction temperature is rising and must take action to reduce consumption. Those mechanisms are placed on
two opposite sides of the chip and close to the LDOs and SMPSs. Even if there are two identical thermal feature
instances on the chip, it is always considered by the specification to be unique. In addition to those HD
detections, another HD feature is embedded in the charger: The charger HD is specified in BATTERY
CHARGING and does not behave exactly the same way as described in Hot-Die Function.
Different thresholds are implemented. When a threshold is reached, an interrupt is issued. To avoid parasitic
interrupt, debouncing is implemented within the HD detection function.
The TWL6030 device integrates a thermal shutdown mechanism to shut down the device when the junction
temperature reaches a certain level to avoid irreversible die damage. The rising and falling temperature
thresholds have a difference of 10°C minimum. The HD provides some interrupt mechanism and threshold
registers to select the temperature interrupt level.
Hot-Die Function
The HD detector monitors the temperature of the die and provides a warning to the host processor through the
interrupt system when temperature reaches a critical value. The threshold value must be set below the thermal
shutdown threshold. Hysteresis is added to the HD detection to avoid the generation of multiple interrupts.
The integrated HD function provides an early warning overtemperature condition to the host PM software. This
monitoring system is connected to the interrupt controller (INTC) and can send an interrupt when the temperature
is higher than the programmed threshold.
82
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
www.ti.com
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
The TWL6030 device allows the programming of four junction-temperature thresholds to increase the flexibility of
the system: in nominal conditions, the threshold triggering the interrupt can be set from 117°C to 130°C. The HD
hysteresis is 10°C minimum in typical conditions.
When an interrupt is triggered by the power-management software, immediate action must be taken to reduce
the amount of power drawn from the TWL6030 device (for example, noncritical applications must be closed).
The interrupt generation is debounced to avoid parasitic interrupt.
Thermal Shutdown
The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at
which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status
register.
To avoid interrupts at restart, the system cannot be restarted until the die temperature falls below the HD
threshold.
The thermal shutdown monitor function is integrated to generate an immediate, unconditional TWL6030 device
switch-off when an overtemperature condition exists. This function must be distinguished with the early warning
provided to software by the HD monitor function.
In the TWL6030 device, the threshold (Tj rising) of the thermal shutdown is 148°C nominal. The thermal
shutdown hysteresis is 10°C in typical conditions. The reset generation is debounced. The thermal shutdown
function can be masked only in SLEEP state (the TMP_CFG_TRANS register) and in test mode.
CONTROL INTERFACE (I2C , MSECURE, INTERRUPTS)
I2C interfaces
The TWL6030 device provides two serial control interfaces: One is the general-purpose I2C interface (CTL-I2C)
for read-and-write access to the configuration registers of all system resources, and the other is the serial control
interface (SR-I2C) dedicated to SmartReflex applications, such as dynamic voltage frequency scaling (DVFS) or
adaptive voltage scaling (AVS).
Both control interfaces comply with the HS-I2C specification and support the following features:
• Mode: Slave only (receiver and transmitter)
• Speed
– Standard mode (100 kbps)
– Fast mode (400 kbps)
– High-speed mode (limited to 2.4 Mbps maximum)
• Addressing: 7-bit mode addressing device
They do not support the following features:
• 10-bit addressing
• General call
Copyright © 2010–2011, Texas Instruments Incorporated
83
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Single-Byte Access
A write access is initiated by a first byte that includes the address of the device (7 MSBs) and a write command
(LSB), a second byte that provides the address (8 bits) of the internal register, and the third byte that represents
the data to be written in the internal register.
A
•
•
•
read access is initiated by:
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
A second byte, providing the address (8 bits) of the internal register
A third byte, including again the address of the device (7 MSBs) and the read command (LSB)
The device replies by sending a fourth byte representing the content of the internal register.
Figure 24 shows a write access single-byte timing diagram.
S
T
A
R
T
W WA AR RR
D D DD DD DD DD DD D
A A AA AA AA AA AA R C CA AA
D D D D D D D I K D D
D
D
D
D
D
D
K7 D6
6 5 4 3 2 1 0 T
E
RR
AA
D
D5
6
RR
AA
D
D4
5
RR
AA
D
D3
DAD: Device address
R R R RA AD D DD DD D D D D A S
A A AA AC A A AA AA A A A A C T
D D D K T T T T T T T T K O
D2 D1 D0 D K7 6 T5 4 3 2 1 0
P
3 2 1 0
7
RAD: Register address
0
DAT: Data
SCL
Master drives SDA
SDA
Slave drives SDA
SWCS045-022
2
Figure 24. I C Write Access Single Byte
Figure 25 shows a read access single-byte timing diagram.
S
T
A
R
T
D D D D D D D W A
A A A A A A A R C
D D D D D D D I K
6 5 4 3 2 1 0 T
E
R R R R R R R R A S
A A A A A A A A C T
D D D D D D D D K A
7 6 5 4 3 2 1 0
R
T
D
A
D
7
D D D D D D D R A
A A A A A A A E C
D D D D D D D A K
6 5 4 3 2 1 0 D
D D D D D D D D A S
A A A A A A A A C T
T T T T T T T T K O
7 6 5 4 3 2 1 0
P
SCL
SDA
SWCS045-023
2
Figure 25. I C Read Access Single Byte
Multiple-Byte Access to Several Adjacent Registers
A write access is initiated by:
• A first byte, including the address of the device (7 MSBs) and a write command (LSB)
• A second byte, providing the base address (8 bits) of the internal registers
The following N bytes represent the data to be written in the internal register, starting at the base address and
incremented by one at each data byte.
Figure 26 shows a multiple-byte write access.
S
T
A
R
T
D D D D D D D W A
A A A A A A A R C
D D D D D D D I K
6 5 4 3 2 1 0 T
E
R R R R R R R R A D
A A A A A A A A C A
D D D D D D D D K T
7
7 6 5 4 3 2 1 0
D D D D D D D A
A A A A A A A C
T D T T T T T K
6 5 4 3 2 1 0
D D D D D D D D A S
A A A A A A A A C T
T T T T T T T T K O
7 6 5 4 3 2 1 0
P
SCL
SDA
SWCS045-024
2
Figure 26. I CWrite Access Multiple Bytes
A
•
•
•
84
read access is initiated by:
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
A second byte, providing the base address (8 bits) of the internal register
A third byte, including again the address of the device (7 MSBs) and the read command (LSB)
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
The device replies by sending a fourth byte representing the content of the internal registers, starting at the base
address and next consecutive ones.
Figure 27 shows a multiple-byte read access.
S
T
A
R
T
D D D D D D D W A
A A A A A A A R C
D D D D D D D I K
6 5 4 3 2 1 0 T
E
R R R R R R R R A
A A A A A A A A C
D D D D D D D D K
7 6 5 4 3 2 1 0
S D D D D D D D D
T A A A A A A A A
A D D D D D D D D
R 7 6 5 4 3 2 1 0
T
R A D D D D D D D D
E C A A A A A A A A
A K T T T T T T T T
D
7 6 5 4 3 2 1 0
A
C
K
D D D D D D D D A S
A A A A A A A A C T
T T T T T T T T K O
7 6 5 4 3 2 1 0
P
SCL
SDA
SWCS045-025
2
Figure 27. I C Read Access Multiple Bytes
Secure Registers
Some registers of the TWL6030 device can be protected by restricting their access in write mode to software
running in the secure mode of the host read access to protected registers. Secure access is enabled or disabled
by the MSECURE control signal.
The following components or actions can be protected:
• All RTC registers
• 64 bits of general-purpose memory (8 x 8) in the backup domain named VALIDITY
The read accesses are independent to the MSECURE value.
When MSECURE is logical level 1, all read and write accesses are authorized; when MSECURE is logical level
0, only read accesses are authorized.
This security feature (MSECURE detection) is enabled and disabled by an EPROM bit.
Interrupts
The INT signal (active low) warns the host processor of any event occurring on the TWL6030 device. The host
processor then pools the interrupt from the interrupt status register through I2C to identify the interrupt source.
Each interrupt source can be individually masked through the interrupt mask line registers and mask status
registers.
If interrupts occur while the status registers are not cleared, the status registers are not updated immediately.
Instead, the interrupts are held pending in a second stage of shadow registers, waiting for all previous interrupts
to be cleared first. When the interrupt line goes low again, operated just after the first set of interrupts clear, all
status registers are updated with those pending interrupt sources, coming directly from the shadow registers.
To clear both interrupts and register status, a write in the status registers must be done. Each write has the same
effect (interrupt line goes high and all status registers are cleared). This implies that the interrupt subroutine
acquires the three status registers before acknowledging the interrupt to avoid losing any interrupt sources.
NOTE
•
•
•
An interrupt associated with a function should be masked before enabling or disabling the
feature; otherwise, it might generate a false interrupt directly linked to the state change of the
feature and not related to an external detection event (for example, BAT_VLOW interrupt with
VBATMIN_HI comparator).
INT is always active low.
When a TWL6030 interrupt occurs:
– Software should first read all status registers, INT_STS_A, INT_STS_B, and INT_STS_C.
– Execute the subroutines related to the read interrupts.
– Clear the interrupt status of all status registers
Copyright © 2010–2011, Texas Instruments Incorporated
85
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Table 18. Interrupt mapping
#
REG BIT
SECTION
INTERRUPT
DESCRIPTION
PWRON detection: Power-on button pressed and released. Detection
performed on falling and rising edges. Interrupt sent in SLEEP or
ACTIVE only, not in WAIT-ON.
00
A
0
PM
PWRON
01
A
1
PM
RPWRON
02
A
2
PM
BAT_VLOW
03
A
3
RTC
RTC_ALARM
RTC alarm event: Occurs at programmed determinate date and time
04
A
4
RTC
RTC_PERIOD
RTC periodic event: Occurs at programmed regular period of time
(every second or minute)
05
A
5
Thermal monitoring
and shutdown
HOT_DIE
06
A
6
SMPS/LDO
VXXX_SHORT
At least one of the following power resources has its output shorted:
V1V29, V1V8, V2V1, VCORE1, VCORE2, VCORE3, VMEM, VANA,
VAUX1, VAUX2, VAUX3, VCXIO, VDAC, VPP, VUSB
07
A
7
LDO
VMMC_SHORT
VMMC power resource has its output shorted.
08
B
0
LDO
VUSIM_SHORT
VUSIM power resource has its output shorted.
09
B
1
Detection
BAT
Battery detection plug/unplug
10
B
2
Detection
SIM
SIM card plug/unplug
11
B
3
Detection
MMC
12
B
4
13
B
5
GPADC
GPADC_RT_SW1_EOC
14
B
6
GPADC
GPADC_SW2_EOC
15
B
7
Gas gauge
CC_AUTOCAL
16
C
0
OTG
ID_WKUP
17
C
1
OTG
VBUS_WKUP
18
C
2
OTG
ID
19
C
3
OTG
VBUS
RPWRON detection: Remote power-on signal change. Interrupt sent in
SLEEP or ACTIVE only, not in WAIT-ON.
Battery voltage low: Battery voltage decreasing and crossing
VBATMIN_HI
At least one of the two embedded thermal monitoring modules detects
a die temperature above the HD detection threshold.
MMC card plug/unplug
Reserved
End of conversion: Completion of a real time and a GP software 1
(SW1) conversion cycle; result available
End of conversion: Completion of a GP software 2 (SW2) conversion
cycle; result available
Calibration procedure finished and the result is available in the register.
ID wake-up event (from WAIT-ON/SLEEP states)
VBUS wake-up event (from WAIT-ON/SLEEP states)
ID event detection in SLEEP/ACTIVE states
VBUS event detection in SLEEP/ACTIVE states
20
C
4
Charger
CHRG_CTRL
Charger controller
Interrupt source can be:
•
Charger plug insertion and removal detection:
– VAC_PLUG
– VBUS_PLUG
•
Watchdogs 32mn / 32s interrupts:
– FAULT_WDG
•
Battery interrupts:
– BAT_REMOVED
– BAT_TEMP_OVRANGE
21
C
5
Charger
EXT_CHRG
External charger fault(CHRG_EXTCHRG_STATZ)
INT_CHRG
Internal USB charger fault
Interrupt source can be:
•
CHARGERUSB_FAULT
•
CHARGERUSB_THMREG
•
CHARGERUSB_STAT
•
CURRENT_TERM
22
C
6
23
C
7
86
Charger
Reserved
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
RECOMMENDED EXTERNAL COMPONENTS
MODULE
COMPONENT (1)
# (2) MANUFACTURER
PACK (3)
SIZE
(mm)
PM/VBAT
VDD tank
capacitor (4)
1
Murata
GRM188R60J106ME84L
10 µF
603
1.6 x 0.8 x 0.8
PM/VBAT
VDD tank
capacitor (4)
2
Taiyoyuden
JMK107BJ106
10 µF
603
1.6 x 0.8 x 0.8
Backup
Capacitor
1
Seiko Instruments
XH414H-IV01E
0.08 F
Backup
Capacitor
2
Matsushita (MEC)
EECEP0E223AN
0.022 F
PART NUMBER
VALUE
INPUT POWER SUPPLIES EXTERNAL COMPONENTS
ø4.8, 1.4
CRYSTAL OSCILLATOR EXTERNAL COMPONENTS
32 kHz
Crystal
1
Citizen
CM519
32.768 kHz
3.2 x 1.5 x 0.9
32 kHz
Crystal
2
Microcrystal
CC7V-T1A
32.768 kHz
32 kHz
Crystal
3
Epson
FC135
32.768 kHz
32 kHz
Crystal
4
NDK
NX3215SA
32.768 kHz
32 kHz
Supply decoupling
1
Murata
GRM155R61A105KE15D
1 µF
402
1 x 0.5 x 0.5
32 kHz
Supply decoupling
2
Taiyoyuden
JMK105BJ105MV-F
1 µF
402
1 x 0.5 x 0.5
32 kHz
Crystal decoupling
1
Murata
GRM1555C1H220JZ01
22 pF
402
1 x 0.5 x 0.5
32 kHz
Crystal decoupling
2
AVX
04025A120JAT2A
12 pF
402
1 x 0.5 x 0.5
Bandgap
Bias resistor
1
Rohm
1 MΩ
402
1 x 0.5 x 0.5
Bandgap
Bias resistor
2
Vishay
1 MΩ
603
1.6 x 0.8 x 0.8
Bandgap
Capacitor
1
Murata
GRM155R61C104K
100 nF
402
1 x 0.5 x 0.5
Bandgap
Capacitor
2
KEMET
C0402C104K8PAC
100 nF
402
1 x 0.5 x 0.5
10 mΩ
815
47 kΩ
402
1 x 0.5 x 0.5
3.2 x 1.5 x 0.8
BANDGAP EXTERNAL COMPONENTS
0W06 1M 50ppm
GAS GAUGE EXTERNAL COMPONENTS
Gas Gauge
Resistor
1
Cyntec
GPADC
NTC resistor
1
Murata
RL3720T-R010-FN
GPADC EXTERNAL COMPONENTS
NCL15WB473F03RC
I2C EXTERNAL COMPONENTS
I2C interface Pullup resistor
1
SMPS
Input capacitor
1
Murata
GRM155R60J225ME15D
2.2 µF
402
1 x 0.5 x 0.5
SMPS
Input capacitor
2
Taiyoyuden
JMK105BJ225MV-F
2.2 µF
402
1 x 0.5 x 0.5
SMPS
Input capacitor
3
Murata
GRM155R60J475M
4.7 µF
402
1 x 0.5 x 0.5
SMPS
Input capacitor
4
Taiyoyuden
JMK107BJ475KA-T
4.7 µF
603
1.6 x 0.8 x 0.8
SMPS
Input capacitor
5
Murata
GRM155R60J335UE97
4.7 µF
402
1 x 0.5 x 0.5
SMPS
Output capacitor
1
Murata
GRM188R60J106ME84L
10 µF
603
1.6 x 0.8 x 0.8
SMPS
Output capacitor
2
Murata
GRM188R60J106UE82J
10 µF
603
1.6 x 0.8 x 0.8
SMPS
Ferrite bead
1
Murata
BLM18SG700TN1D
–
603
1.6 x 0.8 x 0.8
SMPS
Ferrite bead
2
Murata
BLM15PD121SN1
1300 mA
402
1 x 0.5 x 0.5
SMPS
Ferrite bead
3
Murata
BLM18KG221SN1
2200 mA
603
1.6 x 0.8 x 0.8
SMPS 0.8 A Filter inductor
(volume
minimization)
1
Murata
LQM21PN1R0MC0
1 µH
805
2 x 1.25 x 0.55
SMPS 0.8 A Filter inductor
(performance
maximization)
2
TDK
MLP2520S1R0M
1 µH
1008
2.5 x 2 x 1
SMPS EXTERNAL COMPONENTS
(1)
(2)
(3)
(4)
Component minimum and maximum tolerance values are provided in the electrical parameters section for each IP.
The # column refers to the first (1), second (2), and third (3) source suppliers, for which the IPs are either simulated or characterized.
The PACK column describes the external component package type.
The VDD tank capacitors filter the VBAT/VDD_B [i] input voltage of the LDO and SMPS core architectures.
Copyright © 2010–2011, Texas Instruments Incorporated
87
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
SMPS 1.0
A, 1.2 A
Filter inductor
(volume
minimization)
1
Murata
LQM2MPN1R0NG0
1 µH
806
2 x 1.6 x 1
SMPS 1.2
A, 1.5 A, 2
A
Filter inductor
(performance
maximization)
1
Murata
LQM32PN1R0MG0
1 µH
1210
3.2 x 2.5 x 1
SMPS 1.2
A, 1.5 A, 2
A
Filter inductor
(performance
maximization)
2
TOKO
DFE322512C H1R0N (under
development)
1 µH
1210
3.2 x 2.5 x 1.2
SMPS 1.2
A, 1.5 A, 2
A
Filter inductor
(volume
minimization)
3
TOKO
DFE252012C H1R0N (under
development)
1 µH
1008
2.5 x 2 x 1.2
SMPS 2 A
Filter inductor
(volume
minimization)
1
Coilcraft
EPL2010-681MLB
0.68 µH
LDO
Input capacitor
1
Murata
GRM155R60J105KE19D
1 µF
402
1 x 0.5 x 0.5
LDO
Input capacitor
2
Taiyoyuden
JMK105BJ105MV-F
1 µF
402
1 x 0.5 x 0.5
LDO
Input capacitor
3
KEMET
C0402C105K9PAC7867
1 µF
402
1 x 0.5 x 0.5
LDO
Output capacitor
1
Murata
GRM155R60J105KE19D
1 µF
402
1 x 0.5 x 0.5
LDO
Output capacitor
2
Taiyoyuden
JMK105BJ105MV-F
1 µF
402
1 x 0.5 x 0.5
LDO
Output capacitor
3
KEMET
C0402C105K9PAC7867
1 µF
402
1 x 0.5 x 0.5
LDO
Output capacitor
4
Murata
GRM155R60J155ME80D
2.2 µF
402
1 x 0.5 x 0.5
2x2x1
LDO EXTERNAL COMPONENTS
CHARGER EXTERNAL COMPONENTS
Charger
Filter inductor
1
FDK
MIPS2520D1R0
1 µH
2520
Charger
Filter inductor
2
Taiyoyuden
CKP25201R0M-T
1 µH
2520
Charger
Filter inductor
3
Taiyoyuden
CKP2520D1R0
1 µH
2520
Charger
Sense resistor
1
Panasonic
ERJ2BWFR068X
68 mΩ
402
1 x 0.5 x 0.5
Charger
Sense resistor
2
Rohm
UCR01
68 mΩ
402
1 x 0.5 x 0.37
Charger
Sense resistor
3
Tyco Electronics
219-908
68 mΩ
2512
Charger
CHRG_VREF
capacitor
1
KEMET
C0603C225K4PAC
2.2 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_VREF
capacitor
2
Murata
GRM188R61C225UAAG
2.2 µF
603
1.6 x 0.8 x 0.8
Charger
VAC decoupling
1
Murata
GRM155R61C104K
100 nF
402
1 x 0.5 x 0.5
Charger
VAC decoupling
2
Taiyoyuden
LMK105BJ104MV-F
100 nF
402
1 x 0.5 x 0.5
Charger
VBUS decoupling
1
Murata
GRM155R60J475M
4.7 µF
402
1 x 0.5 x 0.5
Charger
VBUS decoupling
2
Taiyoyuden
JMK107BJ475KA-T
4.7 µF
603
1.6 x 0.8 x 0.8
Charger
VBUS decoupling
3
Panasonic
ECJINB1C475M
4.7 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_PMID
capacitor
1
Murata
GRM155R60J475M
4.7 µF
402
1 x 0.5 x 0.5
Charger
CHRG_PMID
capacitor
2
Taiyoyuden
JMK107BJ475KA-T
4.7 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_PMID
capacitor
3
Panasonic
ECJINB1C475M
4.7 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_CSIN
capacitor
1
Murata
GRM155R61C104K
100 nF
402
1 x 0.5 x 0.5
Charger
CHRG_CSIN
capacitor
2
Taiyoyuden
LMK105BJ104MV-F
100 nF
402
1 x 0.5 x 0.5
Charger
CHRG_CSOUT
1
Murata
GRM188R60J106ME84L
10 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_CSOUT
2
Taiyoyuden
JMK107BJ106
10 µF
603
1.6 x 0.8 x 0.8
Charger
CHRG_SW
capacitor
1
Murata
GRM155R61C103KA01D
10 nF
402
1 x 0.5 x 0.5
Charger
CHRG_SW
capacitor
2
Taiyoyuden
TMK105BJ103MV
10 nF
402
1 x 0.5 x 0.5
Charger
CHRG_AUXPWR
1
Murata
GRM155R61A105KE15D
1 µF
402
1 x 0.5 x 0.5
88
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Charger
CHRG_AUXPWR
2
Taiyoyuden
JMK105BJ105MV-F
1 µF
402
1 x 0.5 x 0.5
Charger
CHRG_AUXPWR
3
KEMET
C0402C105K9PAC7867
1 µF
402
1 x 0.5 x 0.5
Charger
LED
1
Osram
LYL296
–
Charger
LED
2
Everlight
16S-216UTD/S559/TR8
2 mA
402
1 x 0.5 x 0.35
Charger
CHRG_BOOT
1
Murata
GRM188R71H103KA01D
10 nF
603
1.6 x 0.8 x 0.8
Copyright © 2010–2011, Texas Instruments Incorporated
89
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
PACKAGE MATERIALS INFORMATION
PACKAGE CHARACTERISTICS
The package description of the TWL6030 PMU device is presented as follows:
PACKAGE (1)
TWL6030
Type
nFBGA
Size (mm)
7x7
Substrate layers
2-layer
Pitch ball array (mm)
0.4 mm
ViP (via-in-pad)
No
Array grid
16 x 16, depopulated
Number of balls
187
Thickness (mm; maximum height, including balls)
1.0 mm
Maximum power dissipation (85°C ambient temperature)
1.7 W
Others
(1)
Green, ROHS compliant
Moisture Sensitivity Level Target: JEDEC MSL3 @ 260°C
B
7,10
6,90
6,00 TYP
A
0,40
T
R
P
N
M
L
K
J
H
G
E
F
D
C
B
A
7,10
6,90
A1 corner
0,40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Bottom View
1,00 MAX
Seating plane
0,31
0,21
0,15 M C A B
0,05 M C
0,24
0,14
0,08
C
SWCS045-002
The thermal resistance characteristics for the package used on the TWL6030 device is given in the following
table.
PACKAGE
nFBGA, 7mm x 7mm
90
POWER (W)
RΘJA (°C/W)
RΘJB (°C/W)
RΘJC (°C/W)
BOARD TYPE
1.7
31
19
12
1S2P
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
TAPE AND REEL INFORMATION
A1 corner
Carrier tape
Sprocket hole
Embossment
Cover tape
User direction of feed
SWCS045-032
Figure 28. Tape and Reel
0.30±0.05
2.0±0.1
4.0±0.1
Do
Ø1.55±0.05
W
F
D1
Ø1.6±0.1
Bo
CL
R 0.3
Typical
Ko
P1
Bo
Ao
Ko
SWCS045-031
Figure 29. Tape
Table 19. Tape Dimensions
A0
B0
K0 ±0.1
F
P1
W ±0.3
7.30
7.30
1.50
7.50
12.00
16.00
Copyright © 2010–2011, Texas Instruments Incorporated
91
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
W2 (MEASURED AT HUB)
W1 (MEASURED AT HUB)
W3 (INCLUDES
FLANGE DISTORTION
AT OUTER EDGE)
C
1.8
N
(HUB DIAMETER)
A
“B”
“D”
“C” (REF)
ARBOR HOLE DETAIL
SWCS045-033
Figure 30. Reel Dimensions
Table 20. Reel Dimensions
Material
type
ESD
type
Tape
size
Hub size
Material
color
A(max)
B(±0.5)
C(±0.20)
D(min)
N
PS
ASD
16.0
4”
Black
330
2.0
13.0
20.8
100 ±1.0
92
W1(+2.0/
W3(min/
W2(max)
-0.0)
max)
18.4
22.4
15.9/19.4
Copyright © 2010–2011, Texas Instruments Incorporated
TWL6030
SWCS045B – SEPTEMBER 2010 – REVISED JUNE 2011
www.ti.com
Revision History
The following table summarizes the TWL6030 Data Sheet versions.
Note: Numbering may vary from previous verisons.
Table 21. Revision History
Version
Literature Number
Date
*
SWCS045
December 2009
See
(1)
A
SWCS045A
April 2011
See
(2)
See
(3)
B
(1)
(2)
(3)
SWCS045B
June 2011
Notes
.
.
.
TWL6030 Data Sheet, (SWCS045) - initial release.
TWL6030 Data Sheet, (SWCS045A):
(a) Added Figure 1, TWL6030 Block Diagram, Table 2, Ball Description, FEATURES, and APPLICATIONS.
(b) Updated ELECTRICAL CHARACTERISTICS, PACKAGE MATERIALS INFORMATION, and Figure 2, TWL6030 Package Top View
Ball Mapping.
(c) Updated RECOMMENDED EXTERNAL COMPONENTS.
(d) Updated part numbers, Table 1, Ordering Information.
(e) Rewrite of all functional blocks.
(f) Updated figures.
TWL6030 Data Sheet, (SWCS045B):
(a) Updated part numbers, Table 1, Ordering Information.
(b) Updated Figure 1, TWL6030 Block Diagram
(c) Updated balls N15, K13, B7 name from SPARE to RESERVED.
(d) Updated LDO REGULATORS description.
(e) Updated Subsystem Hardware Commands description.
(f) Updated Warmreset description.
(g) Updated Table 12, BOOT[3:0].
(h) Updated Figure 11. Q1,Q2, and Q3 transistors name added.
(i) Updated list of GPADC internal monitored parameters in GENERAL-PURPOSE ADC.
(j) Updated Interrupts functionality description.
(k) Updated Table 18, Interrupt mapping.
(l) Updated ID Line, added Figure 16 and Table 17.
Copyright © 2010–2011, Texas Instruments Incorporated
93
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TWL6030B107CMR
ACTIVE
FCBGA
CMR
187
260
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
TWL6030B107CMRR
PREVIEW
FCBGA
CMR
187
2500
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TWL6030B107CMRR
Package Package Pins
Type Drawing
FCBGA
CMR
187
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.5
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TWL6030B107CMRR
FCBGA
CMR
187
2500
333.2
345.9
31.8
Pack Materials-Page 2
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