ETC SDA9489X

PRELIMINARY DATA SHEET
SDA 9489X PIP IV Advanced
SDA 9589X SOPHISTICUS
High-End
Picture-In-Picture ICs
Edition Feb. 28, 2001
6251-562-1PD
SDA 9489X
Preliminary Data Sheet
SDA 9589X
High-end Picture-In-Picture (PIP) ICs
Version 1.3
CMOS
General Description
SDA 9489X ’PIP IV Advanced’ and SDA 9589X
’SOPHISTICUS’ belong to a new generation of Picturein-Picture (PiP) processors that combine high-quality
digital PIP signal processing, digital multistandard
color decoding and AD/DA conversion on a single chip.
Both devices are equipped with CVBS and Y/C input
interfaces. In addition the SDA SDA 9589X is also able
to process YUV input signals for displaying high quality
video signals e.g. coming from a DVD source.
Figure 0-1
P-DSO28-1
Picture-In-Picture
The integrated digital color decoder is able to decode all analog TV standards (PAL,
NTSC and SECAM) and detects the standard automatically. Therefore the IC is suited
for world-wide use.
A picture reduction from 1/4 to 1/81 of original size selectable in fine steps is possible.
The transfer functions of the decimation filters are optimally matched to the selected
picture size reduction and can furthermore be adjusted to the viewer’s requirements by
a selectable peaking. A maximum of 324 luminance and 2x81 chrominance pixels per
line are stored in the memory. The PiP supports split-screen applications as well as
multi-PiP display.
Type
Package
SDA 9489X
P-DSO28-1
SDA 9589X
P-DSO28-1
Micronas
-2
SDA 9489X
Preliminary Data Sheet
SDA 9589X
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.9
4.9.1
4.9.2
4.9.3
4.10
4.10.1
4.10.2
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Analog Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
AD-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Signal Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chroma Decoding And Standard Identification . . . . . . . . . . . . . . . . . . . . . .13
Comb Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Single PIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Continuos Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Horizontal And Vertical Fine Positioning . . . . . . . . . . . . . . . . . . . . . . . . .19
Multi Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Multi-PiP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
100 Hz Frame Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Mixed Standard Applications And (S)VGA Support . . . . . . . . . . . . . . . . .26
Display standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Picture Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Wipe In / Wipe Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Luminance Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Frame Generation And Colored Background . . . . . . . . . . . . . . . . . . . . .32
16:9 Inset Picture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Parent Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Automatic Brightness Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
On Screen Display (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Character Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Character and Character Background Color . . . . . . . . . . . . . . . . . . . . . .36
DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .38
Micronas
-3
SDA 9489X
Preliminary Data Sheet
SDA 9589X
4.11
4.11.1
4.11.2
4.11.3
4.11.4
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Closed Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Widescreen Signalling (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Indication Of New Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Violence Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
6.1
6.2
6.3
6.4
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9
Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Micronas
-4
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Features
1
Features
• Single chip solution:
– AD-conversion for CVBS or Y/C or YUV1), multistandard color decoding, PLL for
synchronization of inset channel, decimation filtering, embedded memory, RGBmatrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation
integrated on chip
• Analog inputs:
– 3x CVBS or 1x CVBS and 1x Y/C or 1xYUV 1)alternatively
– Clamping of each input
– All ADCs with 8 bit amplitude resolution
– Automatic Gain Control (AGC) for Y and CVBS
• Inset Synchronization:
– Multiple time constants for reliable synchronization
– Automatic recognition of 625 lines / 525 lines standard
• Color Decoder:
– PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 and SECAM
– Adjustable color saturation
– Hue control for NTSC
– Automatic Chroma Control (-24 dB ... +6 dB)
– Automatic recognition of chroma standards: different search strategies selectable
– Single crystal for all standards
– IF-characteristic compensation filter
• Decimation:
– PIP sizes between 1/81 and 1/4 adjustable with steps of 2 lines and 4 pixel
– Resolution up to 324 luminance and 2x81 chrominance pixels per inset line
– Horizontal and vertical filtering dependent on picture size
– Automatic zoom in/out possible with three speeds
• Display Features:
– 7 bit per pixel stored in memory
– Field and joint-line free frame mode display (even at 100/120 Hz AABB with picture
sizes<=1/9)
– Two ’split-screen’ modes with horizontal decimation of 2 and vertical of 1.5 or 1.0
– POP display
– Up to 12 pictures of 1/36th size (11 still and 1 moving)
– Up to 6 pictures of 1/16th size (5 still and 1 moving)
– Up to 3 pictures of 1/9th size (2 still and 1 moving)
– Display on VGA and SVGA screen (fH limited to 40kHz)
– 8 different read frequencies for 16:9 compatibility
– Line doubling mode for progressive scan applications
1)
SDA 9589X only
Micronas
1-5
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Features
•
•
•
•
•
•
•
•
•
– Freeze picture
– Coarse positioning at 4 corners of the parent picture
– Fine positioning at steps of 4 pixels and 2 lines
– Wipe in / out programmable with 3 time periods
Output signal processing:
– 7 Bit DAC
– RGB or YUV switch: insertion of an external source without PIP processing
– Digital interpolation for anti-imaging
– Adjustable transient improvement for luma (peaking)
– Contrast, Brightness and Pedestal Level adjustable
– Analog outputs: Y, +(B-Y), +(R-Y), or Y, -(B-Y), -(R-Y) or RGB
– Three RGB matrices available: NTSC(Japan), NTSC(USA) or EBU
– 64 different background colors and 4096 different frame colors
– Plain or 3D frame with variable width and height
Data Slicing:
– Slicing of closed-caption (CC) or wide-screen-signaling (WSS) data
– Violence blocking capability (V-chip)
– Several filter for XDS data extraction
On-screen display:
– 64 characters programmable
– 5 characters displayed in every PIP picture or 3 rows of 20 characters each
– 4 different character luminance values or frame color
– 4 background luminance values or (semi-) transparent mode
I2C-Bus control (400 kHz)
High stability clock generation
PDSO 28-1 package (SMD)
Full SDA 9488X and SDA 9588X backward compatibility
SDA 9388X / SDA 9389X pinout compatibility
3.3V supply voltage (5V input capable)
Micronas
1-6
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Pin Configuration
Pin Configuration
XIN
1
28
XQ
2
27
HSP
3
VSP
4
SDA
5
SCL
6
VDD
7
VSS
8
I2C
9
INT
10
IN1
11
IN2
12
IN3
13
FSW
14
Figure 2-1
Pinning
Figure 2-2
Package Outlines
Micronas
26
PDSO 28 -1
2
25
24
23
22
21
CVBS1
VREFM
CVBS2
VREFL
CVBS3
VSSA1
VDDA1
VREFH
20
VSSA2
19
VDDA2
18
OUT1
17
OUT2
16
OUT3
15
SEL
2-7
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Pin Configuration
Numb
er
Name
Type
Description
1
XIN
I
crystal oscillator (input) or external clock input
2
XQ
O
crystal oscillator (output)
3
HSP
I/TTL
horizontal sync for parent channel
4
VSP
I/TTL
vertical sync for parent channel
5
SDA
I/O
I2C-bus data
6
SCL
I
I2C-bus clock
7
VDD
S
digital supply voltage
8
VSS
S
digital ground
9
I2C
I
I2C Address
10
INT
O/TTL
interrupt
11
IN1
I/ana
V/R input for external YUV/RGB source
12
IN2
I/ana
Y/G input for external YUV/RGB source
13
IN3
I/ana
U/B input for external YUV/RGB source
14
FSW
I
fast switch input for YUV/RGB switch
15
SEL
O
fast blanking output for PIP
16
OUT3
O/ana
analog output: chrominance signal +(B-Y) or -(B-Y) or B
17
OUT2
O/ana
analog output: luminance signal Y or G
18
OUT1
O/ana
analog output: chrominance signal +(R-Y) or -(R-Y) or R
19
VDDA2
S
analog supply voltage for DAC
20
VSSA2
S
analog ground for DAC
21
VREFH
I/ana
22
VDDA1
S
analog supply voltage for ADC
23
VSSA1
S
analog ground for ADC
24
CVBS3
I/ana
25
VREFL
I/O
26
CVBS2
I/ana
27
VREFM
I/O
28
CVBS1
I/ana
uppper reference voltage for ADC and DAC
CVBS3 or V (SDA 9589X) or C Input
lower reference voltage for ADC
CVBS2 or U (SDA 9589X) or Y (from Y/C) Input
mid-level reference voltage for ADC
CVBS1 or Y (from YUV, SDA 9589X) Input
I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage
Table 2-1
Micronas
Pin Description
2-8
Figure 3-1
Micronas
CVBS3
CVBS2
24
26
28
25
21
27
6
5
9
I2C
INTR
10
Data Slicer
Acquisition
Inset
Sync
Processing
PAL/ SECAM/ NTSC
Color
Decoder
Skewcomp.
H/V Scaler
Decimation
1) SDA 9589X, SDA 9489X: 2x8bit
SDA
DCVBS/DY
SCL
Y/C and
Sync
Sep.
DUV/DCHR
I2C
Controller
Input
Select
Clamp
Gain
Triple
ADC
3x8bit 1)
XQ
2
XTAL
20.25 MHz
XIN
1
Clock
Synthesizer
Memory
Controller
768kbit
eDRAM
8
7
Peaking
Oversampling
Insertion
VSS
VDD
HSP
3
VSP
4
Parent
Sync
Processing
Display
Controller
Frame
Generation
DEMUX
CVBS1
VREFL
VREFM
VREFH
23
OSD
RGB
Matrix
14
13
12
11
20
IN3
IN2
IN1
15
16
SEL
OUT3
Fast
FSW
RGB/YUV 18 OUT1
Switch 17
OUT2
Triple
DAC
3x7bit
19
VDDA2VSSA2
3
22
VDDA1 VSSA1
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Block Diagram
Block Diagram
MUX
Block Diagram
3-9
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4
System Description
4.1
Analog Frontend
4.1.1
Input Selection
An analog inset CVBS signal can be fed to the inputs CVBS1-3 of SDA 9589X/SDA
9489X. Each of these sources is selectable via I2C bus (CVBSEL). CVBS2 and CVBS3
can be used as separate Y/C inputs. At SDA 9589X YUV sources can be connected to
CVBS1, CVBS2 and CVBS3 provided YUV operation being enabled (YUVSEL). Using
an external switch SDA 9589X can operate in applications with both YUV and CVBS
signals.
CVBSEL
YUVSEL
Input
CVBS1
CVBS2
D1
D0
0
0
0
0
1
0
CVBS
1
0
0
Y (VBS)
1
1
0
X
X
1
Table 4-1
4.1.2
remark
CVBS3
CVBS
C
Y/C mode
CVBS
Y (VBS)
U (CB)
V (CR)
YUV mode
(only SDA 9589X)
Input selection
AD-Conversion
All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and
Y signals are clamped to the sync bottom whereas U/V and C signals are clamped to
their mid-level during blanking.
Inset
Video
HD
CLMPIST
CLAMPI
Figure 4-1
Micronas
CLMPID
Clamping timing
4-10
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust
to the specific application. The ADCs are driven by a 20.25 MHz free running crystal
clock which is not related to the incoming CVBS signal.
To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum should not
exceed 5 MHz. The digital filtering suppresses all frequencies above the usable
spectrum.
4.1.3
Automatic Gain Control
To accommodate to different CVBS input voltages an automatic gain control has been
implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5Vpp.
For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if
available. The AGC behavior can be chosen out of four possibilities (AGCMDE).
The sync height serves as reference for the gain control in the typical application. When
using overflow detection only, the gain is set to maximum and is reduced whenever an
overflow occurs. This procedure will be executed again when a channel change is
detected or the gain control is manually reset by AGCRES.
Automatic Gain Control Characteristic
2
Input Voltage [V]
1.5
1
0.5
0
0
2
4
6
8
10
12
14
16
AGCVAL
Figure 4-2
4.1.4
AGC characteristic
Signal Magnitudes
The nominal CVBS signal with 75% color has a magnitude of 1 Vpp. The upper headroom
is left to permit signals with 100% color resulting in 1.23 Vpp. The Y signal must always
contain the sync part. Its levels correspond to the CVBS levels except for the missing
color and burst. After A/D conversion the video part is clamped to its black value and is
amplified to 224 digital steps. The nominal signal levels ensure correct brightness and
saturation. The YUV signal levels conform to the ITU 601 recommendation.
Micronas
4-11
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
255
255
upper headroom
217
32
4
0
lower headroom
255
240
212
128
44
16
0
75% V
128
44
16
0
lower headroom
D3
D2
D1
D0
Conversion
Range
CRYC
0
0
0
0
0.5Vpp
0.42Vpp
...
...
...
0
1.2Vpp
1.0Vpp
...
...
...
1
1.5Vpp
1.25Vpp
Table 4-2
Micronas
CRYC = 1.2 Vpp
SRC = 0.89 Vpp
lower headroom
UV input signal range
AGCVAL
1
upper headroom
CRUV = 0.8 Vpp
75% U
CRUV = 0.8 Vpp
SRUV = 0.7 Vpp
upper headroom
0
100% chroma
CVBS/Y and chroma ADC input signal range
255
240
212
Figure 4-4
lower headroom
0
SRUV = 0.7 Vpp
Figure 4-3
1
burst
128
75% chroma
black
CRYC = 1.2 Vpp
SRY = 1 Vpp
burst
white
68
1
upper headroom
224
0
1
Signal
Range
SRY
Signal
Range
SRC
Conversion
Range
CRUV
Signal
Range
SRUV
0.89Vpp
0.8Vpp
0.7Vpp
ADC conversion range and required input signal voltage
4-12
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
4.2
Inset Synchronization
Horizontal and vertical sync pulses are separated after elimination of the high frequency
components of the CVBS signal by a low pass filter. Horizontal sync pulses are
generated by a digital phase-locked-loop (DPLL). Its time constant is adjustable between
fast and slow behavior in four steps (PLLITC) to consider different input sources (e.g.
VCR). Noisy input signals become more stable when a noise-reduction is enabled
(NSRED). Additionally weak input signals from a satellite dish (’fishes’) become more
stable when SATNR is enabled. Both should be enabled to have best available
performance. When NOSIGB is enabled, a colored background is shown instead of the
picture when PIP is out of synchronization. The detected line standard is indicated by
SYNCSTAT.
4.3
Chroma Decoding And Standard Identification
The system is able to decode NTSC and PAL signals with a subcarrier of 3.58MHz and
4.43MHz (PAL B/M/N/60, NTSC M/4.4) as well as SECAM signals with 4.05/4.2MHz
subcarrier. The system may be forced to a certain standard, or an automatic standard
detection can be used (CSTAND). For automatic standard detection, some standards
which are not likely to be received can be ignored to improve the detection process.
Depending on the detected line standard (525 or 625 lines) the color standard detection
circuit searches for 60 Hz signals (NTSC-M / PAL-M / PAL 60 / NTSC44) or 50 Hz signals
(PAL-B / SECAM / PAL-N) respectively. Within each line standard, the standard is
detected by consequently switching from one to another. This standard detection
process can be set to medium or fast behavior (LOCKSP). In medium behavior 30 fields
(in fast 20) are used to detect the standard. If not being successful within this time period
the system tries to detect another one. For SECAM detection, a choice between two
recognition levels is possible (SCMIDL) and the evaluated burst position is selectable
(BGPOS).
.
CSTANDEX
D1
D0
0
0
0
.1
1
0
1
1
Table 4-3
NTSCM
PAL60
PAL-N
PAL-M
PAL-B
SECAM
NTSC
44
Considered color standards for automatic standard detection
For getting the chrominance information the digitized video signal is multiplied with the
regenerated color subcarrier once in-phase and once phase-shifted by 90°. After
lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated
Micronas
4-13
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
by a digital PLL. At SECAM operation the PLL runs free and generates the line-wise
alternating subcarriers. A CORDIC structure demodulates the frequency-modulated UV
signals. The following SECAM de-emphasis filter characteristic is adjustable (DEEMP).
The chroma signal can be filtered before demodulation by means of a selectable IFprefilter (IFCOMP).
0
5
2.5
5
DEEMP = ’00’
10
DEEMP = ’01’
DEEMP = ’10’
DEEMP = ’11’
15
gain [dB]
gain [dB]
0
3.58
4.4
IFCOMP = ’00’
IFCOMP = ’01’
2.5
IFCOMP = ’10’
5
7.5
20
0
0.5
1
1.5
frequency [MHz]
Figure 4-5
2
2.5
10
2
3
4
5
6
frequency [MHz]
SECAM de-emphasis filter characteristic and IF-compensation filter
characteristic
The Hue Control (HUE) influences the phase of the demodulation subcarrier between
-44.8° and 43.4° in steps of 1.4°. This is provided for NTSC only and adjustment is
ineffective for PAL and SECAM signals.
The reference for the subcarrier generation is a crystal stable clock of 20.25000 MHz. In
order to avoid color standard detection problems, the maximum deviation of this
frequency should not exceed 100ppm. For a good PLL locking behavior a maximum
deviation of 40ppm is recommended. A small frequency adjustment (-150 ... +310 ppm)
is possible for using a crystal with small frequency deviations (SCADJ). For test
purposes, CPLL allows to open the loop of the chroma PLL.
For deviations in the chroma signal up to 30dB, a stable output amplitude after chroma
decoding is achieved due to the ACC (Automatic Chroma Control). If the chroma signal
(color burst) is below a selectable threshold (CKILL), the color will be switched off.
Alternatively the color-killer can be bypassed and the color can be switched on or off
under all conditions (COLON). By setting ACCFIX, the automatic chroma control is
disabled and set to a default value.
Micronas
4-14
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
CKILL
COLON
color killed at damping of
D1
D0
0
0
0
30 dB
0
1
0
18 dB
1
1
0
24 dB
1
1
0
color always off
X
X
1
color always on
Table 4-4
Color-killer adjustment
The bandwidth of the chroma filter is adjustable via CHRBW. The bandwidth depends
on whether the decoder is in SECAM operation or not. A change in CHRBW does not
result in a chrominance position shift on the screen.
CKSTAT can be read out and gives information whether the color is switched on or off.
STDET indicates the detected color standard. Additionally PALID signals whether a PAL
signal or a NTSC signal is applied.
4.4
Comb Filtering
Depending on the selected picture size and color standard, a comb filtering is performed
for luminance and chrominance. A comb filter uses the spectral interleaving of the
encoded luminance and chrominance to separate both without cross artifacts. Thus
cross-color and cross-luminance are suppressed effectively. For NTSC sources, a comb
filtering is performed for all picture sizes. Due to reduced bandwidth in horizontal and
vertical direction a strong reduction of cross artifacts can be achieved for PAL signals.
The same applies for the luminance signal of SECAM signals.
4.5
Luminance Processing
The A/D-converted CVBS (or Y) signal is digitally clamped to back porch. Depending on
the transmitted standard and operational area, an offset between black- and blanking
level can be found in the incoming signal (’7.5 IRE’). As for some applications a black
offset is not desired, controlling may be done using LMOFST. The positive or negative
offset is added to the Y signal before scaling.
Micronas
4-15
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
Received signal
BLACK value
BLANK value
Processed signal
BLACK value
BLANK value
M standard signals
LMOFST='00' (no additional offset)
BLACK value
BLANK value
LMOFST='10' (reduction of 16 LSB)
BLACK value
BLANK value
B/G/H/I/N standard signals
LMOFST='00' (no additional offset)
Figure 4-6
LMOFST='01' (addition of 16 LSB)
Black level correction of luminance signal
The color carrier is removed out of a CVBS signal by means of a notch filter. It is set to
the corresponding color carrier (3.58 or 4.4 MHz) only if the standard is detected
permanently. This prevents the luminance sharpness of being changed within the
standard search process. For Y signals the notch is disabled.
For a fine adjustment of delaycompensation between luminance and chrominance,
YCDEL allows a luminance shifting in 16 steps of 50ns.
4.6
Decimation
4.6.1
Single PIP Mode
Luminance and chrominance signals are filtered in horizontal and vertical direction. The
coarse horizontal and vertical picture size (1/2, 1/3, 1/4, 1/6) is independently
programmable with SIZEHOR and SIZEVER. A fine adjustment in steps of 4 pixel and 2
lines is possible by HSHRINK and VSHRINK, which allows correct aspect ratio for
multistandard applications (50/60 Hz mixed mode, (S)VGA).
For main decimation factors, the stored number of pixel and lines are listed in the
following tables.
Micronas
4-16
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
SIZEHOR
horizontal
scaling
PIP Pixel per line
Y
(B-Y)
(R-Y)
D1
D0
0
0
2:1
324
81
81
0
1
3:1
216
54
54
1
0
4:1
160
40
40
1
1
6:1
108
27
27
Table 4-5
Number of stored pixel per line dependent on SIZEHOR
SIZEVER
vertical scaling
PIP lines
625 lines source
525 lines source
2:1
132
108
1
3:1
88
72
1
0
4:1
66
54
1
1
6:1
44
36
D1
D0
0
0
0
Table 4-6
4.6.2
Number of stored lines per field
Continuos Zoom
The continuos zoom feature changes the picture size rapidly in an animated manner. It
is available in single-PIP mode for picture sizes smaller or equal 1/4 of the undecimated
picture.
There are three possibilities of using the zoom feature:
2
• The PIP is zoomed via HSHRINK and VSHRINK manually. This requires an I C
protocol each time the picture size should change. CZMEN should be used to
synchronize the update of HSHRNK/VSHRNK with SIZEHOR/SIZEVER.
• A different way is to make usage of the automatic zooming. The zoom speed can be
controlled by CZMSPD. When switching PIP on or off by using PIPON, the PIP zooms
automatically to the selected picture size or disappears at size of 1/81.
• A zooming between two picture sizes can be performed by changing the HSHRINK,
VSHRINK, SIZEHOR, SIZEVER values when CZMEN is enabled. Then the new
picture size is obtained by zooming and not taken immediately.
Automatic zooming is only possible in frame mode. Being in field mode, the picture size
remains stable until frame mode occurs or until the internal counter reaches the desired
Micronas
4-17
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
picture size. Then the size changes immediately. Equal to the wipe process, the zooming
direction depends on the coarse position (CPOS).
625 lines
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
1
2
3
4
5
6
7
8
9
10
Table 4-7
Micronas
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
2
2,03
2,06
2,09
2,13
2,16
2,2
2,23
2,28
2,31
2,36
2,41
2,44
2,48
2,53
2,59
2,64
2,69
2,75
2,81
2,88
2,94
3
3,07
3,14
3,21
3,3
3,38
3,47
3,56
3,66
3,77
3,89
132
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
525 lines
2
2,03
2,08
2,13
2,16
2,2
2,25
2,3
2,34
2,41
2,45
2,52
2,58
2,64
2,7
2,77
2,84
2,92
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
3
3,09
3,19
3,28
3,38
3,49
3,61
3,73
3,87
72
70
68
66
64
62
60
58
56
625 lines
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4,13
4,25
4,41
4,56
4,72
4,88
5,06
5,28
5,5
5,75
6
6,28
6,61
6,94
7,31
7,78
8,25
8,81
9,42
10,17
11,02
525 lines
66 4,01
64 4,15
62 4,31
60
4,5
58 4,69
56
4,9
54 5,13
52 5,39
50
5,7
48
46
44
6
42 6,38
40 6,75
38 7,22
36 7,73
34
8,3
32
9
30
9,8
28 10,78
26
24
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
Number of stored lines per field dependent on VSHRNK
4-18
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 4-8
4.6.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2,00
2,02
2,05
2,08
2,10
2,13
2,16
2,19
2,22
2,25
2,28
2,31
2,35
2,38
2,41
2,45
2,49
2,53
2,57
2,61
2,66
2,70
2,74
2,80
2,84
2,89
2,95
324
320
316
312
308
304
300
296
292
288
284
280
276
272
268
264
260
256
252
248
244
240
236
232
228
224
220
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
3,00
3,04
3,11
3,17
3,23
3,29
3,37
3,44
3,51
3,60
3,67
3,76
3,84
3,94
4,05
4,16
4,27
4,38
4,50
4,63
4,77
4,91
5,06
5,22
5,41
5,59
5,78
216
212
208
204
200
196
192
188
184
180
176
172
168
164
160
156
152
148
144
140
136
132
128
124
120
116
112
0
1
2
3
4
5
6
7
8
9
10
11
12
3
3
3
3
3
3
3
3
3
3
3
3
3
6,00
6,23
6,48
6,75
7,04
7,35
7,70
8,10
8,52
8,99
9,51
10,12
10,64
108
104
100
96
92
88
84
80
76
72
68
64
60
Number of stored pixel per line dependent on HSHRNK
Horizontal And Vertical Fine Positioning
All picture sizes are pre-centered inside the frame. In addition, if necessary the vertical
and horizontal acquisition area can be shifted by VFP for vertical and HFP for horizontal
direction.
Micronas
4-19
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.6.4
Multi Display Mode
SDA 9589X and SDA 9489X offer the feature to display a sub-picture more than once.
The picture size and arrangement depends on the display mode (DISPMOD) and not on
SIZEHOR or SIZEVER. Hence variable scaling is not possible in these modes.
Display
Mode
DISPMOD
D1
D0
1
0
0
2
0
1
3
1
0
Table 4-9
Size
SIZEHOR/
SIZEVER
HSRHNK/
VSHRNK
Picture
configuration
Pixel
Lines
625
525
single PIP mode
324
60
132
24
108
20
3 X1/9
one upon another
(same content)
216
264
216
4 X 1/16
one upon another
(same content)
156
264
216
Multi-display modes
The display modes are shown in the appendix. The sizes of the partial pictures are listed
in table 4-11 .
4.6.5
Split Screen
For split screen applications two selectable ’double window’ modes in which one half of
the picture is generated by the ’Sophisticus’/’PIP IV Advanced’ can be used. The split
screen mode can be selected by two possible combinations of DISPMOD.
Figure 4-7
Micronas
Double window mode 1.5 (left picture) and mode 1 (right picture)
4-20
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
The D1.5 mode is suited for displaying split screen on 16:9 tubes keeping the aspect
ratio. The DW1 format covers the full height of the screen.
4.6.6
Multi-PiP Mode
There is a great variety of multi-pip modes available. Up to 11 different still pictures and
one moving picture can be shown. This is useful to give an overview over broadcasted
programmes (e.g. tuner-scan) or for supervising purposes. For multi-PiP modes only
three fixed picture sizes are available (1/9, 1/16 or 1/36). The picture size and
arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or
SIZEVER. Variable scaling is thus not possible in these modes. Because of limited
memory capacity, the number of frozen multi-pictures is limited dependent on picture
size to the number shown in the table below:
Table 4-10
picture sizes
maximum number of pictures
(including one live picture)
1/9
3
1/16
6
1/36
12
Maximum number of pictures in multi-PIP mode
The partial picture that is written is addressed via WRPOS. With INFRM, a frame for
separation of every PiP can be selected. This is adjustable to single or dual PIP mode
(INFRMOD). The current updated picture can be highlighted with PIPHLT. To avoid
garbage pictures after switching from one mode to another the selected picture can be
blanked with PIPBLK. MPIPBG defines wether the picture will be blanked with black or
with the adjusted background color.
For compatibility reasons to other devices, the DISPMOD register is split into two
segments. If a display mode is chosen that is not implemented, the PIP insertion is
switched off automatically (PIPON = ’0’). The sizes of the partial pictures correspond to
the sizes of the inset pictures of the single PIP modes.
Micronas
4-21
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
Display
DISPMOD
Mode D6 D5 D4 D3 D2
Size
Picture
configuration
Pixel
Lines
625 525
4
0
0
0
0
1
2 X 1/9,
one upon another
216
176 144
5
0
0
0
1
0
2 X 1/9,
side by side
432
88
72
6
0
0
0
1
1
3 X 1/9,
side by side
648
88
72
7
0
0
1
0
0
3 X 1/9
one upon another
216
264 216
8
0
0
1
0
1
4 X 1/16 side by side
624
66
9
0
0
1
1
0
6 X 1/16 inverted U shaped
624
132 108
10
0
0
1
1
1
6 X 1/16 U shaped
624
132 108
11
0
1
0
0
0
4 X 1/16 2 rows of 2 pictures
312
132 108
12
0
1
0
0
1
4 X 1/16 one upon another
156
264 216
13
0
1
0
1
0
12 X 1/36 6 rows of 2 pictures
216
264 216
14
0
1
0
1
1
12 X 1/36 2 rows of 6 pictures
648
88
15
0
1
1
0
0
9 X 1/36 3 rows of 3 pictures
324
132 108
16
0
1
1
0
1
12 X 1/36 3 rows of 4 pictures
432
132 108
17
0
1
1
1
0
11 X 1/36 angular of 11
pictures
648
264 216
18
0
1
1
1
1
9 X 1/36 angular of 9 pictures
540
220 180
19
1
0
0
0
0
1X1/3
Double Window
(V=1.5)
324
176 144
20
1
0
0
0
1
1X1/2
Double Window
(V=1)
324
264 216
21
1
0
0
1
0
all other
Table 4-11
4.7
54
72
OSD only
PIP off (PIPON=0)
Display Modes
Display Control
The on-chip memory capacity is 768 kbits. Provided that the same standard (50 or 60
Hz) video sources are applied to inset and parent channel, joint-line free frame mode
display is possible. This means that every incoming field is processed and displayed by
the SDA 9589X/SDA 9489X processors. The result is a high vertical and time resolution.
For this purpose the standard is analyzed internally and frame mode display is blocked
Micronas
4-22
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
automatically, if the described restrictions are not fulfilled. Then only every second
incoming field is shown (field mode). Field mode normally shows joint-lines. This is
caused by an update of the memory during read out. The result is that one part of the
picture contains new picture information and the other part contains one earlier written
field. The switching from or to frame mode is free of artifacts.
Activation of frame-mode display is blocked automatically if at least one of the following
conditions is not fulfilled:
• Inset and parent channel have the same field repetition frequency. This means that
frame mode is possible only for 50Hz inset and parent sources or 60Hz inset and
parent sources.
• Interlace signal is detected for inset and parent channel. For progressive scan or
(S)VGA display therefore only field mode is possible. For some VCRs in trick mode,
often no interlace is detected also.
• The number of lines is within a predefined range for inset (FMACTI) or parent
(FMACTP) channel (assuming standard signals according to ITU)
FMACTP
parent
standard
number of
lines per field
FMACTI
inset
standard
number of
lines per field
0
50 Hz
310...315
0
50 Hz
310...315
1
50 Hz
290...325
1
50 Hz
290...325
0
60 Hz
260...265
0
60 Hz
260...265
1
60 Hz
250...275
1
60 Hz
250...275
Table 4-12
Required number of lines for frame mode display
The system may be forced to field mode by means of FIESEL. Either first or second field
is selectable. ’One of both’ takes every second field independent of the field number.
This is meant for sources generating only one field (e.g. video-games).
For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling
mode is available (PROGEN). Every line of the inset picture is read twice.
Memory writing is stopped by FREEZE bit. The field stored in the memory is then
continuously read. As the picture decimation takes place before storing, the picture size
of a frozen picture can not be changed.
Synchronization of memory reading with the parent channel is achieved by processing
the parent horizontal and vertical synchronization signals connected to the pin HSP for
horizontal synchronization and pin VSP for vertical synchronization. HSPINV or VSPINV
respectively allow an inversion of the expected signal polarity.
Micronas
4-23
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
HSP
VSP
VSPDELmax=151 (75) ←s
VSPDEL
VSPD
field 0 window
field 1 window
(internal)
tH/2 = 32 (16) ←s
tH = 64 (32) ←s
values in brackets () apply for 100Hz systems
Figure 4-8
Field detection and phase adjustment of vertical pulse (VSP)
Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed. As the external VSP and HSP signals may
come from different devices with different delay paths, the phase between V-sync and
H-sync is adjustable (VSPDEL). An incorrect setting of VSPDEL may result in wrong or
unreliable field detection of parent channel.
Normally a noise reduction of the incoming parent vertical pulse is performed. With this
function missing vertical pulses are compensated. The circuit works for 50/60 Hz
applications as well as progressive and 100/120Hz application. (S)VGA signals are
supposed to be very stable and therefore not supported by the noise suppression. By
means of VSPNSRQ, vertical noise suppression is switched off.
A great variety of combinations of inset and parent frequencies are possible. The
following table shows some constellations.
Micronas
4-24
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
Inset
Parent
frame correct aspect correct aspect
vertical
Frequency1) Frequency1) mode
ratio
ratio
noise
(HSP/VSP)
(single pip)
(multi display) suppression
selectable
50
50i
50
60i
60
50i
60
60i
50
50p
50
60p
60
50p
60
60p
50
100i
50
120i
60
100i
60
120i
50
(S)VGA
3)
60
(S)VGA
3)
2)
2)
1)
standard signals supposed
2)
AABB only and picture size smaller than 1/9
3)
valid for some parent frequencies. Please refer to Chapter 4.7.2
Table 4-13
4.7.1
Available Features with varying inset and parent standards
100 Hz Frame Mode
If the picture size is smaller or equal than 1/9 PIP a true frame mode display for 100Hz
parent standard with a double field repetition rate is possible (display raster ∼∼ϒϒ only).
The picture size is indicated by the horizontal and vertical decimation factors that must
be equal or below 1/3 of undecimated picture size in both directions. This guarantees
enough memory for a joint-line free picture with full vertical resolution. For bigger pictures
only field mode is supported. The 100 Hz frame mode is activated if READD=’1’ for the
above mentioned picture sizes. For an acceptable quality without line flicker or motion
artifacts only the mode ∼∼ϒϒ is supported for HSP and VSP. If the sequence ∼ϒ∼ϒ is
detected, the field mode will be activated again. Continous switching between these
modes is possible, resulting in continous switching between field- and frame mode.
Micronas
4-25
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.7.2
Mixed Standard Applications And (S)VGA Support
remark
(Napel X Naline @ fV)
fH
(kHz)
TH
(←s)
THact
(←s)
lines/
active
fdot
(MHz)
scan
720X576@50Hz
(TV)
15.6
64.0
52.0
625/
576
13.5
interlace
702X488@60Hz
(TV)
15.7
63.6
52.7
525/
488
13.5
interlace
720X576@100Hz
(TV 100 Hz)
31.2
32.0
26.0
625/
576
27
interlace
702X488@120Hz
(TV 120 Hz)
31.2
31.8
26.4
525/
488
27
interlace
720X576@50Hz
(TV progressive)
31.2
32.0
26.0
625/
576
27
progressive
702X488@60Hz
(TV progressive)
31.2
31.8
26.4
525/
488
27
progressive
640X480@60Hz
(VGA)
31.5
31.8
25.4
525/
480
25.2
progressive
640X480@72Hz
(VGA)
37.9
26.4
20.3
520/
480
31.5
progressive
640X480@75Hz
(VGA)
37.5
26.7
20.3
500/
480
31.5
progressive
800X600@56Hz
(SVGA)
35.2
28.4
22.2
625/
600
36.0
progressive
800X600@60Hz
(SVGA)
37.9
26.4
20.0
625/
600
40.0
progressive
800X600@72Hz
(SVGA)
48.1
20.8
16.0
666/
600
50.0
progressive
800X600@75Hz
(SVGA)
46.9
21.3
16.2
625/
600
49.5
progressive
800X600@85Hz
(SVGA)
53.7
18.6
14.2
631/
600
56.3
progressive
1024X768@43Hz
(SVGA)
35.5
28.2
22.8
817/
768
44.9
interlace
Table 4-14
Micronas
correct
aspect
ratio
Examples of supported parent signals
4-26
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
SDA 9589X and SDA 9489X allow multiple scan rates for the use in desktop video
applications, VGA compatible or 100Hz TV sets. All features are provided in ’normal’
operating modes at auto detected 50Hz and 60 Hz parent and inset standards. 2fH
modes (100/120Hz and progressive) are supported by line frequency- and pixel clock
doubling and are not detected automatically. Even on a 16:9 picture tube correct aspect
ratio can be displayed by selecting the suitable parent clock. The video synthesizer
generates also a special pixel clock for VGA display (see chapter 5.5.9 for details). As
(S)VGA consists of a variety of scan rates the correct aspect ratio is not adjustable for
all modes with the parent clock (HZOOM) because of the limited count of frequencies.
For single PIP only, correct aspect ratio is maintained by the vertical and horizontal
scaler (HSHRINK and VSHRINK).
It is possible to display (S)VGA sources for parent display, as long as the horizontal
frequency is lower than 40 kHz and the signal does not contain more than 1023 lines.
For progressive scan mode, PROGEN must be set. Additionally field-mode should be
forced to prevent unallowed frame-mode displaying (FIESEL). As the (S)VGA normally
does not fit to the display raster generated in the vertical noise suppression, VSPNSRQ
should be disabled. (S)VGA signals for inset channel are not supported.
PROGEN
READD
Expected input signal
0
0
50 or 60 Hz signal interlace
0
1
100 or 120 Hz signals interlace
1
0
(reserved)
1
1
50 or 60 Hz or (S)VGA signal progressive
Table 4-15
4.7.3
Selection of display field repetition
Display standard
For a single-PiP, the number of displayed lines depends on the selected picture size and
on the signal standard. For multi picture display, the number of displayed lines depends
on the selected picture size and on the signal standard of the parent signal. Additionally,
a standard can be forced by DISPSTD.
Micronas
4-27
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
DISPSTD
DISPMOD
Display Standard
D1
D0
0
0
0
PIP depends on detected inset standard (single pip)
0
0
>0
PIP depends on detected parent standard (multi display)
0
1
x
PIP display is always in 625 lines mode
1
0
x
PIP display is always in 525 lines mode
1
1
x
freeze last detected display standard and size
Table 4-16
Display standard selection
If a 625 lines picture is shown with a 525 lines parent signal, some lines are missing on
top and bottom of picture. If a 525 lines picture is shown with a 625 lines display
standard, missing lines at top and bottom are filled with background color or black
depending on MPIPBG.
625 lines / 50 Hz
Figure 4-9
4.7.4
525 lines / 60 Hz
50 and 60 Hz Multi PiP display on 50 Hz and 60 Hz display
Picture Positioning
The display position of the inset picture is programmable to the 4 corners of the parent
picture (CPOS). From there PIP can be moved to the middle of the TV Picture with
POSHOR and POSVER. The corner positions can be centered coarsely on the screen
with POSOFH and POSOFV. Depending on coarse position, one PIP corner remains
stable when changing the picture size.
Micronas
4-28
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
CPOS
D1
D0
Coarse
Position
0
0
upper left
upper left
down
right
0
1
upper right
upper right
down
left
1
0
lower left
lower left
up
right
1
1
lower right
lower right
up
left
Table 4-17
Reference
corner of PiP
increasing
POSVER
increasing
POSHOR
Coarse Positioning
There are 256 horizontal locations (4 pixel increments) and 256 vertical locations (2 line
increments). The pixel width on the screen depends on the selected HZOOM factor.
Even POP-positions (Picture Outside Picture) in 16:9 applications are possible.
POSHOR
CPOS='01'
CPOS='00'
POSVER
POSVER
CPOS='11'
CPOS='10'
POSHOR
Figure 4-10 Coarse Positioning
4.7.5
Wipe In / Wipe Out
With the wipe in / wipe out function it is possible to let appear or disappear the complete
inset picture starting or ending at the corner of the inset picture position defined by
CPOS. Thereby the size of the visible picture-part is continuously increased and
decreased respectively. During this procedure the frame is shown with its chosen widths.
3 different wipe in / out time periods or ’no wipe’ are programmable via WIPESPD. The
wipe algorithm always works in horizontal and vertical direction.
Micronas
4-29
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
wipe out
CPOS='00'
CPOS='10'
CPOS='01'
CPOS='11'
CPOS='00'
CPOS='10'
CPOS='01'
CPOS='11'
CPOS='00'
CPOS='10'
CPOS='01'
CPOS='11'
wipe in
Figure 4-11 Wipe display
If WIPESPD is set accordingly, PIPON controls the wipe operation. When PIPON
changes the wipe operation starts. During this period, the readable PIPSTAT indicates
the ongoing wipe-process. A transition of PIPON from ’0’ to ’1’ triggers the wipe-in. The
wipe-in process stops when the picture reaches its programmed size. When PIPON
changes from ’1’ to ’0’ the wipe-out starts. The wipe-out is finished when the PiP picture
vanishes. Even for multi-picture display wipe operation is possible. A change of PIPON
or WIPESPD during wipe operation has only an effect after the wipe operation has been
finished.
4.8
Output Signal Processing
4.8.1
Luminance Peaking
To improve picture sharpness, a peaking filter which amplifies higher frequencies of the
input signal is implemented. The amount of peaking can be varied in seven steps by
YPEAK. The setting ’000’ switches off the peaking. The value ’001’ is recommended as
This value provides a good compromise between sharpness impression and annoying
aliasing. The characteristic for all possible settings is shown in fig. (4-12). The
emphasized frequency depends on the adjusted decimation. The gain maximum is
always located before the band-limit ensuring optimal picture impression.
Micronas
4-30
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
10
9
YPEAK = ’111’
8
YPEAK = ’110’
YPEAK = ’101’
gain [dB]
7
6
YPEAK = ’100’
5
YPEAK = ’011’
4
YPEAK = ’010’
3
YPEAK = ’001’
2
1
0
0
0.1
0.2
0.3
YPEAK = ’000’
0.5
0.4
normed frequency
Figure 4-12 Characteristics of selectable peaking factors
(0.5 = band limit)
Coring should be switched on by YCOR to reduce noise, which is also amplified when
peaking is enabled. As the coring stage is in front of the peaking filter, 1 LSB noise will
not be peaked.
4.8.2
RGB Matrix
The chip contains three different matrices, one suited for EBU standards, one suited for
NTSC-Japan and one suited for NTSC-USA, which are selected via MAT. The signal
OUTFOR switches between YUV output or RGB output. The signal UVPOLAR inverts
the U and V channels and results in Y-U-V output. The standard magnitudes and angles
of the color-difference signals in the UV-plane are defined as follows:
MAT
Magnitudes
Angles
Standard
D1
D0
(B-Y)
(R-Y)
(G-Y)
(B-Y)
(R-Y)
(G-Y)
0
0
2.028
1.14
0.7
0
90
236
EBU
0
1
2.028
1.582
0.608
0
95
240
NTSC (Japan)
1
0
2.028
2.028
0.608
0
105
250
NTSC (USA)
1
1
Table 4-18
(reserved)
RGB matrices characteristics
The color saturation can be adjusted with SATADJ register in 16 steps between 0 and
1.875. Values above 1.0 may clip the chrominance signals.
Micronas
4-31
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.8.3
Frame Generation And Colored Background
With FRSEL a colored frame is added to the inset picture. The chip can display two
different types of frames, one simple monochrome frame and a more sophisticated
frame giving a three dimensional impression.
Figure 4-13 Normal frame and 3D frame
The frame elements are always placed outside the inset picture, except for the inner
shade of three dimensional frame or inner frame in multi-pip mode. There is no shift of
the inset picture position if the inset frame width is modified.
character
no
character
luminance
frame color
character background
transparent
char. background luminance
semi-transparent
PiP Picture
background
picture
frame
no
frame color
shades
no
dark/light
background
no
background color
frame color
Figure 4-14 Selectable picture configurations
Micronas
4-32
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
4096 frame colors are programmable by FRY, FRU, and FRV, 4 bits for each
component. Horizontal and vertical width of the frame are programmable independently
by FRWIDH and FRWIDV. If desired, frame color is displayed over the whole PIP size
or whole picture size of the main channel when PIPBG is set accordingly. 64 background
colors are programmable by BGY, BGU, BGV, 2 bits for each component. Alternatively
BGFRC sets the background to frame color.
4.8.4
16:9 Inset Picture Support
To remove dark stripes at 16:9 inset pictures the vertical display area is shrinkable with
VPSRED. The number of omitted lines depends on the vertical decimation factor.
vertical
decimation
factor
displayed
lines (50Hz)
displayed
lines (50Hz)
with reduction
displayed
lines (60Hz)
displayed
lines (60Hz)
with reduction
1
264
214
216
175
44
35
36
29
...
6
Table 4-19
Number of lines without and with reduction of vertical picture size
.
Figure 4-15 16:9 inset picture without and with reduction of vertical picture size
4.8.5
Parent Clock Generation
The phase of the output signals is locked to the rising edge of the horizontal sync pulse.
The frequency varies in a certain range to ensure correct aspect ratio for 16:9
applications depending on HZOOM. The horizontal and vertical scaling can be used for
all display frequencies.
Micronas
4-33
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
display
format
inset
picture
format
desired
PiP format
required
parent
frequency
4:3
4:3
4:3
4:3
4:3
16:9
16:9
Table 4-20
value of HZOOM
D2
D1
D0
27
0
0
0
16:9
20.25
0
0
1
4:3
4:3
36
0
1
0
16:9
16:9
36
0
1
0
Format conversion using HZOOM
For variations of parental horizontal frequency (e.g. VCR), a digital correction of the
position is useful to stabilize the picture (POSCOR). This circuit detects a varying
parental line frequency and moves the picture to the place, where it would have been
without this frequency deviation. The deviation is calculated once a field.
4.8.6
Select Signal
For controlling an external RGB or YUV switch a select signal is supplied. The delay of
this signal is programmable for adaptation to different external output signal processing
devices (SELDEL).
frame
PiP signal
OUTx
picture
SEL
SELDEL
Figure 4-16 Select timing
4.8.7
Automatic Brightness Reduction
Displaying a bright PIP picture, the beamcurrent-limitation of the parent system may
become active. This may cause the parent picture to be influenced by the inset picture.
Therefore a detection circuit reduces the brightness of the inset picture when the
average brightness is above a selectable threshold. After bright picture content has
disappeared, the initial brightness reappears. The threshold is adjustable via ABRTHD
and the speed via ABRSPD. Both settings have to be selected for parent system
accordingly.
Micronas
4-34
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.9
On Screen Display (OSD)
4.9.1
Display Format
The on screen display allows to insert a block of 5 characters into each of the PIP
pictures. The characters are placed in a box (background) whose width is 64 pixels and
height is 12 lines. This box is placed in the upper left corner of the PIP picture. 64
different characters are stored in a character ROM. Each character is defined by a pixel
matrix consisting of 10 lines and 12 pixels per line. A doubling of the character’s height
and width is achieved by CHRDHW. The OSD starting position is not influenced.
OSD display is also possible if PIP is switched off (DISPMOD =’100011’). Now 3 lines of
20 characters each are displayed at the PiP position.
Figure 4-17 Example of OSD-only mode
Figure 4-18 Example of transparent mode (normal and double size OSD)
4.9.2
Character Programming
The characters are programmed via I²C bus using a 7 bit code which is identical with the
ASCII code except for some of the special characters. The codes are stored in a
character RAM consisting of 60 cells. The character codes can be transmitted in two
ways: each character position can be addressed separately by its 7 bit address or the
characters can be written consecutively starting at an arbitrarily chosen position. In this
case the address is increased automatically. The 7 bit address consists of two parts: the
4 MSBs are used to chose one of the partial pictures and the 3 LSBs to select one of the
5 characters per block.
Micronas
4-35
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.9.3
Character and Character Background Color
The character’s color is either same as frame color (CHRFRC) or the character appears
with a grey value programmable with CHRY.
The character’s background box is influenced by CHRBGON and CHRBGY. It can be
made transparent so that behind the characters the inset picture becomes visible.
Alternatively the semi-transparent mode can be chosen. At this mode the background
box contains the original picture content with reduced luminance value. This mode offers
a good trade-off between reduction of visible display area and character readability.
4.10
DA-Conversion And RGB / YUV Switch
SDA 9589X and SDA 9489X include three 7bit DA-converters. Brightness BRTADJ,
Contrast CONADJ and overall amplitude PKLR, PKLG, PKLB of the output signal are
adjustable. External RGB or YUV signals can be connected to the inputs IN1...3. By
forcing the FSW input to high-level these signals are switched to the outputs OUT1...3
while the internal signals are switched off. The FSW input signal is passed through to the
SEL output. The setting of RGBINS determines wether an RGB insertion is possible and
which source, the external picture or the PiP, gets priority.
R/V
G/Y
B/U
RGBINS='10'
PIPON='1'
RGBINS='11'
PIPON='1'
OSD
OSD
OSD
OSD
RGBINS='00'
PIPON='1'
RGBIN='1X'
PIPON='0'
OSD
OSD
VSSA2
VDDA2
OUT1
OUT2
OUT3
SEL
INT
IN1
IN2
IN3
FSW
VSS
I2C
VSSA1
VDDA1
VREFH
VDD
VREFL
CVBS3
SCL
CVBS2
HSP
SDA
XQ
VSP
CVBS1
VREFM
XIN
SEL
PiP IV
RGB/VYU
FSW
OSD
OSD
Figure 4-19 Visualization of RGB/YUV insertion
The external RGB or YUV signals are each clamped to the reference levels of the DACs
to force uniform black levels in each channel. The clamping needs careful adjustment
especially for VGA applications. The position and the length of the blanking pulse as well
as the clamping pulse are adjustable (CLPPOS, CLPLEN). If READD is set to ’1’ (100Hz
mode), all pulses are shortened by one half. HZOOM influences the adjustment range of
Micronas
4-36
Preliminary Data Sheet
SDA 9489X
SDA 9589X
System Description
the clamping and blanking pulse because of the modified clock frequency, but the pulse
length is kept nearly constant.
Parent
Video
HSP
256 T
allowed
HSP range
b
BLANKP
a
c
CLAMPP
d
Figure 4-20 PIP horizontal blanking timing
READD
CLPDEL
CLPLEN
a (←s)
Blanking
Start
b (←s)
Blanking
Duration
c (←s)
Clamping
Start
d (←s)
Clamping
Duration
D2
D1
D0
D1
D0
0
0
0
0
0
0
-1.5
10.5
3
5
0
1
1
1
0
0
-11
10.5
-6.4
5
0
0
0
0
0
1
-1.5
7.9
2.2
3.8
0
1
1
1
0
1
-11.0
7.9
-7.3
3.8
1
0
0
0
0
0
-0.8
5.3
1.5
2.5
1
1
1
1
0
0
-5.5
5.3
-3.2
2.5
1
0
0
0
0
1
-0.8
4
1.1
1.9
1
1
1
1
0
1
-5.5
4
-3.6
1.9
Table 4-21
4.10.1
PIP horizontal blanking timing
Pedestal Level Adjustment
The pedestal level adjustment controlled by I2C signals BLKLR, BLKLG, BLKLB
enables the correction of small offset errors, possibly appearing at the successive
blanking stage of RGB processor. This adjustment has an effect on the setup level
during the active line interval of each channel like the brightness adjustment but has an
Micronas
4-37
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
enhanced resolution of 0.5 LSB. The maximum possible offset amounts to 7.5 LSBs. In
YUV mode (OUTFOR = ’1’) the action depends on the setting of BLKINVR and
BLKINVB. If BLKINVR (BLKINVB) is active the offset applies to the blank level of the
RV (BU) channel during the clamping interval for shifting the setup level to the negative
direction. In RGB mode (OUTFOR = ’0’) BLKINVR and BLKINVB have no effect.
4.10.2
Contrast, Brightness and Peak Level Adjustment
The peak level adjustment modifies the magnitude of each channel separately. It should
be used to adapt once the signal levels to the following stage. The contrast adjustment
influences all three channels and allows a further increase of 30% of the peak level
magnitude. The effect of the brightness adjustment depends on the selected output
mode (RGB/YUV). In YUV mode it changes the offset of the OUT2 (Y) signal only while
in RGB mode it changes the offset of all three channels at the same time. The brightness
increase is up to 20%.
OUTFOR = ’1’ (YUV Mode)
BLKINVR = BLKINVB = ’1’
BLKINVR = BLKINVB = ’0’
OUT1, 3
OUT1, 3
BLKLR = 15
BLKLR = 15
BLKLB = 15
BLKLB = 15
64
64
BLKLR = 0
BLKLB = 0
BLKLR = 0
BLKLB = 0
OUTFOR = ’0’ (RGB Mode)
BLKLR = 15
BLKLB = 15
BLKLG = 15
0
OUT1 - 3
BLKLR = 0
BLKLB = 0
BLKLG = 0
Figure 4-21 Pedestal level adjustment
Micronas
4-38
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
4.11
Data Slicer
Depending on SERVICE, Closed Caption data (’Line 21’) or WSS (Widescreen
signalling) is sliced by the digital data slicer and can be read out from I2C interface. The
line number of the sliced data is selectable with SELLNR. Therefore WSS and CC can
be processed in different regions (e.g. CC with PAL M). The Closed Caption data is
assumed to conform with the ITU standards EIA-608 and EIA-744-A. WSS data is
assumed to conform with ETS 300 294 (2nd edition, May 1996).
4.11.1
Closed Caption
The closed caption data stream contains different data services. In field 1 (line 21) the
captions CC1 and CC2 and the text pages T1 and T2 are transmitted whereas in field 2
(line 284) caption CC3, CC4, text T3, T4 and the XDS data are transmitted. For more
information please refer to the above mentioned standards.
Raw CC as well as prefiltered data is provided alternatively. With the built-in
programmable XDS-Filter (XDSCLS), the program-rating information (’V-chip’) as well
2
as others can be filtered out. The XDS filter reduce traffic on the I C bus and save
calculation power of the main controller. If no class filter is selected, all incoming data
2
(both fields) is sliced and provided by the I C interface. When one or more class filters
are chosen, only data in field 2 is sliced. Any combination of class filters is allowed. Each
’CLASS’ is divided into ’TYPES’ which can be sorted out by the XDS-secondary filter
(XDSTPE). Any combination of type filter is allowed. Some type filter require an
appropriate class filter.
4.11.2
Widescreen Signalling (WSS)
In WSS mode (SERVICE=’1’) no filtering is possible. All sliced data is passed to the
output registers. In this case XDSTPE selects the field number of the data to be sliced.
In Europe WSS carries for instance information about aspect ratio and movie mode.
4.11.3
Indication Of New Data
The sliced and possibly filtered data is available in DATAA and DATAB. The
corresponding status bits are DATAV and SLFIELD. When new data were received,
DATAV becomes ’1’ and the controller must read DATAA, DATAB and the status
information. After both data bytes were read DATAV becomes ’0’ until new data arrives.
It must be ensured that the data polling is activated once per field (16.7 or 20 ms) or
every second field (33.3 or 40 ms), depending on the slicer configuration and inset field
frequency. The field number of the data in DATAA and DATAB can be found in
SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always ’1’.
Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state
mode to be compatible with Micronas' SDA9388X/9389X PIP devices. It can also be
configured by IRQCON to output a single short pulse when new data is available or
behave equal to DATAV. In the last case the output remains active until the two data
Micronas
4-39
SDA 9489X
Preliminary Data Sheet
SDA 9589X
System Description
registers DATAA/DATAB are read. Both modes are useful to avoid continous polling of
the I2C bus. The micro-controller initiates I2C transfers only when required.
while (1){
i2c_read pip4_adr, status_reg_adr, status
if (status & data_valid_mask) {
i2c_read_inc pip4_adr, dataa_reg_adr, dataa, datab, status
process_data dataa, datab, status
}
}
Figure 4-22 Example in pseudo-code for reading the data
4.11.4
Violence Protection
The rating information is sent in the program rating packet of the current (sometimes
future) class in the XDS data stream. If only this information is desired the corresponding
XDS filter (class 01h, type 05h) should be used to suppress other data. The class/packet
bytes (0105h) precede the 2 bytes rating information. Each sequence is closed by the
end-of-packet byte (0fh) and a checksum. This checksum complements the byte
truncated sum of all bytes to 00h. Except comparison of the received rating with the
adjusted user rating threshold the micro-controller should check the parity of each byte
and validate the checksum to avoid miss-interpretation of wrong received data.
The SDA 9589X/SDA 9489X offer some alternatives to blocking the PIP channel
completely by switching it off (fig. (4-23)).
“Warning Message”
“Blue Screen”
“Mosaic”
THIS PROGRAM
CONTAINS VIOLENT
SCENES
Figure 4-23 Possibilities of PiP blocking
The Mosaic mode (MOSAIC) hides details of the picture by reduced sharpness and
increased aliasing. The picture looks scrambled and is less perceptible.
Micronas
4-40
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Application Examples
5
Application Examples
The following two figures show 100/120Hz applications with the Micronas Featurebox
SDA 9400/01. As the chip supports two I2C addresses and owns a RGB switch dual-PiP
applications are easy to implement. The arrangement for best possible performance is
shown in the fig. (5-1).
additional 1fH source
IN1-3
CVBS
(Y/C, YUV)
SDA9589X
SDA9589X
SDA9589X
HSP/VSP
OUT1-3
I2C
+3.3V
SDA9589X
SDA9589X
SDA 9400
IN1-3
CVBS
(Y/C, YUV)
SDA9589X
additional 2fH sources
HSP/VSP
OUT1-3
I2C
H/V2H
H/V1H
CVBS
(Y/C)
analog / digital
Frontend
Figure 5-1
YUV1H
Featurebox
i.e.SDA 9400
YUV2H
Backend
i.e. SDA9380
SDA 9589X application with insertion in front of the featurebox
The output of two ’SOPHISTICUS’ are connected to the YUV (or RGB) input of the video
processor of the main channel. Due to the 4:2:2 processing within the SDA 9400 the
inset picture remains brilliant.
SDA9589X
CVBS
(Y/C, YUV)
IN1-3
SDA9589X
HSP/VSP
SDA9400
SDA9589X
SDA 9400
OUT1-3
I2C
additional 2fH sources
H/V2H
H/V1H
CVBS (Y/C)
Figure 5-2
analog / digital
Frontend
YUV1H
Featurebox
i.e. SDA 9400
YUV2H
Backend
i.e. SDA9380
SDA 9589X application with insertion behind the featurebox
Connecting the SDA 9589X/SDA 9489X directly to the RGB input of the RGB processor
is possible as well. One picture is generated from SDA 9589X/SDA 9489X device, the
other one from the featurebox. This cheap implementation preserves the chroma of inset
channel at its full bandwidth, although frame mode is only possible for PiP pictures
Micronas
5-41
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Application Examples
smaller than 1/9. The output of an OSD/Text processor may be fed to the RGB switch of
the SDA 9589X/SDA 9489X.
Micronas
5-42
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
6
I2C Bus
6.1
I2C Bus Address
Write Address1
1
1
0
1
0
1
1
0
(D6h)
Read Address1
1
1
0
1
0
1
1
1
(D7h)
Table 6-1
Primary Address (pin 9=’low-level’)
Write Address2
1
1
0
1
1
1
1
0
(DEh)
Read Address2
1
1
0
1
1
1
1
1
(DFh)
Table 6-2
6.2
Secondary Address (pin 9 = ’high-level’)
I2C-Bus Format
WRITE
S 1101x110 A Subaddress A
Data Byte
A
****
A
P
READ
S 1101x110 A Subaddress A Sr 1101x111 A Data Byte n NA P
S: Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition /
NA: No Acknowledge
Write operation is possible at registers 00h-21h only, read operation is possible at
registers 28, 2Ah-2Ch only. An automatic address increment function is implemented.
Micronas
6-43
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
I2C bus Command Table
6.3
Subadd
(Hex)
Data Byte
00h
D7
D6
D5
D4
D3
D2
D1
D0
PIPON
CPOS1
CPOS0
YUVSEL
READD
PROGEN
FIESEL1
FIESEL0
01h
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0
02h
POSVER7 POSVER6 POSVER5 POSVER4 POSVER3 POSVER2 POSVER1 POSVER0
03h
04h
VFP3
VFP2
DISPSTD1 DISPSTD0
VFP1
VFP0
FREEZE
MOSAIC
PIPBG1
PIPBG0
05h
FPSTD1
FPSTD0
06h
HSPINV
VSPINV
07h
FRSEL
INFRM
VPSRED
FRWIDH2
08h
RGBINS1
RGBINS0
VERBLK
09h
POSCOR DISPMOD1 DISPMOD0 CLPDEL4
0Ah
AGCRES
AGCMD1
AGCMD0
0Bh
CVBSEL1
CVBSEL0
0Ch
PLLITC1
0Dh
HFP3
HFP2
HFP1
HFP0
SIZEHOR1 SIZEHOR0 SIZEVER1 SIZEVER0
FMACTP
HZOOM2
HZOOM1
HZOOM0
VSPDEL3
VSPDEL2
VSPDEL1
VSPDEL0
FRWIDH1
FRWIDH0
FRWIDV1
FRWIDV0
SELDOWN SELDEL3
SELDEL2
SELDEL1
SELDEL0
CLPDEL3
CLPDEL2
CLPDEL1
CLPDEL0
AGCVAL3
AGCVAL2
AGCVAL1
AGCVAL0
NOSIGB
CLMPID1
CLMPID0
CLMPIST1 CLMPIST0 LMOFST1
PLLITC0
NSRED1
NSRED0
YCDEL3
YCDEL2
YCDEL1
YCDEL0
CSTAND2
CSTAND1
CSTAND0
CSTDEX1
CSTDEX0
LOCKSP
CKILL1
CKILL0
0Eh
BGPOS
SCMIDL0
DEEMP1
DEEMP0
COLON
ACCFIX
CHRBW1
CHRBW0
0Fh
IFCOMP1
IFCOMP0
HUE5
HUE4
HUE3
HUE2
HUE1
HUE0
10h
SATNR
FMACTI
CPLLOF
SCADJ4
SCADJ3
SCADJ2
SCADJ1
SCADJ0
11h
CONADJ3
CONADJ2
CONADJ1
CONADJ0
BLKLR3
BLKLR2
BLKLR1
BLKLR0
12h
BRTADJ3
BRTADJ2
BRTADJ1
BRTADJ0
BLKLG3
BLKLG2
BLKLG1
BLKLG0
13h
TRIOUT
REFINT
BLKINVR
BLKINVB
BLKLB3
BLKLB2
BLKLB1
BLKLB0
14h
PKLR7
PKLR6
PKLR5
PKLR4
PKLR3
PKLR2
PKLR1
PKLR0
15h
PKLG7
PKLG6
PKLG5
PKLG4
PKLG3
PKLG2
PKLG1
PKLG0
16h
PKLB7
PKLB6
PKLB5
PKLB4
PKLB3
PKLB2
PKLB1
PKLB0
Micronas
VSPNSRQ VSPDEL4
LMOFST0
6-44
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subadd
(Hex)
Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
17h
MAT1
MAT0
BGY1
BGY0
FRY3
FRY2
FRY1
FRY0
18h
OUTFOR
UVPOLAR
BGU1
BGU0
FRU3
FRU2
FRU1
FRU0
19h
(reserved)
BGFRC
BGV1
BGV0
FRV3
FRV2
FRV1
FRV0
1Ah
SATADJ3†
SATADJ2
SATADJ1
SATADJ0†
YPEAK2
YPEAK1
YPEAK0
YCOR
1Bh
XDSCLS4
XDSCLS3
XDSCLS2
XDSCLS1
XDSCLS0
XDSTPE2
XDSTPE1
XDSTPE0
1Ch
UVSEQ
MPIPBG
SERVICE
SELLNR1
SELLNR0
IRQCON2
IRQCON1
IRQCON0
1Dh
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
PIPBLK
PALIDL1
PALIDL0
1Eh
POSOFV2 POSOFV1 POSOFV0 POSOFH4 POSOFH3 POSOFH2 POSOFH1 POSOFH0
1Fh
(reserved)
(reserved)
(reserved)
VSHRNK4 VSHRNK3 VSHRNK2 VSHRNK1 VSHRNK0
20h
(reserved)
(reserved)
(reserved)
HSHRNK4 HSHRNK3 HSHRNK2 HSHRNK1 HSHRNK0
21h
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
CLPLEN1
CLPLEN0
22h
PIPHLT
ABRTHD3
ABRTHD2
ABRTHD1
ABRTHD0
ABRSPD2
ABRSPD1
ABRSPD0
23h
INFRMOD DISPMOD6 DISPMOD5 DISPMOD4 DISPMOD3 DISPMOD2 WIPESP1† WIPESP0
24h
CZMEN
CZMSP1
CZMSP0
(reserved)
25h
CHRFRC
CHRDHW
CHRY1
CHRY0
26h
OSDON
CHRADR6 CHRADR5 CHRADR4 CHRADR3 CHRADR2 CHRADR1 CHRADR0
27h
CHRCLR
CHRCOD6 CHRCOD5 CHRCOD4 CHRCOD3 CHRCOD2 CHRCOD1 CHRCOD0
28h
FRMMD
PIPSTAT
SYNCST1
SYNCST0
CKSTAT
STDET2
STDET1
STDET0
29h
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
2Ah
DATAA7
DATAA6
DATAA5
DATAA4
DATAA3
DATAA2
DATAA1
DATAA0
2Bh
DATAB7
DATAB6
DATAB5
DATAB4
DATAB3
DATAB2
DATAB1
DATAB0
DEVICE1
DEVICE0
PRNSTD
PALID
DATAV
SLFIELD
2Ch
WRPOS3
WRPOS2
WRPOS1
WRPOS0
CHRBGY1 CHRBGY0 CHRBGON CHRBGON
1
0
After power on the grey marked data bits are set to '1', all other to ‘0‘.
Micronas
6-45
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
I2C Bus Command Description
6.4
Subaddress 00h
PIPON
D7
PiP on
switches the PIP insertion on
0
PIP insertion off
1
PIP insertion on
CPOS
Coarse position
D6
D5
coarse positioning of the picture
0
0
upper left position
0
1
upper right position
1
0
lower left position
1
1
lower right position
YUVSEL
D4
YUV Select
select YUV mode
0
CVBS or Y/C source
1
YUV source
READD
D3
Read Double Mode
double read frequency for compatibility with systems that use 2fH
(e.g.100 Hz, progressive)
0
PIP display with single read frequency and 2x oversampling
1
PIP display with double read frequency
Micronas
6-46
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
PROGEN
Progressive Scan Enable
D2
for compatibility with progressive scan systems
0
each line of PIP is read once (normal operation)
1
each line of PIP is read twice (line doubling operation)
FIESEL
Field Select
D1
D0
set field or frame display mode
0
0
frame mode (if possible)
0
1
field mode (first field only)
1
0
field mode (second field only)
1
1
field mode (one of both)
Subaddress 01h
POSHOR
D7-D0
Horizontal Picture Position
horizontal position adjustment of the PIP in steps of 4 pixel
shift direction depends on the coarse positioning of the picture
Subaddress 02h
POSVER
D7-D0
Micronas
Vertical Picture Position
vertical position adjustment of the PIP in steps of 1 lines
shift direction depends on the coarse positioning of the picture
6-47
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
Subaddress 03h
HFP
Horizontal Fine Positioning
D7
D6
D5
D4
1
0
0
0
changes the position of the horizontal
acquisition window by steps of 2 pixel
-16 pixel (-0.8 ←s), most right position of
the image
..
0
0
0
0
0 pixel, nominal center position
Note
values refer to
the
undecimated
picture
..
0
1
1
1
VFP
+14 pixel (0.7 ←s), most left position
Vertical Fine Positioning
D3
D2
D1
D0
1
0
0
0
changes the position of the vertical
acquisition window by steps of 1 line
-8 lines, most upper position of the image
..
0
0
0
0
0 lines, nominal center position
Note
values refer to
the
undecimated
picture
..
0
1
1
1
+7 lines, most lower position
Subaddress 04h
DISPSTD
Display Standard
D7
D6
0
0
PIP depends on detected parent standard (multi pip) or inset standard
(single pip)
0
1
PIP display is always in 625 line mode
1
0
PIP display is always in 525 line mode
1
1
freeze last detected display standard and size
Micronas
selects the line standard of PIP display
6-48
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
FREEZE
D5
Freeze Picture
interrupts the inset picture writing and displays still picture
0
live picture
1
still picture
MOSAIC
D4
Mosaic Mode
hides picture details, intended for use with parental control
0
mosaic mode off
1
mosaic mode on
SIZEHOR
Horizontal Size
D3
D2
horizontal decimation
0
0
reduction = 2
0
1
reduction = 3
1
0
reduction = 4
1
1
reduction = 6
SIZEVER
Vertical Size
D1
D0
0
0
reduction = 2
0
1
reduction = 3
1
0
reduction = 4
1
1
reduction = 6
Micronas
vertical decimation
6-49
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
Subaddress 05h
FPSTD
Force Parent Standard
D7
D6
forces the parent standard to one of the following modes
0
0
auto-detect parent standard
0
1
50Hz/625 lines parent standard forced
1
0
60Hz/525 lines parent standard forced
1
1
freeze last detected standard
PIPBG
PIP Background Display
D5
D4
selects the background display
0
0
PIP visible, no background display
0
1
PIP invisible, background display in PIP
1
0
PIP visible, full screen background display
1
1
PIP invisible, background display in PIP and full screen background
FMACTP
D3
Frame Mode Activation Parent
selects the parent condition for the activation of the frame mode
0
Frame mode active for standard parent video sources only
1
Frame mode active for some nonstandard sources also
HZOOM
Horizontal Zoom
D2
D1
D0
0
0
0
27.34 MHz
0
0
1
20.25 MHz
0
1
0
35.27 MHz
0
1
1
25.43 MHz
1
0
0
26.67 MHz
1
0
1
20.63 MHz
1
1
0
34.17MHz
1
1
1
28.04 MHz
Micronas
selects the parent (display) clock frequency
6-50
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 06h
HSPINV
D7
Horizontal Sync Pulse Inversion
inverts the polarity of HSP
0
no inversion, raising edge is sync reference
1
HSP inverted, falling edge is sync reference
VSPINV
D6
Vertical Sync Pulse Inversion
inverts the polarity of VSP
0
no inversion, raising edge is sync reference
1
VSP inverted, falling edge is sync reference
VSPNSRQ
D5
Vertical Sync Pulse Noise Reduction
activates automatic V insertion that generates vertical sync pulses in
case of missing external VSP
0
on
1
off
VSPDEL
Vertical Sync Pulse Delay
D4
D3
D2
D1
D0
0
0
0
0
0
delay of the vertical sync pulse
in steps of 128 parent clocks
Note
no delay (0)
delay
depends on
HZOOM
...
1
1
1
1
1
maximum delay, 4096 clocks of
parent frequency
Subaddress 07h
FRSEL
D7
Frame Select
selects between the normal frame and the shaded frame
0
normal frame
1
shaded frame with 3D impression
Micronas
6-51
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
INFRM
Inner Frame activation
D6
actives inner frame (4 pixel width, 2 lines height) for multi-PIP display
0
inner frame off
1
inner frame on
VPSRED
D5
Vertical Picture Size Reduction
reduces vertical picture size to suppress black bars in 16:9 programs
0
no reduction
1
reduction on
FRWIDH
Frame Width Horizontal
D4
D3
D2
0
0
0
adjusts the horizontal width of the PIP frame in steps of one
pixel
no horizontal frame
...
1
1
1
7 pixel
FRWIDV
D1
D0
0
0
Frame Width Vertical
adjusts the vertical width of the PIP frame in steps of one line
no vertical frame
...
1
1
3 lines
Subaddress 08h
RGBINS
RGB Insertion
D7
D6
0
0
no external insertion possible, FSW input inactive
0
1
external insertion forced (FSW = 1)
1
0
external insertion with FSW possible (priority of FSW input)
1
1
external insertion with FSW possible (priority of PIP)
Micronas
controls the insertion of external RGB/YUV sources
6-52
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
VERBLK
D5
Vertical Blanking
switches the vertical blanking mode
0
blanking level at DAC outputs only during line-blanking intervals
1
blanking level at DAC outputs during line-blanking intervals and fieldblanking intervals, 16 lines following the parent vertical synchronization
pulse are blanked
SELDOWN
Select Down
D4
switches the driver type at the output of the SEL pin
0
open source output
1
TTL output
SELDEL
Select Delay
D3
D2
D1
D0
adjusts the delay of select signal
1
0
0
0
-8 clock periods of display clock
..
0
0
0
0
0 clock periods of display clock
..
0
1
1
1
+7 clock cycles of display clock
Subaddress 09h
POSCOR
D7
Position Correction
activates correction of display position
0
position correction disabled
1
position correction enabled
Micronas
6-53
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
DISPMOD
Display Mode
D6
D5
selects display modes with equal pictures
0
0
single PiP mode
0
1
3 x1/9 PiP (same content)
1
0
4 x1/16 PiP (same content)
1
1
(reserved)
CLPDEL
Clamping Delay
D4
D3
D2
D1
D0
0
0
0
0
0
delay of the clamping pulse for the external RGB/YUV
inputs in steps of 8 parent clock periods
no delay (0)
...
1
1
1
1
1
maximum delay, 256 clock periods of parent
frequency
Subaddress 0Ah
AGCRES
D7
Automatic Gain Control Reset
resets AGC
0
normal operation
1
reset of AGC
AGCMD
AGC Mode
D6
D5
0
0
evaluation of sync height and ADC overflow
0
1
evaluation of sync height only
1
0
evaluation of ADC overflow only
1
1
AGC fixed (gain depends on AGCVAL)
Micronas
controls the AGC operation
6-54
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
AGCVAL
Automatic Gain Control Value
D4
D3
D2
D1
0
0
0
0
AGC value for fixed mode (AGCMD=’11’)
input voltage 0.5 Vpp
..
1
0
0
0
input voltage 1 Vpp
..
1
1
1
1
input voltage 1.5 Vpp
NOSIGB
No Signal Behavior
D0
controls behavior if synchronization is not possible (no source applied)
0
noisy picture
1
colored background
Subaddress 0Bh
CVBSEL
CVBS Select
D7
D6
select CVBS source
0
0
CVBS1
0
1
CVBS2
1
0
Y/C (Y@CVBS2 / C@CVBS3)
1
1
CVBS3
CLMPID
Clamping Duration
D5
D4
0
0
0.5←s
0
1
0.9←s
1
0
1.2←s
1
1
1.5←s
Micronas
adjusts duration of clamping pulse for ADC (inset channel)
6-55
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
CLMPIST
Clamping Pulse Start
D3
D2
adjusts delay of clamping pulse for ADC refered to the horizontal sync
0
0
1.0←s
0
1
1.5←s
1
0
2.0←s
1
1
2.5←s
LMOFST
Luminance Offset
D1
D0
modifies black to blank level offset
0
0
no offset
0
1
offset of 16 LSB
1
0
offset of -8 LSB
1
1
offset of -16 LSB
Subaddress 0Ch
PLLITC
Inset PLL Time Constant
D7
D6
0
0
VCR1 (very fast)
0
1
VCR2
1
0
TV1
1
1
TV2 (very slow)
NSRED
switches the time constant of the inset PLL
Noise Reduction Inset PLL
D5
D4
0
0
noise reduction disabled
0
1
weak noise reduction
1
0
heavy noise reduction
1
1
medium noise reduction
Micronas
selects the level of noise reduction
Note
may cause trouble for VCR
signals
6-56
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
YCDEL
Y/C Delay
D3
D2
D1
D0
1
0
0
0
adjusts the delay between luminance and chrominance
-8 pixel (-0.4 ←s with respect to undecimated picture)
..
0
0
0
0
0 pixel
..
0
1
1
+7 pixel (0.35 ←s)
1
Subaddress 0Dh
CSTAND
Color Standard
D7
D6
D5
forces the desired color standard
0
0
0
automatic standard identification
0
0
1
NTSC-M
0
1
0
PAL-N (Argentina)
0
1
1
PAL-M
1
0
0
NTSC44
1
0
1
PAL-B/G/H/I/D
1
1
0
SECAM
1
1
1
PAL60
CSTDEX
Color Standard Exclusion
D4
D3
excludes standards from automatic standard identification
0
0
ignore PAL-M / PAL-N
0
1
ignore SECAM, PAL B/G, PAL60, NTSC4.4
1
0
ignore PAL-M /PAL-N / NTSC-M
1
1
ignore PAL-M / PAL-N / NTSC4.4 / PAL60
LOCKSP
D2
Standard Identification Speed
sets the speed of the color standard recognition
0
medium
1
fast
Micronas
6-57
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
CKILL
D1
D0
0
Color Killer Threshold
damping of color carrier to switch color off
Note
0
-30 dB
0
1
-18 dB
1
0
-24 dB
only valid if color killer
active (COLON=’0’),
values are
approximative
1
1
color always off
Subaddress 0Eh
BGPOS
D7
Burst Gate Position
adjusts position of burst gate (SECAM only)
0
normal position
1
0.5 ←s delayed
SCMIDL
D6
SECAM Identification Level
changes SECAM identification sensitivity
0
default
1
enhanced
DEEMP
Deemphase Selection
D5
D4
adjusts SECAM deemphase filter
0
0
Filter1
0
1
ITU recommendation
1
0
Filter2
1
1
Filter3
COLON
Color On
D3
disable color killer
0
color killer active
1
color forced on
Micronas
6-58
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
ACCFIX
D2
Disable Automatic Chroma Control
disables the automatic chroma control (ACC)
0
ACC active
1
ACC fixed (ACC set to nominal value)
CHRBW
Chroma Bandwidth
D1
D0
PAL
SECAM
remark
0
0
wide
small
adjusts chroma bandwidth
0
1
medium
medium
1
0
reserved
1
1
small
wide
Subaddress 0Fh
IFCOMP
IF-Compensation Filter
D7
D6
equalizes the IF-stage characteristic
0
0
no filtering
0
1
chroma bandpass active
1
0
IF-compensation bandpass (6dB/octave)
1
1
reserved
HUE
Hue Control
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
phase of color
subcarrier for NTSC
remark
-44.8°
skin color becomes
greenish
..
0
0
0
0
0
0
0°
..
0
1
Micronas
1
1
1
1
43.4°
skin color becomes
redish
6-59
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
Subaddress 10h
SATNR
D7
Satellite Noise Reduction
stabilizes the horizontal PLL for bad satellite signals („fishes“)
0
disabled
1
enabled
FMACTI
D6
Frame Mode Activation Inset
sets the inset condition for the activation of the frame mode
0
frame mode only active for standard inset video sources
1
enhanced frame mode activation range
CPLLOF
D5
Chroma PLL Off
opens loop of chroma PLL (only for test and servicing)
0
chroma PLL active
1
chroma PLL opened (free running oscillator)
SCADJ
Color Subcarrier Adjustment
D4
D3
D2
D1
D0
0
0
0
0
0
color subcarrier frequency fine adjustment
max. negative deviation (-150 ppm)
...
0
0
1
1
1
default (for nominal crystal frequency
...
1
1
1
1
1
max. positive deviation (+310 ppm)
Subaddress 11h
CONADJ
Contrast Adjustment
D7
D6
D5
D4
0
0
0
0
adjusts the contrast of the picture, acts on OUT1-OUT3
nominal contrast
..
1
1
Micronas
1
1
+30% contrast increase
6-60
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
BLKLR
Blanking Level Red
D3
D2
D1
D0
0
0
0
0
adjusts the pedestal level of the OUT1 channel in steps of
0.5LSB
no pedestal
..
1
1
1
1
+7.5LSB offset
Subaddress 12h
BRTADJ
Brightness Adjustment
D7
D6
D5
D4
0
0
0
0
adjusts the brightness of the picture, acts on OUT1-OUT3 in
RGB mode (YUVFOR = ’0’) and on OUT1 in YUV mode
(YUVFOR = ’1’)
nominal brightness
..
1
1
1
1
+20% brightness increase
BLKLG
Blanking Level Green
D3
D2
D1
D0
0
0
0
0
adjusts the pedestal level of the OUT2 channel in steps of
0.5LSB
no pedestal
..
1
1
1
1
+7.5LSB offset
Subaddress 13h
TRIOUT
D7
Tristate Output
sets OUT1-OUT3 to tristate mode (high resistance)
0
normal operation, outputs are active
1
pins OUT1-3 are in tri-state mode
Micronas
6-61
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
REFINT
D6
Refresh Intervall
changes the refresh rate of eDRAM
Note
0
normal refresh
let it to this default value
1
fast refresh
BLKINVR
D5
Blanking Inversion Red
inverts the sign of the OUT1 channel offset (BLKLR)
0
offset added during the active picture
1
offset added during blanking
BLKINVB
D4
Blanking Inversion Blue
inverts the sign of the OUT3 channel offset (BLKLB)
0
offset added during the active picture
1
offset added during blanking
BLKLB
Blanking Level Blue
D3
D2
D1
D0
0
0
0
0
adjusts the pedestal level of the OUT3 channel in steps of
0.5LSB
no pedestal
..
1
1
Micronas
1
1
+7.5LSB offset
6-62
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 14h
PKLR
Peak Level Red
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
peak to peak output
voltage of the
OUT1 channel
Note
0.3 Vpp
values refer to
contrast
(CONADJ)
and
brightness
(BRTADJ) at
minimum
...
1
1
0
0
0
0
0
0
1 Vpp
...
1
1
1
1
1
1
1
1
1.2 Vpp
Subaddress 15h
PKLG
Peak Level Green
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
peak to peak
output voltage of
the OUT2 channel
Note
0.3 Vpp
values refer to
contrast
(CONADJ)
and
brightness
(BRTADJ) at
minimum
...
1
1
0
0
0
0
0
0
1 Vpp
...
1
1
Micronas
1
1
1
1
1
1
1.2 Vpp
6-63
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
Subaddress 16h
PKLB
Peak Level Blue
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
peak to peak
output voltage of
the OUT2 channel
Note
0.3 Vpp
values refer
to contrast
(CONADJ)
and
brightness
(BRTADJ)
at minimum
...
1
1
0
0
0
0
0
0
1 Vpp
...
1
1
1
1
1
1
1
1
1.2 Vpp
Subaddress 17h
MAT
RGB Matrix Select
D7
D6
0
0
EBU- Matrix
0
1
NTSC-Japan Matrix
1
0
NTSC-USA Matrix
1
1
(reserved)
BGY
D5-D4
FRY
D3-D0
Micronas
selects the RGB matrix coefficients for YUV to RGB conversion
Background Color Y
adjusts the Y background color component
the values gives the two MSBs of the Y background signal
Frame Color Y
adjusts the Y frame color component
the value gives the 4 MSBs of the Y frame signal
6-64
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 18h
OUTFOR
D7
Output Format
switches between RGB output and YUV output
0
RGB output signals, matrix active
1
YUV output signals
UVPOLAR
UV Polarity
D6
switches between UV or inverted UV output, has no influence in RGB
mode
0
+U / +V output
1
-U / -V output
BGU
D5-D4
Background Color U
adjusts the U background color component
the values gives the two MSBs of the U background signal
FRU
D3-D0
Frame Color U
adjusts the U frame color component
the value gives the 4 MSBs of the U frame signal
Subaddress 19h
BGFRC
D6
Background Frame Color
selects background color table or frame color table for background
color
0
background color according to BGY, BGU, BGV
1
background color according to FRY, FRU, FRV
Micronas
6-65
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
BGV
D5-D4
Background Color V
adjusts the V background color component
the values gives the two MSBs of the V background signal
FRV
D3-D0
Frame Color V
adjusts the V frame color component
the value gives the 4 MSBs of the V frame signal
Subaddress 1Ah
SATADJ
Color Saturation Adjustment
D7
D6
D5
D4
0
0
0
0
adjusts the color saturation in steps of x/8
no color
..
1
0
0
0
nominal saturation
..
1
1
1
1
1.875 times saturation
YPEAK
Y Peaking Adjustment
D3
D2
D1
adjusts luminance peaking
0
0
0
no peaking
0
1
1
recommended value
1
1
1
strongest peaking
YCOR
D0
Y Coring Enable
suppresses noise introduced by peaking
0
coring off
1
1LSB coring
Micronas
6-66
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 1Bh
XDSCLS
XDS Class Select
D7
D6
D5
D4
D3
Closed Caption XDS-Primary Filter (Class)
0
0
0
0
0
transparent, no filtering
1
X
X
X
X
’Current’ class selected
X
1
X
X
X
’Future’ class selected
X
X
1
X
X
’Channel’ class selected
X
X
X
1
X
’Miscellaneous’ class selected
X
X
X
X
1
’Public Services’ class selected
XDSTPE
XDS Type Select/WSS Field Select
D2
D1
D0
XDS-Secondary
Filter Type
Meaning
WSS
field
Note
0
0
0
all
no filtering
0
0
1
05h
program rating
1
0
1
0
01h, 04h
time information
only
0/1
0
1
1
40h
out of band only
0/1
1
0
0
01h, 02h, 03h, 04h,
0Dh, 40h
VCR information
0/1
behavior of
these bits
depends
on
selected
dataservice
0
1
0
1
01h, 04h, 05h
time information
and program rating
0/1
1
1
0
05h, 40h
out of band and
program rating
0/1
1
1
1
01h, 02h, 03h, 04h,
05h, 0Dh, 40h
VCR information
and program rating
0/1
Subaddress 1Ch
UVSEQ
D7
UV Sequence
changes the UV multiplex sequence
remark
0
U and V are correct
valid only if YUVSEL=’1’
1
U and V are exchanged
Micronas
6-67
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
MPIPBG
D6
Multi-PIP Background
selects the background color for multi-PIP mode
0
black
1
same as background color
SERVICE
D5
Data Service Select
selects data service for slicing
0
Closed Caption
1
Widescreen Signalling (WSS)
SELLNR
D4
D3
0
Select Line Number
line number of data service field 0 (field1)
remark
0
[NTSC] 20 (283), [PAL M] 17 (280)
WSS
0
1
[NTSC] 21 (284), [PAL M] 18 (281)
Closed Caption
1
0
[PAL B/G] 22 (329)
Closed Caption
1
1
[PAL B/G] 23 (330)
WSS
IRQCON
Interrupt Request Pin Configuration
D2
D1
D0
0
0
0
tri-state (high-Z)
0
0
1
interrupt, when new data received
(neg. polarity)
0
1
0
interrupt, when new data received
(pos. polarity)
0
1
1
equivalent to DATAV for both
registers (neg. polarity)
1
0
0
equivalent to DATAV for both
registers (pos. polarity)
1
0
1
inset V-pulse (neg. polarity)
pulse length is 50ns
1
1
0
inset field
high = first field, low =
second field,
1
1
1
inset clamping pulse (neg. polarity)
only for test purpuse
Micronas
output of INT pin is:
remark
pulse length is
approximately 2←s
6-68
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 1D
PIPBLK
D2
PIP Blank
blanks the current picture by setting it to background color
0
no blank
1
blanks the current selected (WRPOS) PIP
PALIDL
D1
D0
0
0
PAL ID Level
sensitivity of identification of PAL/NTSC signals
high rejection of PAL/NTSC
..
1
1
low rejection of PAL/NTSC
Subaddress 1Eh
POSOFV
Position Offset Vertical
D7
D6
D5
1
0
0
vertical position offset in steps of 4 lines
-16 lines
...
0
0
0
0 lines
...
0
1
1
+12 lines
POSOFH
Position Offset Horizontal
D4
D3
D2
D1
D0
1
0
0
0
0
horizontal position offset in steps of 16 pixel
-256 pixel
...
0
0
0
0
0
0 pixel
...
0
1
Micronas
1
1
1
+240 pixel
6-69
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
Subaddress 1Fh
VSHRNK
Vertical Shrink
D4
D3
D2
D1
D0
0
0
0
0
0
changes the vertical size in steps of 2
lines
Note
no shrink, picture size according to
SIZEVER
max. usable
value
depends on
SIZEVER
...
1
1
1
1
1
max. possible shrink
Subaddress 20h
HSHRNK
Horizontal Shrink
D4
D3
D2
D1
D0
0
0
0
0
0
changes the horzontal size in steps of
4 pixel
Note
no shrink, picture size according to
SIZEHOR
max. usable
value
depends on
SIZEVER
...
1
1
1
1
1
max. possible shrink
Subaddress 21h
CLPLEN
D1
D0
0
Clamping Pulse Length
clamping pulse
length
blanking duration
Note
0
5us
10.5us
0
1
3.75us
7.9us
1
0
2.5us
5.2us
the clamping pulse length
and the blanking is also
influenced by the setting
of READD and HZOOM
1
1
1.25us
2.6us
Micronas
6-70
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 22h
PIPHLT
D7
PIP Highlighting
highlights the current selected (WRPOS) PIPr
0
no highlighting
1
highlighting the PIP
ABRTHD
Automatic Brightness Reduction Threshold
D6
D5
D4
D3
threshold adjustment for reduction of luminance magnitude
0
0
0
0
ABR off
0
0
0
1
ABR threshold at luminance value of 240
..
1
1
1
1
ABR threshold at luminance value of 180
ABRSPD
Automatic Brightness Reduction Speed
D2
D1
D0
0
0
0
speed adjustment for reduction of luminance magnitude
2 fields
...
1
1
1
16 fields
Subaddress 23h
INFRMOD
D7
Inner Frame Modification
modifies the look of the frame for dual-PiP applications
0
inner frame suited for usage of single SDA 9589X/9489X applications
1
inner frame suited for usage of dual SDA 9589X/9489X applications
Micronas
6-71
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
DISPMOD
Display Mode
D6
D5
D4
D3
D2
0
0
0
0
0
selects the single PIP modes, MultiPIP modes or Double-Window mode
Note
Single PiP mode
see table 411 for
description
of modes
...
1
0
1
0
OSD only mode
WIPESP
Wipe Speed
D1
D0
selects the period for opening/closing the PIP window
0
0
wipe off
0
1
1/3 second
1
0
2/3 second
1
1
1 second
Subaddress 24h
CZMEN
D7
Continuos Zoom Enable
controls the update of the picture size
0
delayed execution of HDEC/VDEC/HSHRNK/VSHRNK update
1
picture size will be updated
CZMSP
Continuos Zoom Speed
D6
D5
0
0
no zoom
0
1
1 step per 1 fields
1
0
1 step per 2 fields
1
1
1 step per 4 fields
Micronas
speed setting for continous zooming Note
1 step means 20 pixel and 8
lines (PAL) or 6 lines (NTSC)
decrement or increment
6-72
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
WRPOS
Write Position
D3
D2
D1
D0
position of the current written
picture
Note
0
0
0
0
first writing position = first picture
1
second writing position
number of last valid writing
position depends on
display mode (DISPMOD)
0
0
0
..
1
0
0
1
maximum writing position
Subaddress 25h
CHRFRC
D7
Character Frame Color
modifies the character color
0
character luminance table used
1
frame color table used
CHRDHW
D6
Character Double Height and Width
doubles the characters’ height and width
0
normal height and width
1
double height and width
CHRY
D5
D4
0
Character Luminance
character luminance level (IRE)
Note
0
60
0
1
70
1
0
80
valid only if CHRFRC =
’0’, character
chrominance is 0 IRE
1
1
90
Micronas
6-73
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
CHRBGY
Character Background Luminance
D3
D2
character background luminance level (IRE)
0
0
10
0
1
20
1
0
30
1
1
40
CHRBGON
Character Background On
D1
D0
defines the characters’ background
0
0
no character background (transparent
mode)
0
1
character background (dependent on
CHRBGY)
1
0
semi-transparent mode (black&white)
1
1
semi-transparent mode (colored)
Note
not possible in case of
active background in PiP
Subaddress 26h
OSDON
D7
OSD On
switches OSD on
0
OSD off
1
OSD on
Micronas
6-74
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
CHRADR
Character Address
D6
D5
D4
D3
D2
D1
D0
No. picture
No. character
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
...
...
...
0
0
0
0
1
0
0
0
4
0
0
0
1
0
0
1
1
1
...
...
...
0
11
4
1
0
1
1
1
0
Note
will be autoincremented
with every
write access
to CHRCOD
Subaddress 27h
CHRCLR
D7
Character Clear
resets all characters to ’blank’ character
0
no blank
1
character reset
CHRCOD
D6-D0
Character Code
character code, see Appendix
Subaddress 28h
FRMMD
D7
Frame Mode Indication
PIP displays field or frame mode
0
field mode, one field is repeated twice
1
frame mode, both fields are displayed
Micronas
6-75
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
PIPSTAT
D6
PIP Status
indication of visibility of PIP, corresponds to PIPON
0
PIP off
1
PIP on
SYNCST
Inset Synchronization Status
D5
D4
inset synchronization PLL is
0
0
0
1
1
0
locked to CVBS signal (60 Hz)
1
1
locked to CVBS signal (50 Hz)
not locked to CVBS signal
CKSTAT
D3
Color Killer Status
chroma is
0
off
1
on
STDET
Standard Detection
D2
D1
D0
0
0
0
nonstandard or standard not detected
0
0
1
NTSC-M
0
1
0
PAL-M
0
1
1
NTSC44
1
0
0
PAL60
1
0
1
PAL-N
1
1
0
SECAM
1
1
1
PAL-B/G
Micronas
detected color standard
6-76
Preliminary Data Sheet
SDA 9489X
SDA 9589X
I2C Bus
Subaddress 2Ah
DATAA
D7-D0
First Data Byte
first word of sliced data, D7 = MSB, D0 = LSB
Subaddress 2Bh
DATAB
D7-D0
Second Data Byte
second word of sliced data, D7 = MSB, D0 = LSB
Subaddress 2Ch
DEVICE
Device Identification
Micronas PIP IC
D5
D4
0
0
SDA 9488X (PIP IV Basic)
0
1
SDA 9489X (PIP IV Advanced)
1
0
SDA 9588X (OCTOPUS)
1
1
SDA 9589X (SOPHISTICUS)
PRNSTD
D3
Parent Standard Detection
status of parent (display) standard detection
0
60Hz field frequency detected
1
50Hz field frequency detected
PALID
D2
PAL Identification
identification of PAL signal
Note
0
NTSC signal
not valid if STDET= ’000’
1
PAL signal
Micronas
6-77
SDA 9489X
Preliminary Data Sheet
SDA 9589X
I2C Bus
DATAV
D1
Data Valid
new data indication, used for data flow control (polling mode)
0
data read via I2C or no data available
1
new data received and available in DATAA and DATAB
SLFIELD
D0
Sliced Data Field Number
DATAA and DATAB are from
0
first field
1
second field
Micronas
6-78
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Pin Description
7
Pin Description
pin
schematic
1 (XIN)
2 (XQ)
remark
VDD
VDD
XIN
crystal oscillator, input
can be used for
external clocking
VDD
XQ
3 (HSP)
4 (VSP)
schmitt-trigger input
with high hysteresis,
for best jitter
performance use
pulses with steep
slopes
VDD
HSP
VSP
5 (SDA)
6 (SCL)
VDD
SDA
SCL
low-side driver not
used for SCL, slope of
acknowledge is limited
slope
control
9 (I2C)
VDD
I2C
Micronas
I2C address selection,
only static switch
supported
7-79
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Pin Description
pin
schematic
remark
10 (INT)
VDD
INT
11 12 13
(IN1 IN2 IN3)
clamped RGB/YUV
video inputs, if not
used let open or
connect with 10nF to
ground
VDD
IN1
IN2
IN3
+ V
CL
-
14 (FSW)
fast switch input
VDD
FSW
15 (SEL)
VDD
SEL
Micronas
low-side driver can be
disabled (open source
mode)
7-80
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Pin Description
pin
schematic
16 (OUT3)
17 (OUT2)
18 (OUT1)
24 (CVBS3)
26 (CVBS2)
28 (CVBS1)
Micronas
RGB/YUV video
outputs
VDD
OUT1
OUT2
OUT3
+
-
21 (VREFH)
25 (VREFL)
27 (VREFM)
remark
VDD
VDD
reference voltage for
ADC and DAC
VDD
VREFM
VREFH
VDD VDD
VREFL
clamped video inputs
CVBS1
CVBS2
CVBS3
7-81
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Absolute Maximum Ratings
8
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
remark
Ambient Temperature
TA
0
70
°C
Storage Temperature
Tstg
-55
125
°C
Junction Temperature
Tj
125
°C
Soldering Temperature
Tsold
260
°C
duration <10s
Input Voltage
Vi
-0.3V
VDD+0.3V
1
except SDA, SCL,
HSP, VSP
Vi
-0.3
5.5
V
SDA, SCL, HSP,
VSP only
VQ
-0.3V
VDD+0.3V
1
except SDA
VQ
-0.3
5.5
V
SDA only
VDD
-0.3
3.6
V
-0.25
0.25
V
0.86
W
Output Voltage
Supply Voltages
Supply Voltage Differentials
Total Power Dissipation
Ptot
Latch-Up Protection
ILU
-100
100
mA
ESD robustness
VESD,HBM
-2000
2000
V
HBM: 1.5kτ, 100pF
All voltages listed are referenced to ground (0V, VSS) except where noted.
Stresses above those listed here may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Micronas
8-82
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Recommended Operating Range
9
Recommended Operating Range
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
Supply Voltages
VDDxx
3.15
3.3
3.45
V
Ambient Temperature
TA
0
25
70
°C
Remark
Main horizontal / vertical Sync Inputs: VSP, HSP
HSP Signal Frequency
fPH
15.000
15.625
16.250
kHz
1fH mode
HSP Signal Frequency
fP2H
30.000
31.250
32.500
kHz
2fH mode
HSP Signal Frequency
fP2H
11.7
25.2
48
kHz
VGA mode
HSP Signal Rise Time
tr
100
ns
noisefree
transition
HSP Signal High Time
tHH
200
ns
HSP Signal Low Time
tLH
900
ns
VSP Signal Frequency
fPV
50/60
Hz
VSP Signal Frequency
fPV
100/120
Hz
VSP Signal High Time
tHV
200
ns
VSP Signal Low Time
tLV
200
ns
scan rate
conversion
Inset Input: CVBS1, CVBS2, CVBS3
Horizontal Frequency
fH
15.734
kHz
60 Hz input
Horizontal Frequency
fH
15.625
kHz
50 Hz input
Amplitude of
synchronization pulse
Vsync
300
mV
length of horizontal
synchronization puls
tDH
4.7
←s
length of vertical
synchronization puls
tDV
22
←s
chroma amplitude
ACHR
300
mV
burst
Input Coupling
Capacitors
CCLI
necessary
for proper
clamping
CVBS Source
Resistance
RSRCI
Micronas
2.2
10
100
nF
100
500
τ
9-83
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Recommended Operating Range
Parameter
Input Voltage Range at
inputs CVBS1-3
Symbol
Vi
Limit Values
Unit
Remark
dep. on AGC
setting
min.
typ.
max.
0.5
1
1.5
V
Reference Voltages:VREFL, VREFM, VREFH
Reference Voltage Low
VREFL
1.05
1.11
1.17
V
Reference Voltage
Middle
VREFM
1.81
1.91
2.00
V
Reference Voltage High
VREFH
3.15
3.3
VDDA1
V
2.2
10
100
nF
100
500
τ
RGB/YUV Switch:IN1,IN2,IN3,FSW
Input Coupling
Capacitors
CCLS
Source Resistance
RSRCS
Input Voltage Range at
inputs IN1-3
VIS
0.3
1
1.6
V
Input Voltage Range at
inputs FSW
VIF
0.3
1
1.6
V
Input Voltage Range for
Address
VSA1
0
0.8
V
Input Voltage Range for
Address
VSA2
2.8
VDDD
V
necessary
for proper
clamping
I²C Address: I2C
Fast I²C Bus (All values are referred to min(VIH) and max(VIL))
This specification of the bus lines need not be identical with the I/O stages
specification because of optional series resistors between bus lines and I/O pins.
SCL Clock Frequency
fSCL
0
Inactive Time Before
Start Of Transmission
tBUF
1.3
µs
Set-Up Time Start
Condition
tSU;STA
0.6
µs
Hold Time Start
Condition
tHD;STA
0.6
µs
SCL Low Time
tLOW
1.3
µs
Micronas
400
kHz
9-84
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Recommended Operating Range
Parameter
Symbol
Limit Values
min.
typ.
Unit
Remark
max.
SCL High Time
tHIGH
0.6
µs
Set-Up Time DATA
tSU;DAT
100
ns
Hold Time DATA
tHD;DAT
0
0.9
µs
SDA/SCL Rise/Fall
Times
tR, tF
20+$
300
ns
Set-Up Time Stop
Condition
tSU;STO
0.6
Capacitive Load/Bus Line
Cb
$=0.1Cb/pF
µs
400
pF
I²C Bus Inputs/Output: SDA, SCL
High-Level Input Voltage
VIH
3V
5.5V
1
Low-Level Input Voltage
VIL
-0.25V
1.5
V
50
ns
6
mA
Spike Duration At Inputs
Low-Level Output
Current
0
0
IOL
also for
SDA/SCL
input stages
Digital To Analog Converters (7-bit):OUT1, OUT2, OUT3
Load resistance
RL
Load capacitance
CL
10
kτ
30
pF
20.252
MHz
deviation
outside this
range will
cause color
decoding
failures
100
10-6
deviation
outside this
range will
cause color
decoding
failures
40
10-6
Crystal Specification: XIN, XQ
Frequency
fxtal
20.248
Maximum Permissible
Frequency Deviation
αfmax/
fxtal
-100
Recommended
Permissible Frequency
Deviation
αf/fxtal
-40
Micronas
20.25
0
9-85
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Recommended Operating Range
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
12
27
39
Remark
pF
Load Capacitance
CL
Series resonance
resistance
RS
25
τ
Motional capacitance
C1
27
fF
Parallel capacitance
C0
7
pF
In the operating range the functions given in the circuit description are fulfilled.
Micronas
9-86
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Characteristics
10
Characteristics
(Assuming Recommended Operating Conditions)
Parameter
Symbol
Average total supply
current
IDDtot
Limit Values
Unit
min.
typ.
max.
180
210
240
Remark
mA
All Digital Inputs (TTL, I²C)
Input Capacitance
7
CI
Input Leakage Current
pF
-10
10
µA
incl. leakage
current of
SDA output
stage
SEL
High-Level Output
Voltage
VOH
2.4 V
VDD
V
IOH=-200µA
High-Level Output
Voltage
VOH
1.5V
VDD
V
IOH=-4.5mA
Low-Level Output
Voltage
VOL
0.4
V
IOL=1.6mA,
only valid if
bit
SELDOWN=
1
FSW
Low-Level Input Voltage
VIL
-0.25
0.4
V
High-Level Input Voltage
VIH
0.9
VDD+0.5
V
Delay FSW in -> SEL out
10
ns
I²C Inputs: SDA/SCL
Schmitt Trigger
Hysteresis
Vhys
0.1
0.2
0.5
V
not tested
I²C Input / Output: SDA (Referenced to SCL; Open Drain Output)
Low-Level Output
Voltage
VOL
0.4
V
IOL=3mA
Low-Level Output
Voltage
VOL
0.6
V
IOL=max
Micronas
10-87
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Characteristics
Parameter
Symbol
Limit Values
min.
Output Fall Time from
min(VIH) to max(VIL)
tOF
typ.
20+0.1*
Cb /pF
Unit
Remark
250
ns
10pFCb40
0pF
100
nA
clamping
inactive
max.
Analog Inputs CVBS1, CVBS2, CVBS3
-100
CVBS Input Leakage
Current
IL
CVBS Input Capacitance
CI
Input Clamping Error
αCLE
-1
1
Input Clamping Current
|ICLP|
43
326
µA
max. Input Clamping
Current deviation
|ICLPx|/
|ICLP|
-40
40
%
Reference Voltage
Difference
VREFHVREFL
0.5
1.5
V
VDDA1=3.3
V
D.C. Differential
Nonlinearity
DNL
-1
1
LSB
VREFH-VREFL
= max
Crosstalk between CVBS
Inputs
CT
7
pF
-50
LSB settled state
dependent
on clamping
error
dB
Digital To Analog Converters (7-bit): Outputs OUT1, OUT2, OUT3
D.C. Differential
Nonlinearity
DNLE
-0.5
Full Range Output
Voltage
VOL
0.3
Full Range Output
Voltage
VOH
Micronas
0.5
1.6
LSB
V
CON,
UAMP,
VAMP,
YAMP = 0
V
CON,
UAMP,
VAMP,
YAMP =
max
10-88
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Characteristics
Parameter
Symbol
Limit Values
Unit
Remark
CON,
UAMP,
VAMP,
YAMP =
default,
VREF =
const.
min.
typ.
max.
1
1.1
V
3
%
Output Voltage
VO
0.9
Deviation of OUT1-3
(matching)
MCH
-3
Contrast Increase
αCON
30
%
Output Amplitude Ratio
(UOH-UOL)/UOL
αAMP
400
%
Brightness Increase
αBRT
15
LSB
Pedestal Level variation
αPED
+/- 7.5
LSB
1.2
Vpp
RGB / YUV switch; IN1, IN2, IN3
Input Voltage Range
αVI
Bandwith (-3dB)
BW
Gain
G
Gain Difference RGB
αG
Crosstalk Between Inputs
MHz
RL>10kτ;
CL=20pF
3
%
f<4MHz
CTI
-40
dB
f=5MHz,
(R-G-B, UV)
Crosstalk Between Inputs
CTI
-45
dB
f=5MHz,
(Y-UV)
Isolation (off state)
D
dB
f=5MHz
Clamping Level
Difference at Output
αCLPE
mV
between
external and
internal
source
kHz
VCR1 and
VCR2
25
0.9
1.1
45
15
Colordecoder/Synchronization and Luminance Processing
Horizontal PLL pull-inrange
Micronas
αfHf/fH
13.3
17.4
10-89
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Characteristics
Parameter
Symbol
Limit Values
min.
typ.
Unit
Remark
max.
Horizontal PLL pull-inrange
αfHf/fH
13.3
17.4
kHz
TV1 and
TV2
Amplitude of
synchronization pulse
Vsync
60
600
mV
AGC set to
1.2 V input
signals
length of horizontal
synchronization pulse
tDH
1.8
←s
length of vertical
synchronization pulse
tDV
22
←s
ACC range
CRACC
-24
+6
dB
AGC range
CRAGC
-7.5
+2
dB
Chroma PLL pull-inrange
αfSC
+/- 500
Hz
nominal
crystal
frequency
Data slicer
Data level
VD
266
350
434
mV
CC
Data height
αVD
280
350
420
mV
CC
Eye Height
EH
26.6
Co Channel Distortion
CD25
174
mV
25kHz
Co Channel Distortion
CD50
155
mV
50kHz
Max. permissible Noise
N
20
dB
%
The listed characteristics are ensured over the operating range of the integratd circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at TA = 25 C and the given supply
voltage.
Micronas
10-90
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
11
Diagrams
Figure 11-1 Display mode 0 with picture sizes 1/4 and 1/9
Figure 11-2 Display mode 0 with picture sizes 1/16 and 1/36
Micronas
11-91
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
0
1
2
3
Figure 11-3 Display mode 0 (with scaling) and display mode 11
Figure 11-4 Display mode 2 and 3 (all pictures with same content)
0
1
0
1
Figure 11-5 Display modes 4 and 5
Micronas
11-92
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Diagrams
0
1
0
2
1
2
Figure 11-6 Display modes 6 and 7
0
1
2
3
0
1
2
3
Figure 11-7 Display modes 8 and 12
0
4
1
2
3
5
0
2
1
3
4
5
Figure 11-8 Display modes 9 and 10
Micronas
11-93
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
Figure 11-9 Display modes 13 and 14
0
1
2
0
1
2
3
3
4
5
4
5
6
7
6
7
8
8
9
10
11
Figure 11-10 Display modes 15 and 16
0
1
2
3
4
5
6
0
7
1
8
2
9
3
10
4
5
6
7
8
Figure 11-11 Display modes 17 and 18
Micronas
11-94
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
Display mode 20 (Double Window 1) and 19 (Double Window 1.5)
Figure 11-12 Combination of display modes 17/ 18 and 9/ 10 (dual PiP application)
Figure 11-13 Display modes 19 and 20 (dual PiP application)
Micronas
11-95
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
0000001=01
0000010=02
0000011=03
0000100=04
0000101=05
0000110=06
0000111=07
0001000=08
0001001=09
0001010=0A
0001011=0B
0100000=20
0100001=21
0100011=23
0100100=24
0100101=25
0101010=2A
0101011=2B
0101101=2D
0101111=2F
0110000=30
0110001=31
0110010=32
0110011=33
0110100=34
0110101=35
0110110=36
0110111=37
0111000=38
0111001=39
0111100=3C
0111101=3D
0111110=3E
0111111=3F
1000001=41
1000010=42
1000011=43
1000100=44
1000101=45
1000110=46
1000111=47
1001000=48
1001001=49
1001010=4A
1001011=4B
1001100=4C
1001101=4D
1001110=4E
1001111=4F
1010000=50
1010001=51
1010010=52
1010011=53
1010100=54
1010101=55
1010110=56
1010111=57
1011000=58
1011001=59
1011010=5A
1011011=5B
1011101=5D
1011110=5E
1011111=5F
Figure 11-14 OSD Character Set
Micronas
11-96
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Diagrams
Teletext or
OSD processor
optional 2 n d PIP
R G B FSW
CVBS 1
SEL
R(V)
G (Y)
B(U)
CVBS 2
CVBS 3
RGB
Processor
TUNER1
HSP
VSP
TUNER2
CVBS 1
Main Channel
Decoder & Sync
R
G
B
Y
U
V
Figure 11-15 General Application with 3 CVBS sources and Teletext-Processor
Teletext or
OSD processor
optional 2 n d PIP
R G B FSW
Y, U, V
RGB
Processor
SEL
R(V)
G (Y)
B(U)
HSP
VSP
TUNER2
CVBS 1
Main Channel
Decoder & Sync
R
G
B
Y
U
V
Figure 11-16 General Application with YUV source from DVD
Micronas
11-97
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
1/4 PiP
10
10
20
6
10
20
30
30
40
3
0
6
gain [dB]
gain [dB]
0
1/9 PiP
10
3
40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
1/16 PiP
7
8
9
10
3
0
6
10
gain [dB]
gain [dB]
6
1/36 PiP
10
3
0
20
6
10
20
30
30
40
5
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
10
4
frequency [MHz]
frequency [MHz]
0
1
2
3
4
5
6
frequency [MHz]
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
7
8
9
10
40
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
Figure 11-17 Characteristic (PAL) of luminance decimation filter for different
peaking factors
Micronas
11-98
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Diagrams
1/4 PiP
10
10
20
6
10
20
30
30
40
3
0
6
gain [dB]
gain [dB]
0
1/9 PiP
10
3
40
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
1/16 PiP
0
3
10
6
0
10
gain [dB]
gain [dB]
6
7
8
9
10
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
20
1/36 PiP
3
6
10
20
30
30
40
5
frequency [MHz]
frequency [MHz]
10
4
0
1
2
3
4
5
6
frequency [MHz]
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
7
8
9
10
40
0
1
2
3
4
5
6
7
8
9
10
frequency [MHz]
YPEAK = '010'
YPEAK = '100'
YPEAK = '111'
Figure 11-18 Characteristic (NTSC) of luminance decimation filter for different
peaking factors
Micronas
11-99
SDA 9489X
Preliminary Data Sheet
SDA 9589X
Diagrams
10
10
0
3
6
10
gain [dB]
gain [dB]
0
20
30
40
3
6
10
20
30
0
0.25
0.5
0.75
1
1.25 1.5
frequency [MHz]
1.75
2
2.25
2.5
1/4 PiP
1/9 PiP
1/16 PiP
1/36 PiP
40
0
0.25
0.5
0.75
1
1.25 1.5
frequency [MHz]
1.75
2
2.25
2.5
1/4 PiP
1/9 PiP
1/16 PiP
1/36 PiP
10
gain [dB]
0
3
6
10
20
30
40
0
0.25
0.5
0.75
1
1.25 1.5
frequency [MHz]
1.75
2
2.25
2.5
1/4 PiP
1/9 PiP
1/16 PiP
1/36 PiP
Figure 11-19 Characteristic of chrominance decoder filter (small, medium and
narrow)
Micronas
11-100
Preliminary Data Sheet
SDA 9489X
SDA 9589X
Application Circuit
12
Application Circuit
Y
U
CVBS1
CVBS1
Y
CVBS2
or
V
or
C
C18
10n
C19
10n
C20
10n
CVBS3
R6
75
R7
75
R8
75
C1 *
27p
C8
10n
1
X1
20.25 MHz
C2 *
27p
2
HP
3
VP
4
SDA
5
R2
100
SCL
6
7
+3.3V
L1
10←
C3
10←
C4
10n
+3.3V
J1
I2C
Address
C5
10n
RVIN
D6h
8
9
10
11
C6
10n
GYIN
DEh
12
C7
10n
BUIN
13
14
FSW
R3
75
R4
75
XQ
VREFM
HSP
CVBS2
VSP
SDA
SCL
VDD
VSS
I2C
INT
VREFL
SDA9589X
R1
100
CVBS1
XIN
CVBS3
VSSA1
VDDA1
VREFH
VSSA2
VDDA2
IN1
OUT1
IN2
OUT2
IN3
FSW
OUT3
SEL
28
27
C9
1←
26
25
24
L2
10←
C10
10n
C11
1←
C12
10n
23
L3
10←
22
21
+3.3V
C13
10←
C14
10n
C15
1←
C16
10n
C17
10←
+3.3V
20
19
18
17
16
15
RVOUT
GYOUT
BUOUT
SEL
R5
75
INT
*) exact value depends on crystal specification
Micronas
12-101
SDA 9489X, SDA 9589X
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-562-1PD
102
PRELIMINARY DATA SHEET
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas