MICRONAS BSP3505D

PRELIMINARY DATA SHEET
MICRONAS
Edition Oct. 21, 1998
6251-481-1PD
BSP 3505D
Baseband
Sound Processor
MICRONAS
BSP 3505D
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
4
4
4
1.
1.1.
1.2.
1.3.
Introduction
BSP 3505D Integrated Functions
Features of the DSP-Section
Features of the Analog Section
5
5
5
6
6
6
2.
2.1.
2.1.1.
2.2.
2.3.
2.4.
Architecture of the BSP 3505D
Analog Section and SCART Switching Facilities
Standby Mode
BSP 3505DAudio Baseband Processing
Clock and Crystal Specifications
Digital Control Output Pins
7
8
9
9
9
9
9
10
3.
3.1.
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
I2C Bus Interface: Device and Subaddresses
Protocol Description
Proposal for BSP 3505D I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start Up Sequence: Power Up and I2C-Controlling
11
11
12
12
13
13
14
14
15
15
16
17
17
17
17
18
18
18
19
19
19
20
20
20
20
4.
4.1.
4.2.
4.3.
4.4.
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.4.7.
4.4.8.
4.4.9.
4.4.10.
4.4.11.
4.4.12.
4.4.13.
4.4.14.
4.5.
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.5.5.
Programming the BSP 3505D
Register ‘MODE_REG’
DSP Write Registers: Table and Addresses
DSP Read Registers: Table and Addresses
DSP Write Registers: Functions and Values
Volume Loudspeaker Channel
Balance Loudspeaker Channel
Bass Loudspeaker Channel
Treble Loudspeaker Channel
Loudness Loudspeaker Channel
Spatial Effects Loudspeaker Channel
Volume SCART1
Channel Source Modes
Channel Matrix Modes
SCART Prescale
Definition of Digital Control Output Pins
Definition of SCART-Switching Facilities
Beeper
Automatic Volume Correction (AVC)
DSP Read Registers: Functions and Values
Quasi-Peak Detector
BSP Hardware Version Code
BSP Major Revision Code
BSP Product Code
BSP ROM Version Code
2
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PRELIMINARY DATA SHEET
BSP 3505D
Contents, continued
Page
Section
Title
21
21
23
26
30
31
31
32
34
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.5.1.
5.5.2.
5.5.3.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Configurations
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
37
6.
Application Circuit
40
7.
Appendix A: BSP 3505D Version History
40
8.
Data Sheet History
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3
BSP 3505D
PRELIMINARY DATA SHEET
Baseband Sound Processor
1.2. Features of the DSP-Section
Release Notes: The hardware description in this
document is valid for the BSP 3505D version A2.
– flexible selection of audio sources to be processed
1. Introduction
– simple controlling of volume, bass, treble, loudness,
and spatial effects
The BSP 3505D is designed as a single-chip Baseband
Sound Processor for applications in analog and digital
TV sets, video recorders, and satellite receivers.
The IC is produced in submicron CMOS technology, and
is fully pin and software compatible to the MSP 34xx
family. The BSP 3505D is available in a PLCC68,
PSDIP64, PSDIP52, PQFP80, and in a PQFP44 package.
Note: The BSP 3505D version has reduced control registers and less functional pins. The remaining registers
are software compatible to the MSP 34xxD. The pinning
is compatible to the MSP 34xxD.
1.1. BSP 3505D Integrated Functions
– Stereo baseband input via integrated A/D converters
– Two stereo D/A converters
– AVC: Automatic Volume Correction
– Bass, treble, volume, loudness processing
– Full SCART in/out matrix without restrictions
– spatial effect (pseudostereo / basewidth enlargement)
– Digital control output pins D_CTR_OUT0/1
– digital baseband processing: volume, bass, treble,
loudness, and spatial effects
1.3. Features of the Analog Section
– two selectable analog stereo audio baseband inputs
(= two SCART inputs)
input level: ≤2 V RMS,
input impedance: ≥25 kΩ
– one selectable analog mono input:
input level: ≤2 V RMS,
input impedance: ≥15 kΩ
– stereo high-quality A/D converter, S/N-Ratio: ≥85 dB
– 20 Hz to 20 kHz bandwidth for SCART-to-SCARTcopy facilities
– loudspeaker: stereo four-fold oversampled D/A-converter
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kΩ
S/N-ratio: ≥85 dB at maximum volume
max. noise voltage in mute mode: ≤10 µV
(BW: 20 Hz ...16 kHz)
– stereo four-fold oversampled D/A converter supplying
a stereo SCART-output
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kΩ,
S/N-Ratio: ≥85 dB (20 Hz...16 kHz)
– Reduction of necessary controlling
– Less external components
2 I2C
MONO IN
SCART1 IN
2
SCART2 IN
2
2
Loudspeaker
OUT
2
SCART
OUT
BSP 3505D
Fig. 1–2: Main I/O Signals BSP 3505D
Tuner
SIF
VIF
FM/AM Mono
SCART1
SCART
Inputs
SCART2
2
Loudspeaker
BSP 3505D
2
SCART1
SCART
Output
2
Fig. 1–1: Typical BSP 3505D application
4
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BSP 3505D
PRELIMINARY DATA SHEET
SCART_IN
2. Architecture of the BSP 3505D
SC1_IN_L/R
Fig. 2–2 shows a simplified block diagram of the IC. Its
architecture is split into two main functional blocks:
to Audio Baseband
Processing (DSP_IN)
SC2_IN_L/R
A
1. DSP (digital signal processing) section performing
audio baseband processing
D
SCARTL/R
2. analog section containing two A/D-converters,
four D/A-converters, and SCART-switching facilities.
MONO_IN
S1
2.1. Analog Section and SCART Switching Facilities
intern. Signal Lines
The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 2–1.
SCART_OUT
Pins
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 4. Programming the BSP 3505D).
SC1_OUT_L/R
from Audio Baseband
Processing (DSP_OUT)
D
SCART1_L/R
A
S2
2.1.1. Standby Mode
Fig. 2–1: SCART-Switching Facilities (see 4.4.12.)
positions show the default configuration after Power
On Reset.
Note: SCART_OUT is undefined after RESET!
If the BSP 3505D is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1 and S2 (see Fig. 2–1) maintain their position and
function. This facilitates the copying from selected
SCART-inputs to SCART-output in the TV-set’s standby
mode.
In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 2–1. This action takes place after the first
I2C transmission into the DSP part. By transmitting the
ACB register first, the individual default setting mode of
the TV set can be defined.
XTAL_IN
XTAL_OUT
Clock
D_CTR_OUT0/1
DSP
Mono
LOUDSPEAKER L
D/A
DACM_L
LOUDSPEAKER R
D/A
DACM_R
Loudspeaker
MONO_IN
SC1_IN_L
A/D
SCARTL
SCART1_L
D/A
SC1_OUT_L
A/D
SCARTR
SCART1_R
D/A
SC1_OUT_R
SCART1
SC1_IN_R
SCART
SC2_IN_L
SCART2
SC2_IN_R
SCART Switching Facilities
Fig. 2–2: Architecture of the BSP 3505D
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5
BSP 3505D
PRELIMINARY DATA SHEET
2.2. BSP 3505D Audio Baseband Processing
All audio baseband functions are performed by digital
signal processing (DSP). The DSP functions are
grouped into three processing parts: input preprocessing, channel source selection, and channel postprocessing (see Fig. 2–3).
The input preprocessing is intended to form a standardized signal level.
All input and output signals can be processed simultaneously.
2.3. Clock and Crystal Specifications
Remark on using the crystal: External capacitors at
each crystal pin to ground are required. The higher the
capacitors, the lower the clock frequency results.
The nominal free running frequency should match the
center of the tolerance range between 18.433 and
18.431 MHz as closely as possible.
2.4. Digital Control Output Pins
The static level of two output pins of the BSP 3505D
(D_CTR_OUT0/1) is switchable between HIGH and
LOW by means of the I2C-bus. This enables the controlling of external hardware controlled switches or other
devices via I2C-bus (see section 4.4.11.)
Analog
Inputs
SCARTL
Loudspeaker
Channel
Matrix
Prescale
Channel Souce Select
SCARTR
SCART
AVC
Bass
Treble
ȍ
Volume
Loudspeaker L
Balance
Loudspeaker R
Volume
SCART1_L
Loudspeaker
Outputs
Loudness
Beeper
SCART1
Channel
Matrix
SCART
Output
SCART1_R
Quasi peak readout L
Quasi-Peak
Detector
SCART
Internal signal lines (see Fig. 2–1)
Quasi peak readout R
Fig. 2–3: Audio Baseband Processing (DSP-Firmware)
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BSP 3505D
PRELIMINARY DATA SHEET
3. I2C Bus Interface: Device and Subaddresses
As a slave receiver, the BSP 3505D can be controlled via
I2C bus. Access to internal memory locations is
achieved by subaddressing. The DSP processor part
has its own subaddressing register bank.
In order to allow for more BSP or MSP ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to high, low, or left
open, the BSP 3505D responds to changed device addresses. Thus, three identical devices can be selected.
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
The IC is selected by asserting a special device address
in the address part of an I2C transmission. A device address pair is defined as a write address (80, 84, or 88hex)
and a read address (81, 85, or 89hex). Writing is done by
sending the device write address first, followed by the
subaddress byte, two address bytes, and two data bytes. Reading is done by sending the device write address, followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device read
address (81, 85, or 89hex) and reading two bytes of data.
Due to the internal architecture of the BSP 3505D the IC
cannot react immediately to an I2C request. The typical
response time is about 0.3 ms for the DSP processor
part. If the receiver (BSP) can’t receive another complete byte of data until it has performed some other function; for example, servicing an internal interrupt, it can
hold the clock line I2C_CL LOW to force the transmitter
into a wait state. The positions within a transmission
where this may happen are indicated by ’Wait’ in section
3.1. The maximum Wait-period of the BSP during normal
operation mode is less than 1 ms.
I2C-Bus conditions caused by BSP hardware problems:
In case of any internal error, the BSPs wait-period is extended to 1.8 ms. Afterwards, the BSP does not acknowledge (NAK) the device address. The data line will
be left HIGH by the BSP and the clock line will be released. The master can then generate a STOP condition
to abort the transfer.
By means of NAK, the master is able to recognize the error state and to reset the IC via I2C-Bus. While transmitting the reset protocol (s. 5.2.4.) to ‘CONTROL’, the
master must ignore the not acknowledge bits (NAK) of
the BSP.
A general timing diagram of the I2C Bus is shown in
Fig. 3–2.
Refer to Fig. 3–1: I2C Bus Protocol and section 3.2. Proposal for BSP 3505D I2C Telegrams.
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Low
High
Left Open
Mode
Write
Read
Write
Read
Write
Read
BSP device address
80hex
81hex
84hex
85hex
88hex
89hex
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Write
software reset
TEST
0000 0001
01
Write
only for internal use
WR_DSP
0001 0010
12
Write
write address DSP
RD_DSP
0001 0011
13
Write
read address DSP
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BSP 3505D
PRELIMINARY DATA SHEET
Table 3–3: Control Register (Subaddress: 00hex)
Name
Subaddress
MSB
14
13..1
LSB
CONTROL
00hex
1 : RESET
0 : normal
0
0
0
3.1. Protocol Description
Write to DSP
S
write
device
address
Wait
ACK
sub-addr
ACK
addr-byte
high
ACK
addr-byte low
ACK
data-byte high
Read from DSP
S
write
device
address
Wait
ACK
sub-addr
ACK
addr-byte
high
ACK
addr-byte
low
ACK
S
read
device
address
Wait
ACK
ACK
data-byte low
ACK
P
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ ÇÇÇ
data-byte
high
ACK
data-byte
low
NAK
P
Write to Control or Test Registers
S
write
device
address
Note: S =
P=
ACK =
NAK =
Wait =
Wait
ACK
sub-addr
ACK
data-byte high
ACK
data-byte low
ACK
P
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= BSP, gray)
or master (= CCU, hatched)
Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate ‘End of Read’
or from BSP indicating internal error state
I2C-Clock line held low by the slave (= BSP) while interrupt is serviced (<1.8 ms)
I2C_DA
S
1
0
P
I2C_CL
Fig. 3–1: I2C bus protocol
(MSB first; data must be stable while clock is high)
(Data: MSB first)
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BSP 3505D
PRELIMINARY DATA SHEET
FI2C
TI2C4
I2C_CL
TI2C1
TI2C5
TI2C3
TI2C6
TI2C2
I2C_DA as input
TI2COL2
I2C_DA
TI2COL1
as output
Fig. 3–2: I2C bus timing diagram
3.2. Proposal for BSP 3505D I2C Telegrams
3.2.1. Symbols
daw
dar
<
>
aa
dd
write device address
read device address
Start Condition
Stop Condition
Address Byte
Data Byte
3.2.2. Write Telegrams
<daw 00 d0 00>
<daw 12 aa aa dd dd>
write to CONTROL register
write data into DSP
3.2.3. Read Telegrams
<daw 13 aa aa <dar dd dd>
read data from DSP
3.2.4. Examples
<80 00 80 00>
<80 00 00 00>
<80 12 00 08 02 20>
Micronas
RESET BSP statically
clear RESET
set loudspeaker channel source
to SCART, stereo
9
BSP 3505D
PRELIMINARY DATA SHEET
3.3. Start Up Sequence: Power Up and I2C-Controlling
After power on or RESET (see Fig. 3–3), the IC is in an
inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C bus. Initialization must start with the MODE Register.
The reset pin should not be >0.45*DVSUP (see recommended conditions) before the 5 Volt digital power supply (DVSUP) and the analog power supply (AVSUP) are
>4.75 Volt AND the BSP clock is running. (Delay: 0.5 ms
typ, 2 ms max)
This means, if the reset low–high edge starts with a
delay of 2 ms after DVSUP and AVSUP >4,75 Volt, even
under worst case conditions, the reset is ok.
DVSUP/V
AVSUP/V
4.75
Oscillator
RESETQ
time / ms
max. 2
time / ms
min. 2
0.45 * DVSUP
time / ms
Fig. 3–3: Power-up sequence
10
Note: The reset should
not reach high level before the oscillator has
started. This requires a
reset delay of >2 ms
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
4. Programming the BSP 3505D
4.1. Register ‘MODE_REG’
The register ‘MODE_REG’ contains the control bits determining the operation mode of the BSP 3505D;
Table 4–1 explains all bit positions.
Table 4–1: Control word ‘MODE_REG’: All bits are “0” after power-on-reset
Register
Protocol
Write Address (hex)
Function
MODE_REG
long
0083
mode register
Bit
Function
Comment
Definition
[0]
not used
[1]
DCTR_TRI
[2]
not used
must be 1
[3–4]
not used
must be 0
[5]
not used
must be 1
[6–9]
not used
must be 0
[10–15]
not used
must be 0
Micronas
must be 0
Digital_Control_Output tristate
0 : active
1 : tristate
11
BSP 3505D
PRELIMINARY DATA SHEET
4.2. DSP Write Registers: Table and Addresses
Table 4–2: DSP Write Registers; Subaddress: 12hex; if necessary these registers are readable as well.
DSP Write Register
Address
High/
Low
Adjustable Range, Operational Modes
Reset Mode
Volume loudspeaker channel
0000hex
H
[+12 dB ... –114 dB, MUTE]
MUTE
L
1/8 dB Steps / Reduce Vol., Tone, Comprom.
00hex
H
[0..100 / 100 % and vv][–127..0 / 0 dB and vv]
100%/100%
L
[Linear mode / logarithmic mode]
linear mode
Volume / Clipping Mode loudspeaker
Balance loudspeaker channel [L/R]
0001hex
Balance Mode loudspeaker
Bass loudspeaker channel
0002hex
H
[+12 dB ... –12 dB]
0 dB
Treble loudspeaker channel
0003hex
H
[+12 dB ... –12 dB]
0 dB
Loudness loudspeaker channel
0004hex
H
[0 dB ... +17 dB]
0 dB
L
[NORMAL, SUPER_BASS]
NORMAL
H
[–100%...OFF...+100%]
OFF
L
[SBE, SBE+PSE]
SBE+PSE
H
[00hex ... 7Fhex],[+12 dB ... –114 dB, MUTE]
00hex
L
[Linear mode / logarithmic mode]
linear mode
H
[SCART]
FM/AM
L
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
H
[SCART]
FM/AM
L
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
H
[SCART]
FM /AM
L
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
Loudness Filter Characteristic
Spatial effect strength loudspeaker ch.
0005hex
Spatial effect mode/customize
Volume SCART1 channel
0007hex
Volume / Mode SCART1 channel
Loudspeaker channel source
0008hex
Loudspeaker channel matrix
SCART1 channel source
000Ahex
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
SCART1 channel matrix
Quasi-peak detector source
000Chex
Quasi-peak detector matrix
Prescale SCART
000Dhex
H
[00hex ... 7Fhex]
00hex
ACB Register (SCART Switching
Facilities)
0013hex
H/L
Bits [15..0]
00hex
Beeper
0014hex
H/L
[00hex ... 7Fhex]/[00hex ... 7Fhex]
0/0
Automatic Volume Correction
0029hex
H
[off, on, decay time]
off
4.3. DSP Read Registers: Table and Addresses
Table 4–3: DSP Read Registers; Subaddress: 13hex
DSP Read Register
Address
High/Low
Output Range
Quasi peak readout left
0019hex
H&L
[00hex ... 7FFFhex]
16 bit two’s complement
Quasi peak readout right
001Ahex
H&L
[00hex ... 7FFFhex]
16 bit two’s complement
12
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BSP 3505D
PRELIMINARY DATA SHEET
4.4. DSP Write Registers: Functions and Values
Write registers are 16 bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take
place in 16-bit words. Some of the defined 16-bit words
are divided into low [7..0] and high [15..8] byte, or in an
other manner, thus holding two different control entities.
All write registers are readable. Unused parts of the
16-bit registers must be zero. Addresses not given in this
table must not be written at any time!
4.4.1. Volume Loudspeaker Channel
Volume
Loudspeaker
0000hex
[15..4]
+12 dB
0111 1111 0000
7F0hex
+11.875 dB
0111 1110 1110
7EEhex
+0.125 dB
0111 0011 0010 732hex
0 dB
0111 0011 0000 730hex
–0.125 dB
0111 0010 1110
–113.875 dB
0000 0001 0010 012hex
–114 dB
0000 0001 0000 010hex
Mute
0000 0000 0000 000hex
RESET
Fast Mute
1111 1111 1110
72Ehex
FFEhex
The highest given positive 8-bit number (7Fhex) yields in
a maximum possible gain of 12 dB. Decreasing the volume register by 1 LSB decreases the volume by 1 dB.
Volume settings lower than the given minimum mute the
output. With large scale input signals, positive volume
settings may lead to signal clipping.
Micronas
The BSP 3505D loudspeaker volume function is divided
up in a digital and an analog section.
With Fast Mute, volume is reduced to mute position by
digital volume only. Analog volume is not changed. This
reduces any audible DC plops. Going back from Fast
Mute should be done to the volume step before Fast
Mute was activated.
Clipping Mode
Loudspeaker
0000hex
[3..0]
Reduce Volume
0000
RESET
0hex
Reduce Tone Control
0001
1hex
Compromise Mode
0010
2hex
If the clipping mode is set to “Reduce Volume”, the following clipping procedure is used: To prevent severe
clipping effects with bass or treble boosts, the internal
volume is automatically limited to a level where, in combination with either bass or treble setting, the amplification does not exceed 12 dB.
If the clipping mode is “Reduce Tone Control”, the bass
or treble value is reduced if amplification exceeds 12 dB.
If the clipping mode is “Compromise Mode”, the bass or
treble value and volume are reduced half and half if amplification exceeds 12 dB.
Example:
Vol.:
+6 dB
Bass:
+9 dB
Treble:
+5 dB
Red. Volume
3
9
5
Red. Tone Con.
6
6
5
Compromise
4.5
7.5
5
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BSP 3505D
PRELIMINARY DATA SHEET
4.4.2. Balance Loudspeaker Channel
4.4.3. Bass Loudspeaker Channel
Positive balance settings reduce the left channel without
affecting the right channel; negative settings reduce the
right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the
balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases
the balance by 1 dB.
Balance Mode
Loudspeaker
0001hex
[3..0]
linear
0000
RESET
0hex
0001
1hex
logarithmic
Bass Loudspeaker
0002hex
H
+20 dB
0111 1111
7Fhex
+18 dB
0111 1000
78hex
+16 dB
0111 0000
70hex
+14 dB
0110 1000
68hex
+12 dB
0110 0000
60hex
+11 dB
0101 1000
58hex
+1 dB
0000 1000
08hex
+1/8 dB
0000 0001
01hex
0 dB
0000 0000
RESET
00hex
–1/8 dB
1111 1111
FFhex
–1 dB
1111 1000
F8hex
Linear Mode
Balance Loudspeaker
Channel [L/R]
0001hex
H
Left muted, Right 100%
0111 1111
7Fhex
–11 dB
1010 1000
A8hex
Left 0.8%, Right 100%
0111 1110
7Ehex
–12 dB
1010 0000
A0hex
Left 99.2%, Right 100%
0000 0001
01hex
Left 100%, Right 100%
0000 0000
RESET
00hex
Left 100%, Right 99.2%
1111 1111
FFhex
Left 100%, Right 0.8%
1000 0010
82hex
Left 100%, Right muted
1000 0001
81hex
With positive bass settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with
volume, would result in an overall positive gain.
Logarithmic Mode
Balance Loudspeaker
Channel [L/R]
0001hex
H
Left –127 dB, Right 0 dB
0111 1111
7Fhex
Left –126 dB, Right 0 dB
0111 1110
7Ehex
Left –1 dB, Right 0 dB
0000 0001
01hex
Left 0 dB, Right 0 dB
0000 0000
RESET
00hex
Left 0 dB, Right –1 dB
1111 1111
FFhex
Left 0 dB, Right –127 dB
1000 0001
81hex
Left 0 dB, Right –128 dB
1000 0000
80hex
14
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
4.4.5. Loudness Loudspeaker Channel
4.4.4. Treble Loudspeaker Channel
Treble Loudspeaker
0003hex
H
+15 dB
0111 1000
78hex
+14 dB
0111 0000
70hex
+1 dB
0000 1000
08hex
+1/8 dB
0000 0001
01hex
0 dB
0000 0000
RESET
00hex
–1/8 dB
1111 1111
FFhex
–1 dB
1111 1000
F8hex
–11 dB
1010 1000
A8hex
–12 dB
1010 0000
A0hex
With positive treble settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with
volume, would result in an overall positive gain.
Loudness
Loudspeaker
0004hex
H
+17 dB
0100 0100
44hex
+16 dB
0100 0000
40hex
+1 dB
0000 0100
04hex
0 dB
0000 0000
RESET
00hex
Mode Loudness
Loudspeaker
0004hex
L
Normal (constant
volume at 1 kHz)
0000 0000
RESET
00hex
Super Bass (constant
volume at 2 kHz)
0000 0100
04hex
Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has
to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended
to set loudness to a value that, in conjunction with volume, would result in an overall positive gain.
By means of ‘Mode Loudness’, the corner frequency for
bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up.
The point of constant volume is shifted from 1 kHz to
2 kHz.
Micronas
15
BSP 3505D
PRELIMINARY DATA SHEET
4.4.6. Spatial Effects Loudspeaker Channel
16
Spatial Effect Strength
Loudspeaker
0005hex
H
Enlargement 100%
0111 1111
7Fhex
Enlargement 50%
0011 1111
3Fhex
Enlargement 1.5%
0000 0001
01hex
Effect off
0000 0000
RESET
00hex
Reduction 1.5%
1111 1111
FFhex
Reduction 50%
1100 0000
C0hex
Reduction 100%
1000 0000
80hex
Spatial Effect Mode
Loudspeaker
0005hex
[7..4]
Stereo Basewidth Enlargement (SBE) and
Pseudo Stereo Effect
(PSE). (Mode A)
0000
RESET
0000
0hex
Stereo Basewidth Enlargement (SBE) only.
(Mode B)
0010
2hex
Spatial Effect Customize Coefficient
Loudspeaker
0005hex
[3..0]
max high pass gain
0000
RESET
0hex
2/3 high pass gain
0010
2hex
1/3 high pass gain
0100
4hex
min high pass gain
0110
6hex
automatic
1000
8hex
0hex
There are several spatial effect modes available:
Mode A (low byte = 00hex) is compatible to the formerly
used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in
mono mode, Pseudo Stereo Effect is active; for stereo
signals, Pseudo Stereo Effect and Stereo Basewidth
Enlargement is effective. The strength of the effect is
controllable by the upper byte. A negative value reduces
the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is
rather close. For large screen TV sets, a more moderate
spatial effect is recommended. In mode A, even in case
of stereo input signals, Pseudo Stereo Effect is active,
which reduces the center image.
In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect
has to be switched on.
It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin
yields a flat response for center signals (L = R) but a high
pass function of L or R only signals. A value of 0110bin
has a flat response for L or R only signals but a lowpass
function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound
material by choosing an optimal high pass gain.
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
4.4.7. Volume SCART1
4.4.8. Channel Source Modes
Volume Mode SCART1
0007hex
[3..0]
Loudspeaker Source
0008hex
H
linear
0000
RESET
0hex
SCART1 Source
000Ahex
H
0001
1hex
Quasi-Peak
Detector Source
000Chex
H
logarithmic
NONE (MSP3410: FM)
0000 0000
RESET
00hex
NONE (MSP3410: NICAM)
0000 0001
01hex
SCART
0000 0010
02hex
Linear Mode
Volume SCART1
0007hex
H
OFF
0000 0000
RESET
00hex
0 dB gain
(digital full scale (FS)
to 2 VRMS output)
0100 0000
40hex
+6 dB gain (–6 dBFS
to 2 VRMS output)
0111 1111
7Fhex
Logarithmic Mode
4.4.9. Channel Matrix Modes
Loudspeaker Matrix
0008hex
L
SCART1 Matrix
000Ahex
L
Quasi-Peak
Detector Matrix
000Chex
L
SOUNDA / LEFT
0000 0000
RESET
00hex
Volume SCART1
0007hex
[15..4]
SOUNDB / RIGHT
0001 0000
10hex
+12 dB
0111 1111 0000
7F0hex
STEREO
0010 0000
20hex
+11.875 dB
0111 1110 1110
7EEhex
MONO
0011 0000
30hex
+0.125 dB
0111 0011 0010 732hex
0 dB
0111 0011 0000 730hex
–0.125 dB
0111 0010 1110
H
0000 0001 0010 012hex
Volume Prescale
SCART
000Dhex
–113.875 dB
–114 dB
0000 0001 0000 010hex
OFF
0000 0000
RESET
00hex
Mute
0000 0000 0000 000hex
RESET
0 dB gain (2 VRMS input to digital full scale)
0001 1001
19hex
+14 dB gain
(400 mVRMS input to
digital full scale)
0111 1111
7Fhex
Micronas
72Ehex
4.4.10. SCART Prescale
17
BSP 3505D
PRELIMINARY DATA SHEET
4.4.11. Definition of Digital Control Output Pins
ACB Register
0013hex
D_CTR_OUT0
low
(RESET)
high
x0
x1
D_CTR_OUT1
low
(RESET)
high
[15..14]
0x
1x
4.4.12. Definition of SCART-Switching Facilities
ACB Register
0013hex
[13..0]
DSP IN
Selection of Source:
* SC1_IN_L/R
MONO_IN
SC2_IN_L/R
Mute
xx
xx
xx
xx
xx00
xx01
xx10
xx11
xx00
xx00
xx00
xx10
0000
0000
0000
0000
SC1_OUT_L/R
Selection of Source:
SC2_IN_L/R
MONO_IN
SCART1 via D/A
SC1_IN_L/R
Mute
xx
xx
xx
xx
xx
01xx
10xx
11xx
01xx
11xx
x0x0
x0x0
x0x0
x1x0
x1x0
0000
0000
0000
0000
0000
4.4.13. Beeper
Beeper Volume
0014hex
H
OFF
0000 0000
RESET
00hex
Maximum Volume (full
digital scale FDS)
0111 1111
7Fhex
Beeper Frequency
0014hex
L
16 Hz (lowest)
0000 0001
01hex
1 kHz
0100 0000
40hex
4 kHz (highest)
1111 1111
FFhex
A squarewave beeper can be added to the loudspeaker
channel. The addition point is just before volume adjustment.
* = RESET position, which becomes active at the
time of the first write transmission on the control
bus to the audio processing part (DSP). By writing
to the ACB register first, the RESET state can be
redefined.
Note: After RESET, SC1_OUT_L/R is undefined!
Note: If “MONO_IN” is selected at the DSP_IN selection, the channel matrix mode of the corresponding output channel(s) must be set to “sound A”.
18
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
4.4.14. Automatic Volume Correction (AVC)
AVC
on/off
0029hex
[15.12]
AVC
off and Reset
of int. variables
0000
RESET
0hex
AVC
on
1000
8hex
AVC
Decay Time
0029hex
[11..8]
8 sec
4 sec
2 sec
20 ms
(long)
(middle)
(short)
(very short)
1000
0100
0010
0001
8hex
4hex
2hex
1hex
To reset the internal variables, the AVC should be
switched off and on during any channel or source
change. For standard applications, the recommended
decay time is 4 sec.
Note: AVC should not be used in any Dolby Prologic
mode, except PANORAMA, where no other than the
loudspeaker output is active.
4.5. DSP Read Registers: Functions and Values
Different sound sources fairly often do not have the
same volume level. Advertisement during movies, as
well, usually has a different (higher) volume level than
the movie itself. The Automatic Volume Correction
(AVC) solves this problem and equalizes the volume levels.
The absolute value of the incoming signal is fed into a
filter with 16 ms attack time and selectable decay time.
The decay time must be adjusted as shown in the table
above. This attack/decay filter block works similar to a
peak hold function. The volume correction value with its
quasi continuous step width is calculated using the attack/decay filter output.
The Automatic Volume Correction works with an internal
reference level of –18 dBFS. This means, input signals
with a volume level of –18 dBFS will not be affected by
the AVC. If the input signals vary in a range of –24 dB to
0 dB, the AVC compensates this.
Example: A static input signal of 1 kHz on Scart has an
output level as shown in the table below.
Scart Input
0 dbr = 2 Vrms
Volume
Correction
Main Output
0 dBr = 1.4 Vrms
0 dBr
–18 dB
–18 dBr
–6 dBr
–12 dB
–18 dBr
–12 dBr
–6 dB
–18 dBr
–18 dBr
–0 dB
–18 dBr
–24 dBr
+ 6 dB
–18 dBr
–30 dBr
+ 6 dB
–24 dBr
All readable registers are 16-bit wide. Transmissions via
I2C bus have to take place in 16-bit words. Single data
entries are 8 bit. Some of the defined 16-bit words are
divided into low and high byte, thus holding two different
control entities.
These registers are not writeable.
4.5.1. Quasi-Peak Detector
Quasi-Peak
Readout Left
0019hex
H+L
Quasi-Peak
Readout Right
001Ahex
H+L
Quasi peak readout
[0hex ... 7FFFhex]
values are 16 bit two’s
complement
The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is based on a filter time
constant:
attack-time: 1.3 ms
decay-time: 37 ms
Loudspeaker Volume = 73hex = 0 dBFS
Scart Prescale = 20hex i.e. 2.0 Vrms = 0 dBFS
Micronas
19
BSP 3505D
PRELIMINARY DATA SHEET
4.5.2. BSP Hardware Version Code
Hardware Version
001Ehex
Hardware Version
[00hex ... FFhex]
BSP 3505D – A2
01hex
H
A change in the hardware version code defines hardware optimizations that may have influence on the chip’s
behavior. The readout of this register is identical to the
hardware version code in the chip’s imprint.
4.5.3. BSP Major Revision Code
Major Revision
001Ehex
BSP 3505D
04hex
L
4.5.4. BSP Product Code
Product
001Fhex
BSP 3505D
05hex
H
4.5.5. BSP ROM Version Code
ROM Version
001Fhex
Major software revision
[00hex ... FFhex]
BSP 3505D – A2
02hex
L
A change in the ROM version code defines internal software optimizations, that may have influence on the
chip’s behavior, e.g. new features may have been included. While a software change is intended to create no
compatibility problems, customers that want to use the
new functions can identify new BSP 3505D versions according to this number.
20
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
5. Specifications
5.1. Outline Dimensions
61
60
1.27 ± 0.1
10
1.6
2
2
24.22 ±0.1
23.4
0.711
25.125 ± 0.125
9
15
26
0.22 ± 0.07
9
44
27
1.9
43
4.05
25.125 ± 0.125
4.75 ±0.15
24.22 ±0.1
0.1
SPGS7004-3/5E
Fig. 5–1:
68-Pin Plastic Leaded Chip Carrier Package
(PLCC68)
Weight approximately 4.8 g
Dimensions in mm
SPGS0016-4/3E
33
1
32
SPGS0015-1/2E
52
27
1
26
0.3
0.4 ±0.2
4 ±0.1
15.6 ±0.1
14 ±0.1
1 ±0.1
0.457
1.778 ±0.05
25 x 1.778 = 44.47 ±0.1
0.24
20.1 ±0.5
3.2 ±0.2
0.3
0.457
31 x 1.778 = 55.118 ±0.1
Fig. 5–2:
64-Pin Plastic Shrink Dual Inline Package
(PSDIP64)
Weight approximately 9.0 g
Dimensions in mm
Micronas
47 ±0.1
0.27 ±0.06
1 ±0.1
1.778 ±0.05
1.29
19.3 ±0.1
18 ±0.1
4.8 ±0.4
3.2 ±0.4
1.9
(1)
57.7 ±0.1
0.3
3.8 ±0.1
3
2.5
64
16 x 1.27 ± 0.1 = 20.32 ± 0.1
1
0.48
9
16 x 1.27 ± 0.1 = 20.32 ± 0.1
1.27 ± 0.1
1.2 x 45°
0.9
1.1 x 45 °
0.27 ±0.06
0°...15°
Fig. 5–3:
52-Pin Plastic Shrink Dual In Line Package
(PSDIP52)
Weight approximately 5.5 g
Dimensions in mm
21
BSP 3505D
PRELIMINARY DATA SHEET
23 x 0.8 = 18.4
0.8
0.17 ±0.03
64
41
14
17.2
8
1.8
10.3
9.8
5
16
80
0.8
8
1.8
15 x 0.8 = 12.0
40
65
25
1
1.28
24
2.70
23.2
3 ±0.2
20
0.1
Fig. 5–4:
80-Pin Plastic Quad Flat Package
(PQFP80)
Weight approximately 1.6 g
Dimensions in mm
SPGS0025-1/1E
10 x 0.8 = 8
0.8
0.18
33
23
22
1.75
1.3
12
44
1
11
1.75
2.0
13.2
2.15
Fig. 5–5:
44-Pin Plastic Quad Flat Package
(PQFP44)
Weight approx. 0.4 g
Dimensions in mm
22
0.8
10
0.375
13.2
3.0
10 x 0.8 = 8
34
0.1
10
SPGS0006-1/1E
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
5.2. Pin Connections and Short Descriptions
X = obligatory; connect as described in circuit diagram
AHVSS: connect to AHVSS
NC = not connected; leave vacant
LV = if not used, leave vacant
DVSS: if not used, connect to DVSS
Pin No.
Pin Name
Type
Connection
(if not used)
sed)
Short Description
–
TP
OUT
LV
Test pin
–
–
NC
LV
Not connected
13
8
–
TP
OUT
LV
Test pin
14
12
7
17
TP
IN
LV
Test pin
5
13
11
6
16
TP
OUT
LV
Test pin
6
12
10
5
15
TP
IN/OUT
LV
Test pin
7
11
9
4
14
TP
IN/OUT
LV
Test pin
8
10
8
3
13
I2C_DA
IN/OUT
X
I2C data
9
9
7
2
12
I2C_CL
IN/OUT
X
I2C clock
10
8
–
1
–
NC
LV
Not connected
11
7
6
80
11
STANDBYQ
IN
X
Standby (low-active)
12
6
5
79
10
ADR_SEL
IN
X
I2C Bus address select
13
5
4
78
9
D_CTR_OUT0
OUT
LV
Digital control output 0
14
4
3
77
8
D_CTR_OUT1
OUT
LV
Digital control output 1
15
3
–
76
–
NC
LV
Not connected
16
2
–
75
–
NC
LV
Not connected
17
–
–
–
–
NC
LV
Not connected
18
1
2
74
–
NC
LV
Not connected
19
64
1
73
7
TP
LV
Test pin
20
63
52
72
6
XTAL_OUT
OUT
X
Crystal oscillator
21
62
51
71
5
XTAL_IN
IN
X
Crystal oscillator
22
61
50
70
4
TESTEN
IN
X
Test pin
23
60
49
69
–
NC
LV
Not connected
24
59
48
68
3
TP
IN
LV
Test pin
25
58
47
67
2
TP
IN
LV
Test pin
26
57
46
66
1
AVSUP
X
Analog power supply
+5 V
–
–
–
65
–
AVSUP
X
Analog power supply
+5 V
–
–
–
64
–
NC
LV
Not connected
–
–
–
63
–
NC
LV
Not connected
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
1
16
14
9
2
–
–
3
15
4
Micronas
23
BSP 3505D
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Connection
(if not used)
Short Description
AVSS
X
Analog ground
–
AVSS
X
Analog ground
60
43
MONO_IN
LV
Mono input
–
59
–
NC
LV
Not connected
54
43
58
42
VREFTOP
X
Reference voltage
30
53
42
57
41
SC1_IN_R
IN
LV
Scart input 1 in, right
31
52
41
56
40
SC1_IN_L
IN
LV
Scart input 1 in, left
32
51
–
55
39
ASG1
AHVSS
Analog shield ground 1
33
50
40
54
38
SC2_IN_R
IN
LV
Scart input 2 in, right
34
49
39
53
37
SC2_IN_L
IN
LV
Scart input 2 in, left
35
48
–
52
–
TP
LV
Test Pin
36
47
38
51
–
NC
LV
Not connected
37
46
37
50
–
NC
LV
Not connected
38
45
–
49
–
NC
LV
Not connected
39
44
–
48
–
NC
LV
Not connected
40
43
–
47
–
NC
LV
Not connected
41
–
–
46
–
NC
LV
Not connected
42
42
36
45
36
AGNDC
X
Analog reference voltage high voltage part
43
41
35
44
35
AHVSS
X
Analog ground
–
–
–
43
–
AHVSS
X
Analog ground
–
–
–
42
–
NC
LV
Not connected
–
–
–
41
–
NC
LV
Not connected
44
40
34
40
34
CAPL_M
X
Volume capacitor MAIN
45
39
33
39
33
AHVSUP
X
Analog power supply
8.0 V
46
38
32
38
32
NC
LV
Not connected
47
37
31
37
31
SC1_OUT_L
OUT
LV
Scart output 1, left
48
36
30
36
30
SC1_OUT_R
OUT
LV
Scart output 1, right
49
35
29
35
29
VREF1
X
Reference ground 1
high voltage part
50
34
28
34
28
NC
LV
Not connected
51
33
27
33
–
NC
LV
Not connected
52
–
–
32
–
NC
LV
Not connected
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
27
56
45
62
44
–
–
–
61
28
55
44
–
–
29
24
Type
IN
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Connection
(if not used)
Short Description
NC
LV
Not connected
–
NC
LV
Not connected
29
–
NC
LV
Not connected
25
28
27
DACM_L
OUT
LV
Loudspeaker out, left
28
24
27
26
DACM_R
OUT
LV
Loudspeaker out, right
58
27
23
26
25
VREF2
X
Reference ground 2
high voltage part
59
26
22
25
24
NC
LV
Not connected
60
25
21
24
23
NC
LV
Not connected
–
–
–
23
–
NC
LV
Not connected
–
–
–
22
–
NC
LV
Not connected
61
24
20
21
22
RESETQ
X
Power-on-reset
62
23
–
20
–
NC
LV
Not connected
63
22
–
19
–
NC
LV
Not connected
64
21
19
18
21
NC
LV
Not connected
65
20
18
17
–
TP
LV
Test pin
66
19
17
16
–
DVSS
X
Digital ground
–
–
–
15
–
DVSS
X
Digital ground
–
–
–
14
20
DVSS
X
Digital ground
67
18
16
13
19
DVSUP
X
Digital power supply
+5 V
–
–
–
12
–
DVSUP
X
Digital power supply
+5 V
–
–
–
11
–
DVSUP
X
Digital power supply
+5 V
68
17
15
10
18
TP
LV
Test pin
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
53
32
–
31
–
54
31
26
30
55
30
–
56
29
57
Micronas
Type
IN
IN
OUT
25
BSP 3505D
PRELIMINARY DATA SHEET
5.3. Pin Configurations
TP
NC
TP
TP
DVSUP
TP
DVSS
TP
TP
TP
NC
TP
NC
I2C_DA
NC
I2C_CL
RESETQ
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
NC
10
60
NC
STANDBYQ
11
59
NC
ADR_SEL
12
58
VREF2
D_CTR_OUT0
13
57
DACM_R
D_CTR_OUT1
14
56
DACM_L
NC
15
55
NC
NC
16
54
NC
NC
17
53
NC
NC
18
52
NC
TP
19
51
NC
XTAL_OUT
20
50
NC
XTAL_IN
21
49
VREF1
TESTEN
22
48
SC1_OUT_R
NC
23
47
SC1_OUT_L
TP
24
46
NC
TP
25
45
AHVSUP
AVSUP
26
44
CAPL_M
BSP 3505D
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS
AHVSS
MONO_IN
AGNDC
VREFTOP
NC
SC1_IN_R
NC
SC1_IN_L
NC
ASG1
NC
SC2_IN_R
NC
SC2_IN_L
NC
TP
Fig. 5–6: 68-pin PLCC package
26
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
64
TP
TP
1
52
XTAL_OUT
2
63
XTAL_OUT
NC
2
51
XTAL_IN
NC
3
62
XTAL_IN
D_CTR_OUT1
3
50
TESTEN
D_CTR_OUT1
4
61
TESTEN
D_CTR_OUT0
4
49
NC
D_CTR_OUT0
5
60
NC
ADR_SEL
5
48
TP
ADR_SEL
6
59
TP
STANDBYQ
6
47
TP
STANDBYQ
7
58
TP
I2C_CL
7
46
AVSUP
NC
8
57
AVSUP
I2C_DA
8
45
AVSS
I2C_CL
9
56
AVSS
TP
9
44
MONO_IN
I2C_DA
10
55
MONO_IN
TP
10
43
VREFTOP
TP
11
54
VREFTOP
TP
11
42
SC1_IN_R
TP
12
53
SC1_IN_R
TP
12
41
SC1_IN_L
TP
13
52
SC1_IN_L
TP
13
40
SC2_IN_R
TP
14
51
ASG1
TP
14
39
SC2_IN_L
TP
15
50
SC2_IN_R
TP
15
38
NC
TP
16
49
SC2_IN_L
DVSUP
16
37
NC
TP
17
48
TP
DVSS
17
36
AGNDC
DVSUP
18
47
NC
TP
18
35
AHVSS
DVSS
19
46
NC
NC
19
34
CAPL_M
TP
20
45
NC
RESETQ
20
33
AHVSUP
NC
21
44
NC
NC
21
32
NC
NC
22
43
NC
NC
22
31
SC1_OUT_L
NC
23
42
AGNDC
VREF2
23
30
SC1_OUT_R
RESETQ
24
41
AHVSS
DACM_R
24
29
VREF1
NC
25
40
CAPL_M
DACM_L
25
28
NC
NC
26
39
AHVSUP
NC
26
27
NC
VREF2
27
38
NC
DACM_R
28
37
SC1_OUT_L
DACM_L
29
36
SC1_OUT_R
NC
30
35
VREF1
NC
31
34
NC
NC
32
33
NC
BSP 3505D
1
BSP 3505D
NC
NC
Fig. 5–8: 52-pin PSDIP package
Fig. 5–7: 64-pin PSDIP package
Micronas
27
BSP 3505D
PRELIMINARY DATA SHEET
SC2_IN_L
SC2_IN_R
TP
NC
NC
ASG1
NC
SC1_IN_L
SC1_IN_R
NC
VREFTOP
NC
NC
NC
MONO_IN
AGNDC
AVSS
AHVSS
AVSS
AHVSS
NC
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP
65
40
CAPL_M
AVSUP
66
39
AHVSUP
TP
67
38
NC
TP
68
37
SC1_OUT_L
NC
69
36
SC1_OUT_R
TESTEN
70
35
VREF1
XTAL_IN
71
34
NC
XTAL_OUT
72
33
NC
TP
73
32
NC
NC
74
31
NC
NC
75
30
NC
NC
76
29
NC
D_CTR_OUT1
77
28
DACM_L
D_CTR_OUT0
78
27
DACM_R
ADR_SEL
79
26
VREF2
STANDBYQ
80
25
NC
BSP 3505D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
I2C_CL
NC
I2C_DA
NC
TP
RESETQ
TP
NC
NC
TP
TP
NC
TP
TP
DVSS
TP
TP
DVSS
DVSUP
DVSUP
DVSS
DVSUP
Fig. 5–9: 80-pin PQFP package
28
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
NC
VREF1
DACM_L
SC1_OUT_R
DACM_R
SC1_OUT_L
VREF2
NC
NC
AHVSUP
NC
33 32 31 30 29 28 27 26 25 24 23
CAPL_M
34
22
RESETQ
AHVSS
35
21
NC
AGNDC
36
20
DVSS
SC2_IN_L
37
19
DVSUP
SC2_IN_R
38
18
TP
ASG1
39
17
TP
SC1_IN_L
40
16
TP
SC1_IN_R
41
15
TP
VREFTOP
42
14
TP
MONO_IN
43
13
I2C_DA
AVSS
44
12
I2C_CL
BSP 3505D
1
2
3
4
5
6
7
8
9
10 11
STANDBYQ
AVSUP
ADR_SEL
TP
D_CTR_OUT0
TP
D_CTR_OUT1
TESTEN
TP
XTAL_IN
XTAL_OUT
Fig. 5–10: 44-pin PQFP package
Micronas
29
BSP 3505D
PRELIMINARY DATA SHEET
5.4. Pin Circuits (pin numbers refer to PLCC68 package)
40 k
≈ 3.75 V
N
GND
Fig. 5–11: Input/Output Pins 8 and 9
(I2C_DA, I2C_CL)
Fig. 5–17: Input Pins 30, 31, 33, and 34
(SC1–2_IN_L/R)
125 k
≈ 3.75 V
Fig. 5–12: Input Pins 11, 12, and 61
(STANDBYQ, ADR_SEL, RESETQ)
Fig. 5–18: Pin 42 (AGNDC)
DVSUP
P
N
0...2 V
GND
Fig. 5–19: Capacitor Pin 44 (CAPL_M)
Fig. 5–13: Output Pins 13, and 14
(D_CTR_OUT0/1)
P
40 pF
3–30 pF
80 k
500 k
N
300
≈ 3.75 V
3–30 pF
Fig. 5–14: Input/Output Pins 20 and 21
(XTALIN/OUT)
Fig. 5–20: Output Pins 47, 48
(SC1_OUT_L/R)
VREFTOP
≈2.6V
AHVSUP
Fig. 5–15: Pin 29 (VREFTOP)
0...1.2 mA
3.3 k
24 k
≈ 3.75 V
Fig. 5–16: Input Pin 28 (MONO_IN)
30
Fig. 5–21: Output Pins 56, 57
(DACM_L/R)
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
5.5. Electrical Characteristics
5.5.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
701)
°C
TS
Storage Temperature
–
–40
125
°C
VSUP1
First Supply Voltage
AHVSUP
–0.3
9.0
V
VSUP2
Second Supply Voltage
DVSUP
–0.3
6.0
V
VSUP3
Third Supply Voltage
AVSUP
–0.3
6.0
V
dVSUP23
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
–0.5
0.5
V
PTOT
Chip Power Dissipation
PLCC68 without Heat Spreader
PSDIP64 without Heat Spreader
PSDIP52 without Heat Spreader
PQFP44 without Heat Spreader
AHVSUP,
DVSUP,
AVSUP
1200
1300
1200
9601)
mW
–0.3
VSUP2+0.3
V
VIdig
Input Voltage, all Digital Inputs
IIdig
Input Current, all Digital Pins
–
–20
+20
mA2)
VIana
Input Voltage, all Analog Inputs
SCn_IN_s,3)
MONO_IN
–0.3
VSUP1+0.3
V
IIana
Input Current, all Analog Inputs
SCn_IN_s,3)
MONO_IN
–5
+5
mA2)
IOana
Output Current, all SCART Outputs
SC1_OUT_s
4), 5)
4), 5)
IOana
Output Current, all Analog Outputs
except SCART Outputs
DACM_s3)
4)
4)
ICana
Output Current, other pins
connected to capacitors
CAPL_M
AGNDC
4)
4)
1)
2)
3)
4)
5)
For PQFP44 package, max. ambient operating temperature is 65 °C.
positive value means current flowing into the circuit
“n” means “1” or “2”, “s” means “L” or “R”
The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
Micronas
31
BSP 3505D
PRELIMINARY DATA SHEET
5.5.2. Recommended Operating Conditions
at TA = 0 to 70 °C (65 °C for PQFP44)
Symbol
Parameter
Pin Name
Min.
VSUP1
First Supply Voltage
AHVSUP
7.6
VSUP2
Second Supply Voltage
DVSUP
VSUP3
Third Supply Voltage
VREIL
RESET Input High-Low and LowHigh Transition Voltage
tREIL
RESET Low Time after DVSUP
Stable and Oscillator Startup
VDIGIL
Digital Input Low Voltage
VDIGIH
Digital Input High Voltage
STANDBYQ,
ADR SEL
ADR_SEL,
TESTEN
tSTBYQ1
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
Typ.
Max.
Unit
8.0
8.4
V
4.75
5.0
5.25
V
AVSUP
4.75
5.0
5.25
V
RESETQ
0.45
0.8
VSUP2
µs
5
0.2
VSUP2
0.8
VSUP2
1
µs
I2C-Bus Recommendations
VI2CIL
I2C-BUS Input Low Voltage
I2C_CL,
I2C_DA
C DA
VI2CIH
I2C-BUS Input High Voltage
fI2C
I2C-BUS Frequency
I2C_CL
tI2C1
I2C START Condition Setup Time
tI2C2
I2C STOP Condition Setup Time
I2C_CL,
I2C_DA
C DA
tI2C3
I2C-Clock Low Pulse Time
tI2C4
I2C-Clock High Pulse Time
tI2C5
I2C-Data Setup Time Before
Rising Edge of Clock
tI2C6
I2C-Data Hold Time
after Falling Edge of Clock
0.3
0.6
I2C_CL
I2C_CL,
I2C_DA
VSUP2
VSUP2
1.0
MHz
120
ns
120
ns
500
ns
500
ns
55
ns
55
ns
Crystal Recommendations
32
fP
Parallel Resonance Frequency
at 12 pF Load Capacitance
18.432
MHz
fTOL
Accuracy of Adjustment
–100
+100
ppm
DTEM
Frequency Variation versus
Temperature
–50
+50
ppm
RR
Series Resistance
8
25
Ω
C0
Shunt (Parallel) Capacitance
6.2
7.0
pF
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
XTAL_IN,
XTAL_OUT
PSDIP
PLCC
Typ.
Max.
Unit
Load Capacitance Recommendations
External Load Capacitance1)
CL
1.5
3.3
pF
pF
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF)
VXCA
External Clock Amplitude
XTAL_IN
0.7
Vpp
AGNDC
–20%
3.3
µF
–20%
100
nF
–20%
330
Analog Input and Output Recommendations
CAGNDC
AGNDC-Filter-Capacitor
Ceramic Capacitor in Parallel
SCn_IN_s2)
CinSC
DC-Decoupling Capacitor
in front of SCART Inputs
+20%
nF
VinSC
SCART Input Level
2.0
VRMS
VinMONO
Input Level, Mono Input
MONO_IN
2.0
VRMS
RLSC
SCART Load Resistance
SC1_OUT_s2)
CLSC
SCART Load Capacitance
CVMA
Main Volume Capacitor
CAPL_M
CFMA
Main Filter Capacitor
DACM_s2)
–10%
1
VREFTOP
–20%
10
µF
–20%
100
nF
10
kΩ
6.0
nF
µF
10
+10%
nF
Recommendations for Reference Voltage Pin
CVREFTOP
VREFTOP-Filter-Capacitor
Ceramic Capacitor in Parallel
1)
External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock
frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due
to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.
2)
“n” means “1” or “2”, “s” means “L” or “R”
Micronas
33
BSP 3505D
PRELIMINARY DATA SHEET
5.5.3. Characteristics
at TA = 0 to 70 °C (65 °C for PQFP44), fCLOCK = 18.432 MHz,
VSUP1 = 7.6 to 8.4 V, VSUP2 = 4.75 to 5.25 V for min./max. values
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature
MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
Symbol
Parameter
Pin Name
fCLOCK
Clock Input Frequency
XTAL_IN
DCLOCK
Clock High to Low Ratio
tJITTER
Clock Jitter (Verification not
provided in Production test)
VxtalDC
DC-Voltage Oscillator
tStartup
Oscillator Startup Time at
VDD Slew-rate of 1 V/1 µs
XTAL_IN,
XTAL_OUT
ISUP1A
First Supply Current (active)
AHVSUP
Min.
Typ.
Max.
18.432
45
Test Conditions
MHz
55
%
50
ps
2.5
Analog Volume for Main and Aux at 0dB
Analog Volume for Main and Aux at –30dB
Unit
V
0.4
2
ms
9.6
6.3
17.1
11.2
24.6
16.1
mA
mA
ISUP2A
Second Supply Current (active)
DVSUP
86
95
102
mA
ISUP3A
Third Supply Current (active)
AVSUP
15
25
35
mA
ISUP1S
First Supply Current
(standby mode) at Tj = 27 °C
AHVSUP
3.5
5.6
7.7
mA
STANDBYQ = low
VI2COL
I2C-Data Output Low Voltage
I2C_DA
0.4
V
II2COL = 3 mA
II2COH
I2C-Data Output High Current
1.0
µA
VI2COH = 5 V
tI2COL1
I2C-Data Output Hold Time
after Falling Edge of Clock
tI2COL2
I2C-Data Output Setup Time
before Rising Edge of Clock
I2C_DA,
I2C_CL
15
ns
100
ns
fI2C = 1 MHz
Analog Ground
VAGNDC0
AGNDC Open Circuit Voltage
RoutAGN
AGNDC Output Resistance
AGNDC
3.63
3.73
3.83
V
Rload ≥ 10 MΩ
70
125
180
kΩ
3 V ≤ VAGNDC ≤ 4 V
Analog Input Resistance
RinSC
SCART Input Resistance
from TA = 0 to 70 °C
SCn_IN_s1)
25
40
58
kΩ
fsignal = 1 kHz, I = 0.05 mA
RinMONO
MONO Input Resistance
from TA = 0 to 70 °C
MONO_IN
15
24
35
kΩ
fsignal = 1 kHz, I = 0.1 mA
SCn_IN_s,1)
MONO_IN
2.00
2.25
VRMS
fsignal = 1 kHz
Audio Analog-to-Digital-Converter
VAICL
1)
34
Effective Analog Input Clipping
Level for Analog-to-DigitalConversion
“n” means “1”, or “2”;
“s” means “L” or “R”
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
200
200
330
460
500
Ω
Ω
–70
+70
mV
SCn_IN_s1)
MONO_IN
→
SC1_OUT_s1)
–1.0
+0.5
dB
fsignal = 1 kHz
–0.5
+0.5
dB
with resp. to 1 kHz
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
2.1
2.1
3.3
4.6
5.0
kΩ
kΩ
1.8
2.04
61
2.28
V
mV
1.23
1.37
1.51
VRMS
SCART Outputs
RoutSC
SCART Output Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
SC1_OUT_s1)
dVOUTSC
Deviation of DC-Level at SCART
Output from AGNDC Voltage
ASCtoSC
Gain from Analog Input
to SCART Output
frSCtoSC
Frequency Response from Analog
Input to SCART Output
bandwidth: 0 to 20000 Hz
VoutSC
Effective Signal Level at SCARTOutput during full-scale digital input signal from DSP
SC1_OUT_s1)
Main Output Resistance
at Tj = 27 °C
from TA = 0 to 70 °C
DACM_s1)
fsignal = 1 kHz, I = 0.1 mA
Main Outputs
RoutMA
VoutDCMA
VoutMA
DC-Level at Main-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB
Effective Signal Level at Main-Output during full-scale digital input
signal from DSP for Analog Volume at 0 dB
fsignal = 1 kHz, I = 0.1 mA
fsignal = 1 kHz
Analog Performance
SNR
Signal-to-Noise Ratio
from Analog Input to
SCART Output
THD
“n” means “1” or “2”;
Micronas
93
96
dB
Input Level = –20 dB,
fsig = 1 kHz,
equally weighted
20 Hz ... 20 kHz
%
Input Level = –3 dBr,
fsig = 1 kHz,
equally weighted
20 Hz ... 20 kHz
Total Harmonic Distortion
from Analog Input to
SCART Output
1)
MONO_IN,
SCn_IN_s1)
→
SC1_OUT_s1)
MONO_IN,
SCn_IN_s1)
→
SC1_OUT_s1)
0.01
0.03
“s” means “L” or “R”
35
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
XTALK
Crosstalk attenuation
– PLCC68
– PSDIP64
Input Level = –3 dB,
fsig = 1 kHz, unused analog inputs connected to
ground by Z < 1 kΩ
between left and right channel within
SCART Input/Output pair (L→R, R→L)
equally weighted
20 Hz ... 20 kHz
SCn_IN1) → SC1_OUT
PLCC68
PSDIP64
Min.
Typ.
Max.
80
80
Unit
Test Conditions
dB
dB
PSRR: rejection of noise on AHVSUP at 1 kHz
DCVREFTOP
1)
36
AGNDC
AGNDC
80
dB
From Analog Input to
SCART Output
MONO_IN,
SCn_IN_s1)
SC1_OUT_s1)
70
dB
DC voltage at VREFTOP
VREFTOP
“n” means “1” or “2”;
2.4
2.6
2.7
V
“s” means “L” or “R”
Micronas
BSP 3505D
PRELIMINARY DATA SHEET
6. Application Circuit
C s. section 5.5.2.
10
µF
100
nF
+8.0 V
+
3.3
µF
18.432
MHz
100
nF
+
10 µF
28 (55) MONO_IN
CAPL_M (40) 44
XTAL_OUT (63) 20
XTAL_IN (62) 21
VREFTOP (54) 29
AGNDC (42) 42
+
1 µF
DACM_L (29) 56
330 nF
1 nF
1 µF
MAIN
DACM_R (28) 57
31 (52) SC1_IN_L
330 nF
30 (53) SC1_IN_R
330 nF
32 (51) ASG1
AHVSS
SC1_OUT_L (37) 47
34 (49) SC2_IN_L
BSP 3505D
330 nF
33 (50) SC2_IN_R
330 nF
SC1_OUT_R (36) 48
100Ω 22 µF
+
100Ω 22 µF
+
5V
D_CTR_OUT0 (5) 13
11 (7) STANDBYQ
5V
DVSS
D_CTR_OUT1 (4) 14
12 (6) ADR_SEL
DVSS
8 (10) I2C_DA
TESTEN (61) 22
9 (9) I2C_CL
58 (27) VREF2
49 (35) VREF1
43 (41) AHVSS
45 (39) AHVSUP
27 (56) AVSS
26 (57) AVSUP
66 (19) DVSS
67 (18) DVSUP
61 (24) RESETQ
AVSS
100
nF
+
10 µF
5V
100
nF
100
nF
5V
AVSS
ResetQ
(from CCU,
see
section.3.3.)
8.0 V
Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.
Application Note:
All ground pins should be connected to one low-resistive
ground plane.
All supply pins should be connected separately with
short and low-resistive lines to the power supply.
Decoupling capacitors from DVSUP to DVSS, AVSUP to
AVSS, and AHVSUP to AHVSS are recommended as
close as possible to these pins. Decoupling of DVSUP
and DVSS is most important. We recommend using
Micronas
more than one capacitor. By choosing different values,
the frequency range of active decoupling can be extended. In our application boards we use: 220 pF,
470 pF, 1.5 nF, and 10 µF. The capacitor with lowest value should be placed nearest to the DVSUP and DVSS
pins.
The ASG1 pin should be connected as closely as possible to the MSP to ground. If it is lead with the SC1 inputlines as shielding line, it should NOT be conneted to
ground at the SCART connector.
37
BSP 3505D
38
PRELIMINARY DATA SHEET
Micronas
PRELIMINARY DATA SHEET
Micronas
BSP 3505D
39
BSP 3505D
PRELIMINARY DATA SHEET
7. Appendix A: BSP 3505D Version History
8. Data Sheet History
A2
1. Preliminary Data Sheet: “BSP 3505D Baseband
Sound Processor”, Oct. 21, 1998, 6251-481-1PD.
First release of the preliminary data sheet.
First hardware release BSP 3505D
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-481-1PD
40
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples
delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties
which may result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on
a retrieval system, or transmitted without the express written consent
of Micronas GmbH.
Micronas