ETC SSD1815Z

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1815
Advanced Information
LCD Segment / Common Driver
with Controller
CMOS
SSD1815 is a single-chip CMOS LCD driver with controller for liquid crystal dotmatrix graphic display system. It consists of 197 high voltage driving output pins for
driving 132 Segments, 64 Commons and 1 icon driving-Common.
TAB
SSD1815 displays data directly from its internal 132 X 65 bits Graphic Display
Data RAM (GDDRAM). Data/Commands are sent from general MCU through a software selectable 6800-/8080-series compatible Parallel Interface or Serial Peripheral
Interface.
SSD1815 embeds a DC-DC Converter, an On-Chip Bias Divider and an On-Chip
Oscillator which reduce the number of external components. With the special design
on minimizing power consumption and die/package layout, SSD1815 is suitable for
any portable battery-driven applications requiring a long operation period and a compact size.
Gold Bump Die
ORDERING INFORMATION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Supply Operation, 1.8 V - 3.5V
Minimum -12.0V LCD Driving Output Voltage
Low Current Sleep Mode
On-Chip Voltage Generator / External Power Supply
2X / 3X / 4X On-Chip DC-DC Converter
On-Chip Oscillator
Programmable Multiplex ratio (2Mux ~ 65Mux)
On-Chip Bias Divider
Programmable bias ratio
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial
Peripheral Interface
On-Chip 132 X 65 Graphic Display Data RAM
Re-mapping of Row and Column Drivers
Vertical Scrolling
Display Offset Control
64 Level Internal Contrast Control
External Contrast Control
Programmable LCD Driving Voltage Temperature Coefficients
Available in Gold Bump Die and TAB (Tape Automated Bonding) Package
SSD1815Z
SSD1815TR
SSD1815T1R
SSD1815T2R
SSD1815T3R
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copyright © 2000 SolomonGroup
REV 1.5
03/2000
Gold Bump Die
TAB
TAB
TAB
TAB
Block Diagram
ICONS
ROW0 ~
ROW63
SEG0~SEG131
Level
Selector
HV Buffer Cell Level Shifter
VL6
VL5
VL4
VL3
VL2
VDD
Display Data Latch
MSTAT
M
DOF
M/S
CL
CLS
VF
Display
Timing
Generator
LCD Driving
Voltage Generator
2X / 3X / 4X
DC/DC Converter,
Voltage Regulator,
Bias Divider,
Contrast Control,
Temperature
Compensation
Oscillator
GDDRAM
132 X 65 Bits
VEE
VSS1
C3N
C1P
C1N
C2N
C2P
VFS
HPM
IRS
Command Decoder
VSS
VDD
Command Interface
RES P/S CS1 CS2 D/C
E
R/W C68/80
(RD) (WR)
Parallel / Serial Interface
D7
D6 D5 D4 D3 D2 D1 D 0
(SDA) (SCK)
Figure 1 - Block Diagram of SSD1815
SSD1815
2
REV 1.5
03/2000
SOLOMON
ICONS
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
ROW9
ROW10
ROW11
ROW12
ROW13
ROW14
ROW15
ROW16
ROW17
ROW18
ROW19
137
Center: 389.725, -201.6
Radius: 27.125u
Center: 3701.075, -304.5
Radius: 50.925u
(0,0)
Y
Center: -3880.625, 205.625
Size: 99.75u x 99.75u
:
:
268
1
ROW20
ROW21
:
:
ROW30
ROW31
VDD
IRS
VSS
/HPM
VDD
P/S
C68/80
VSS
CLS
M/S
VDD
NC
NC
VDD
VDD
VF
VF
VL6
VL6
VL6
VL5
VL5
VL4
VL4
VL4
VL3
VL3
VL3
VL2
VL2
VDD
VDD
VFS
VFS
VSS
VSS
C2P
C2P
C2P
C2N
C2N
C2N
C2N
C1N
C1N
C1N
C1P
C1P
C1P
C3N
C3N
C3N
C3N
VEE
VEE
VEE
VEE
VSS1
VSS1
VSS1
VSS1
VSS
VSS
VSS
VDD
VDD
VDD
VDD
D7 (SDA)
D6 (SCK)
D5
D4
D3
D2
D1
D0
VDD
E(/RD)
R/W(/WR)
VSS
D/C
/RES
VDD
CS2
/CS1
VSS
/DOF
CL
M
MSTAT
NC
ICONS
ROW63
ROW62
ROW61
:
:
ROW54
ROW53
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
ROW44
ROW45
ROW46
ROW47
ROW48
ROW49
ROW50
ROW51
ROW52
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
:
:
Center: 3819.2, -419.2
Size: 99.75u x 99.75u
Center: 3816.05, -305.2
Size: 100.1u x 100.1u
115
x
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
Gold Bump Alignment Mark
This alignment mark contains gold nump for IC
bumping process alignment and IC identifications.
No conductive tracks should be laid underneath
this mark to avoid short circuit.
Note:
1. This diagram showing Die Face Up view.
2. Coordinates and Size of all alignment marks are
in unit um and w.r.t. center of the chip.
PIN #1
Die Size:
Die Thickness:
Bump Pitch:
Bump Height:
10.977mm X 1.912mm
533 +/-25um
76.2 um [Min]
Nominal 18um
Tolerance <4um within die
<8um within lot
Figure 2 - SSD1815Z Die Pin Assignment
SOLOMON
REV 1.5
03/2000
SSD1815
3
Table 1 - SSD1815Z Die Pad Coordinates
PAD #
NAME
1
ROW53
2
ROW54
3
ROW55
4
ROW56
5
ROW57
6
ROW58
7
ROW59
8
ROW60
9
ROW61
10
ROW62
11
ROW63
12
ICONS
13
NC
14
MSTAT
15
M
16
CL
17
/DOF
18
VSS
19
/CS1
20
CS2
21
VDD
22
/RES
23
D/C
24
VSS
25
R /W
26
E /RD
27
VDD
28
D0
29
D1
30
D2
31
D3
32
D4
33
D5
34
D6
35
D7
36
VDD
37
VDD
38
VDD
39
VDD
40
VSS
41
VSS
42
VSS
43
VSS1
44
VSS1
45
VSS1
46
VSS1
47
VEE
48
VEE
49
VEE
50
VEE
51
C3N
52
C3N
53
C3N
54
C3N
55
C1P
56
C1P
57
C1P
58
C1N
59
C1N
60
C1N
10.977mm
D ie Size:
Bump Size:
Pad #
X [um]
1 - 12
43.5
13 - 103
61.7
104 - 115
43.5
SSD1815
4
REV 1.5
03/2000
X
-4958.45
-4882.15
-4805.85
-4729.55
-4653.25
-4576.95
-4500.65
-4424.35
-4348.05
-4271.75
-4195.45
-4119.15
-4000.50
-3911.60
-3822.70
-3733.80
-3644.90
-3556.00
-3467.10
-3378.20
-3289.30
-3200.40
-3111.50
-3022.60
-2933.70
-2844.80
-2755.90
-2667.00
-2578.10
-2489.20
-2400.30
-2311.40
-2222.50
-2133.60
-2044.70
-1955.80
-1866.90
-1778.00
-1689.10
-1600.20
-1511.30
-1422.40
-1333.50
-1244.60
-1155.70
-1066.80
-977.90
-889.00
-800.10
-711.20
-622.30
-533.40
-444.50
-355.60
-266.70
-177.80
-88.90
0.00
88.90
177.80
X
Y
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
1.912mm
PAD #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
NAME
C2N
C2N
C2N
C2N
C2P
C2P
C2P
VSS
VSS
VFS
VFS
VDD
VDD
VL2
VL2
VL3
VL3
VL3
VL4
VL4
VL4
VL5
VL5
VL6
VL6
VL6
VF
VF
VDD
VDD
NC
NC
VDD
M /S
CLS
VSS
C68/80
P/S
VDD
/HPM
VSS
IRS
VDD
ROW31
ROW30
ROW29
ROW28
ROW27
ROW26
ROW25
ROW24
ROW23
ROW22
ROW21
ROW20
X
266.70
355.60
444.50
533.40
622.30
711.20
800.10
889.00
977.90
1066.80
1155.70
1244.60
1333.50
1422.40
1511.30
1600.20
1689.10
1778.00
1866.90
1955.80
2044.70
2133.60
2222.50
2311.40
2400.30
2489.20
2578.10
2667.00
2755.90
2844.80
2933.70
3022.60
3111.50
3200.40
3289.30
3378.20
3467.10
3556.00
3644.90
3733.80
3822.70
3911.60
4000.50
4119.15
4195.45
4271.75
4348.05
4424.35
4500.65
4576.95
4653.25
4729.55
4805.85
4882.15
4958.45
Y
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-771.93
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
-751.98
PAD #
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Y [um]
101.6
61.7
101.6
Pad #
116 - 136
X [um]
101.6
Y [um]
43.5
Pad #
137 - 268
X [um]
43.5
Y [um]
101.6
NAME
ROW19
ROW18
ROW17
ROW16
ROW15
ROW14
ROW13
ROW12
ROW11
ROW10
ROW9
ROW8
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
ICONS
X
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
5285.18
Y
-768.78
-692.48
-616.18
-539.88
-463.58
-387.28
-310.98
-234.68
-158.38
-82.08
-5.78
70.53
146.83
223.13
299.43
375.73
452.03
528.33
604.63
680.93
757.23
Y
PIN268
PIN137
x
(0,0)
PIN 1
PIN115
Die Size: 10.977mm X 1.912mm
Bump Height:
- nominal: 18um
- tolerance:<4um (within die)
<6um (within wafer)
<8um (within lot)
Unit in um unless otherwise specified.
Pad #
269 - 289
X [um]
101.6
Y [um]
43.5
Gold bump size tolerance: +/-1.5um.
SOLOMON
PAD #
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
SOLOMON
NAME
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
X
4997.65
4921.35
4845.05
4768.75
4692.45
4616.15
4539.85
4463.55
4387.25
4310.95
4234.65
4158.35
4082.05
4005.75
3929.45
3853.15
3776.85
3700.55
3624.25
3547.95
3471.65
3395.35
3319.05
3242.75
3166.45
3090.15
3013.85
2937.55
2861.25
2784.95
2708.65
2632.35
2556.05
2479.75
2403.45
2327.15
2250.85
2174.55
2098.25
2021.95
1945.65
1869.35
1793.05
1716.75
1640.45
1564.15
1487.85
1411.55
1335.25
1258.95
1182.65
1106.35
1030.05
953.75
877.45
801.15
724.85
648.55
572.25
495.95
419.65
343.35
267.05
190.75
114.45
38.15
Y
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
PAD #
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
NAME
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
X
-38.15
-114.45
-190.75
-267.05
-343.35
-419.65
-495.95
-572.25
-648.55
-724.85
-801.15
-877.45
-953.75
-1030.05
-1106.35
-1182.65
-1258.95
-1335.25
-1411.55
-1487.85
-1564.15
-1640.45
-1716.75
-1793.05
-1869.35
-1945.65
-2021.95
-2098.25
-2174.55
-2250.85
-2327.15
-2403.45
-2479.75
-2556.05
-2632.35
-2708.65
-2784.95
-2861.25
-2937.55
-3013.85
-3090.15
-3166.45
-3242.75
-3319.05
-3395.35
-3471.65
-3547.95
-3624.25
-3700.55
-3776.85
-3853.15
-3929.45
-4005.75
-4082.05
-4158.35
-4234.65
-4310.95
-4387.25
-4463.55
-4539.85
-4616.15
-4692.45
-4768.75
-4845.05
-4921.35
-4997.65
Y
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
751.98
PAD #
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
NAME
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
ROW44
ROW45
ROW46
ROW47
ROW48
ROW49
ROW50
ROW51
ROW52
X
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
-5285.18
REV 1.5
03/2000
Y
757.23
680.93
604.63
528.33
452.03
375.73
299.43
223.13
146.83
70.53
-5.78
-82.08
-158.38
-234.68
-310.98
-387.28
-463.58
-539.88
-616.18
-692.48
-768.78
SSD1815
5
PIN DESCRIPTIONS
MSTAT
This pin is the static indicator driving output. It is only active in
master operation. The frame signal output pin, M, should be used
as the back plane signal for the static indicator.
The duration of overlapping could be programmable. See
Extended Command Table for details.
This pin becomes high impedance if the chip is operating in
slave mode.
M
This pin is the frame signal input/output. In master mode, the pin
supplies frame signal to slave devices while in slave mode, the pin
receives frame signal from the master device.
CL
This pin is the display clock input/output. In master mode, the pin
supplies display clock signal to slave devices while in slave mode,
the pin receives display clock signal from the master device.
DOF
This pin is diaplay blanking control between master and slave
devices. In master mode, this pin supplies on/off signal to slave
devices. In slave mode, this pin receives on/off signal from the
master device.
CS1, CS2
These pins are the chip select inputs. The chip is enabled for
MCP communication only when both CS1 is pulled low and CS2 is
pulled high.
D7-D0
These pins are the 8-bit bi-directional data bus to be connected
to the microprocessor in parallel interface mode. D7 is the MSB
while D0 is the LSB.
When serial mode is selected, D7 is the serial data input (SDA)
and D6 is the serial clock input (SCK).
VDD
Power supply pin.
VSS
Ground.
VSS1
Reference voltage input for internal DC-DC converter. The voltage of generated, VEE, equals to the multiple factor times the protential different between this pin, VSS1, and VDD. The multiple
factor, 2X, 3X or 4X, is selected by different external capacitor
connections. All voltage levels are referenced to VDD.
Note: the potential at this input pin must lower than or equal to
VSS.
VEE
This is the most negative voltage supply pin of the chip. It can
be supplied externally or generated by the internal DC-DC converter.
When using internal DC-DC converter as generator, voltage at
this pin is for internal reference only. It CANNOT be used for driving external circuitries.
RES
This pin is reset signal input. Initialization of the chip is started
once this pin is pulled low. Minimum pulse width for completing the
reset is 1us.
C3N, C1P, C1N, C2N and C2P
When internal DC-DC voltage converter is used, external
capacitor(s) is/are connected between these pins. Different connection will result in different DC-DC converter multiple factor, 2X,
3X or 4X. Details please refer to voltage converter section in the
block diagram description.
D/C
This pin is Data/Command control pin. When the pin is pulled
high, the data at D7-D0 is treated as display data. When the pin is
pulled low, the data at D7-D0 will be tranferred to the command register.
VFS
This is an input pin to provide an external voltage reference for
the internal voltage regulator. The function of this pin is only
enabled for the External Input chip models which are required
special ordering. For normal chip model, please leave this pin NC.
R/W(WR)
This pin is microprocessor interface input. When interfacing to an
6800-series microprocessor, this pin will be used as R/W singal
input. Read mode will be carried out when this pin is pulled high
and write mode when low.
When interfacing to an 8080-microprocessor, this pin will be the
WR input. Data write operation is initiated when this pin is pulled
low when the chip is selected.
VL2, VL3, VL4 and VL5 (Voltages referenced to VDD)
LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship:
VDD > VL2 > VL3 > VL4 > VL5 > VL6
E(RD)
This pin is microprocessor interface input. When interfacing to an
6800-series microprocessor, this pin will be used as the enable signal, E. Read/write operation is initiated when this pin is pulled high
when the chip is selected.
When interfacing to an 8080-microprocessor, this pin receives
the RD signal. Data read operation is initiated when this pin is
pulled low when the chip is selected.
SSD1815
6
REV 1.5
03/2000
1:7 bias
1:9 bias (default)
VL2
1/7*VL6
1/9*VL6
VL3
2/7*VL6
2/9*VL6
VL4
5/7*VL6
7/9*VL6
VL5
6/7*VL6
8/9*VL6
VL6
This pin is the most negative LCD driving voltage. It can be supplied externally or generated by the internal regulator.
SOLOMON
VF
This pin is the input of the built-in voltage regulator. When external resistor network is selected to generate the LCD driving level,
VL6, two external resistors, R1 and R2, are connected between VDD
and VF, and VF and VL6, respectively (see application circuit).
NC
These are the No Connection pins. Nothing should be connected to these pins, nor they are connected together. These pins
should be left open individually.
M/S
This pin is the master/slave mode selection input. When this pin
is pulled high, master mode is selected, which CL, M, MSTAT and
DOF signals will be output for slave devices. When this pin is
pulled low, slave mode is selected, which CL, M, DOF are required
to be input from master device and MSTAT is high impedance.
CLS
This pin is the internal clock enable pin. When this pin is pulled
high, internal clock is enabled. The internal clock will be disabled
when it is pulled low, an external clock source should be input to
CL pin.
C68/80
This pin is microprocessor interface selection input. When the
pin is pulled high, 6800 series interface is selected and when the
pin is pulled low, 8080 series MCU interface is selected.
P/S
This pin is serial/parallel interface selection input. When this pin
is pulled high, parallel mode is selected. When it is pulled low,
serial interface will be selected. Read back operation is only available in parallel mode.
HPM
This pin is the control input of High Power Current Mode. The
function of this pin is only enabled for High Power model which
required special ordering.
For normal models, High Power Mode is disabled and the LCD
driving characteristics are the same no matter this pin is pulled
High or Low.
Note: This pin must be pulled to either High or Low. Leaving this
pin floating is prohibited.
IRS
This is the input pin to enable the internal resistors network for
the voltage regulator. When this pin is pulled high the internal resistors will be enalbed, and when it is low, the external resistors, R1
and R2, should be connected to VDD and VF, and VF and VL6,
respectively (see application circuits).
ROW0 - ROW63
These pins provide the row driving signal COM0 - COM63 to the
LCD panel. See Table.1 about the COM signal mapping in different
multiplex ratio N.
SEG0 - SEG131
These pins provide the LCD column driving signals. Their output
voltage level is VDD during sleep mode and standby mode.
ICONS
There are two ICONS pins (pin12 and 136) on the chip. Both
pins output exactly the same signal. The reason for duplicating the
pin is to enhance the flexibility of the LCD layout.
SOLOMON
REV 1.5
03/2000
SSD1815
7
Table 2 - ROW pins assignment for COM signals in different Programmable Multiplex Ratio
[After power-on-reset, SSD1815 is set to 64 Multiplex]
Die Pad Name
64 Mux Com
Signal Output
54 Mux Com
Signal Output
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW8
ROW9
ROW10
ROW11
ROW12
ROW13
ROW14
ROW15
ROW16
ROW17
ROW18
ROW19
ROW20
ROW21
ROW22
ROW23
ROW24
ROW25
ROW26
ROW27
ROW28
ROW29
ROW30
ROW31
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
ROW44
ROW45
ROW46
ROW47
ROW48
ROW49
ROW50
ROW51
ROW52
ROW53
ROW54
ROW55
ROW56
ROW57
ROW58
ROW59
ROW60
ROW61
ROW62
ROW63
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
53 Mux Com
Signal Output
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
52 Mux Com
Signal Output
49 Mux Com
Signal Output
48 Mux Com
Signal Output
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
34 Mux Com
Signal Output
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
33 Mux Com
Signal Output
32 Mux Com
Signal Output
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
NON-SELECT*
Remark:
* The ROW will output a Non-Select COM signal.
SSD1815
8
REV 1.5
03/2000
SOLOMON
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
Command Decoder and Command Interface
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/C pin. If D/C is high, data is written to Graphic Display
Data RAM (GDDRAM). If D/C is low, the input at D7-D0 is interpreted
as a Command and it will be decoded and be written to the corresponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D7-D0),
R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input High indicates
a read operation from the Graphic Display Data RAM (GDDRAM) or
the status register. R/W(WR) input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the
status of D/C input. The E(RD) input serves as data latch signal
(clock) when high provided that CS1 and CS2 are low and high
respectively. Refer to Figure 9 for Parallel Interface Timing Diagram
of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that
of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first
actual display data read. This is shown in Figure 3 below.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D7-D0),
E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input serves as data
read latch signal (clock) when low provided that CS1 and CS2 are
low and high respectively. Whether it is display data or status register read is controlled by D/C. R/W(WR) input serves as data write
latch signal(clock) when high provided that CS1 and CS2 are low
and high respectively. Whether it is display data or command register write is controlled by D/C. Refer to Figure 10 for Parallel Interface
Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required
before the first actual display data read.
MPU Serial interface
The serial interface consists of serial clock SCK (D6), serial data
SDA (D7), D/C, CS1 and CS2. SDA is shifted into a 8-bit shift register
on every rising edge of SCL in the order of D7, D6,... D0. D/C is sampled on every eighth clock to determine whether the data byte in the
shift register is written to the Display Data RAM or command register
at the same clock.
R/W(WR)
E(RD)
data bus
n
N
write column address
dummy read
data read1
n+1
n+2
data read 2
data read 3
Figure 3 - Display data read with the insertion of dummy read
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry
(Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable
enable
enable
Oscillation Circuit
Buffer
(CL)
Internal pwell resistor
OSC1
OSC2
Figure 4 - Oscillator Circuitry
SOLOMON
REV 1.5
03/2000
SSD1815
9
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern
to be displayed. The size of the RAM is 132 X 65= 8580 bits. Figure
5 is a description of the GDDRAM address map. For mechanical
flexibility, re-mapping on both Segment and Common outputs can be
selected by software. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of
the RAM data to be mapped to the display. Figure 5 shows the case
in which the display start line register is set to 38h.
Column address 83H
(00H)
Column address 00H
(83H)
LSB [D0]
COM8 (COM55)
Page 0
MSB [D7]
LSB
Page 1
MSB
LSB
Page 2
MSB
LSB
Page 3
MSB
LSB
Page 4
MSB
LSB
Page 5
MSB
LSB
Page 6
MSB
LSB
COM63 (COM0)
COM0 (COM63)
38H
Page 7
MSB
COM7 (COM56)
Page 8 (LSB)
ICONS
SEG0
SEG131
Note: The configuration in parentheses represent the remapped values of Rows and Columns
Figure 5. Graphic Display Data RAM (GDDRAM) Address Map (with display start line at 38H)
For 132 X 64 Graphic Display Mode with separated Icon Line
SSD1815
10
REV 1.5
03/2000
SOLOMON
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for display driving output. It takes a single supply input and generate necessary voltage levels. This block consists of:
1. 2X, 3X and 4X DC-DC voltage converter
The built-in DC-DC voltage converter is use to generate large negative LCD driving voltage with reference to VDD from the voltage
input (VSS1). For SSD1815, it is possible to produce 2X, 3X or 4X
boosting from the protential different between VSS1 - VDD.
Detail configurations of the DC-DC converter for different boosting
multiples are given in Figure 6 at the right.
2. Voltage Regulator (Voltages referenced to VDD)
The feedback gain control for LCD driving contrast curves can be
selected by IRS pin to either internal (IRS pin = H) or external (IRS
pin = L).
For internal resistor network is enabled, there are eight setting can
be set by software.
If external control is selected, external resistors are required to be
connected between VDD and VF (R1), and between VF and VL6
(R2).
3. Contrast Control (Voltages referenced to VDD)
Software control of the 64 contrast voltage levels at each voltage
regulator feedback gain. The equation of calculating the LCD driving voltage is given as:
Contrast
VL 6 − VDD = Gain ∗ (1 +
) ∗Vref
β
VBE + R ∗ (VDD − VSS )
Vref = (
)
1+ R
SSD1815
VSS1
VEE
C3N
C1P
+
C1N
C2P C2N
+
C1
C1
2X Boosting Configuration
SSD1815
VSS1
VEE
C3N
C1P
+
C1N
+
C1
C2P C2N
+
C1
C1
3X Boosting Configuration
SSD1815
VSS1
VEE
C3N
C1P
C1N
C2P C2N
where
Int. Reg. Resistor
Ratio Setting
0
1
2
3
-4.29
4
5
6
7
Gain
-3.29 -3.76
β
92.59 91.86 91.12 90.40 89.67 89.18 88.29 87.49
Ext.
Resistor
-4.82 -5.39 -5.76 -6.40 -6.95 -(1+R2/R1)
96.68
and
TC
0
2
4
7
(-0.01%/° C) (-0.10%/ °C) (-0.18%/° C) (-0.25%/°C)
VBE
0.025
0.523
0.520
0.517
R
0.72
0.423
0.272
0.121
4. Bias Divider
Divide the regulator output to give the LCD driving voltages (VL2 VL5). A low power consumption circuit design in this bias divider
saves most of the display current comparing to traditional design.
+
C1
+
C1
+
C1
+
C1
4X Boosting Configuration
Remarks:
1. C1 = 0.47 - 1.0uF
2. Boosting input from VSS1.
3. VSS1 should be lower potential than or equal to VSS
4. All voltages are referenced to VDD
Figure 6 - Configurations for DC-DC Converter
5. Bias Ratio Selection circuitry
Software control of 1/7 and 1/9 bias ratio to match the characteristic of LCD panel. In addition, 1/4, 1/5, 1/6 and 1/8 bias ratios are
also software selectable using the extended command for any
mux application.
6. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to satisfy
various liquid crystal temperature gradings by software control.
Default temperature coefficient (TC) setting is TC0.
SOLOMON
REV 1.5
03/2000
SSD1815
11
VL6 vs Contrast Settings
-3
0
10
20
30
40
50
60
-5
20
21
22
23
24
25
26
27
VL6(V)
-7
-9
-11
-13
-15
contrast level at VDD = 2.775V
Figure 7 - Contrast Curves at Different Interneal Feedback Resistor Ratio Settings
Reset Circuit
This block includes Power On Reset circuitry and the Reset pin,
RES. Both of these having the same reset function. Once RES
receives a negative reset pulse, all internal circuitry will start to initialize. Minimum pulse width for completing the reset sequence is 1us.
The status of the chip after reset is given by:
1. Display is turned OFF
2. 132X64 Display Display Mode with seperated Icon Line
3. Normal segment and display data column address mapping
(SEG0 mapped to address 00h)
4. Read-modify-write mode is OFF
5. Power control register is set to 000b
6. Shift register data clear in serial interface
7. Bias ratio is set to 1/9
8. Static indicator is turned OFF
9. Display start line is set to display RAM column address 0
10. Column address counter is set to 0
11. Page address is set to 0
12. Normal scan direction of the COM outputs
13. Contrast control register is set to 20h
14. Test mode is turned OFF
voltage can be separated into two sets and used with different cycles.
Synchronization is important since it selects the required LCD voltage
level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD
waveform.
HV Buffer Cell (Level Shifter)
HV Buffer Cell work as a level shifter which translates the low voltage
output signal to the required driving voltage. The output is shifted out
with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal.
Display Data Latch
A series of registers carrying the display signal information. For
SSD1815, there are 197 latches (132 + 65) for holding the data,
which will be fed to the HV Buffer Cell and Level Selector to output
the required voltage level.
Level Selector
Level Selector is a control of the display synchronization. Display
SSD1815
12
REV 1.5
03/2000
SOLOMON
SEG0
SEG1
SEG2
SEG3
SEG4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Figure 8a. LCD Display Example “0”
TIME SLOT
1 2 3 4 5 6 7 8 9
*
. . . N+1
1 2 3 4 5 6 7 8 9
*
. . . N+1
1 2 3 4 5 6 7 8 9
*
. . . N+1
1 2 3 4 5 6 7 8 9
*
. . . N+1
VDD
VL2
VL3
COM0
VL4
VL5
VL6
VDD
VL2
VL3
COM1
VL4
VL5
VL6
VDD
VL2
VL3
SEG0
VL4
VL5
VL6
VDD
VL2
VL3
SEG1
VL4
VL5
VL6
M
* Note : N is the number of multiplex ratio not included Icon, N is equal to 64 on POR.
Figure 8b - LCD Driving Waveform
SOLOMON
REV 1.5
03/2000
SSD1815
13
COMMAND TABLE
Bit Pattern
Write Command
(D/C=0, R/W(WR)=0, E(RD)=1)
Comment
0000X 3X 2X 1X 0
Set Lower Column Address
Set the lower nibble of the colume address register using
X 3X 2X 1X 0 as data bits. The initial display line register is reset to
0000b during POR.
0001X 3X 2X 1X 0
Set Higher Column Address
Set the higher nibble of the colume address register using
X 3X 2X 1X 0 as data bits. The initial display line register is reset to
0000b during POR.
00100X 2X 1X 0
Set Internal Regulator Resistor Ratio
Internal regulator gain increases as X2X1X 0 increased from 000b
to 111b. At POR, X 2X1X0 = 100b.
00101X 2X 1X 0
Set Power Control Register
X 0=0: turns off the output op-amp buffer (POR)
X 0=1: turns on the output op-amp buffer
X 1=0: turns off the internal regulator (POR)
X 1=1: turns on the internal regulator
X 2=0: turns off the internal voltage booster (POR)
X 2=1: turns on the internal voltage booster
01X 5X 4X 3X 2X 1X0
Set Display Start Line
Set display RAM display start line register from 0-63 using
X 5X 4X 3X 2X 1X0.
Display start line register is reset to 000000 during POR.
10000001
* * X5X4X 3X 2X 1X 0
Set Contrast Control Register
Set Contrast level from 64 contrast steps. Contrast increases (VL6
decreases) as X 5X 4X 3X 2X 1X 0 is increased.
X 5X 4X 3X 2X 1X0 = 100000b (POR)
1010000X 0
Set Segment Re-map
X 0=0: column address 00h is mapped to SEG0 (POR)
X 0=1: column address 83h is mapped to SEG0
Refer to Figure 5 for example.
1010001X 0
Set LCD Bias
X 0=0: 1/9 bias (POR)
X 0=1: 1/7 bias
For setting bias ratio to 1/4, 1/5, 1/6 or 1/8, see Extended Command Table.
1010010X 0
Set Entire Display On/Off
X 0=0: normal display (POR)
X 0=1: entire display on
1010011X 0
Set Normal/Reverse Display
X 0=0: normal display (POR)
X 0=1: reverse display
1010111X 0
Set Display On/Off
X 0=0: turns off LCD panel (POR)
X 0=1: turns on LCD panel
1011X 3X 2X 1X 0
Set Page Address
Set GDDRAM Page Address (0-8) using X 3X 2X 1X0
1100X 3 * * *
Set COM Output Scan Direction
X 3=0: normal mode (POR)
X 3=1: remapped mode, COM0 to COM[N-1] becomes COM[N-1]
to COM0 when Multiplex ratio is equal to N. See Figure 5
as an example for N equal to 64.
11100000
Set Read-Modify-Write Mode
Read-modify-write mode will be entered in which the column
address will not be incremented during display data read. At POR,
Read-modify-write mode is turned OFF.
11100010
Software Reset
Initialize the internal status register.
11101110
Set End of Read-Modify-Write Mode
Exit Read-modify-write mode. Column address before entering the
mode will be restored. At POR, Read-modify-write mode is OFF.
1010110X 0
Set Indicator On/Off
X 0 = 0: indicator off (POR, no need of second command byte)
X 0 = 1: indicator on (second command byte required)
* * * * * * X1X 0
Indicator Display Mode,
This second byte command is required
ONLY when “Set Indicator On” command is sent.
X 1X 0 = 00: indicator off
X 1X 0 = 01: indicator on and blinking at ~1 second interval
X 1X 0 = 10: indicator on and blinking at ~1/2 second interval
X 1X 0 = 11: indicator on constantly
11100011
NOP
Command for No Operation
11110000
Test Mode Reset
Reserved for IC testing. Do NOT use.
1111 * * * *
Set Test Mode
Reserved for IC testing. Do NOT use.
********
Set Power Save Mode
Standby or sleep mode will be entered with compound commands
SSD1815
14
REV 1.5
03/2000
SOLOMON
Bit Pattern
Read Command
(D/C=0, R/W(WR)=1, E(RD)=0)
D7D6D5D4D3D2D1D0
Status Register Read
(Data Read Back from the
driver)
Comment
D7=0: indicates an internal operation is completed.
D7=1: indicates an internal operation is in progress.
D6=0: indicates reverse segment mapping with column address
D6=1: indicates normal segment mapping with column address
D5=0: indicates the display is ON
D5=1: indicates the display is OFF
D4=0: initialization is not in progress
D4=1: initialization is in progress after RES or software reset
D3D2D1D0 = 1010, these 4-bit is fixed to 1010 which could be used
to identify as Solomon Systech Device.
EXTENDED COMMAND TABLE
Bit Pattern
Command
Comment
10101000
00X5X4X3X2X1X0
X5X4X 3X 2X 1X 0: Set Multiplex Ratio
To select multiplex ratio N from 2 to 65 [Included Icon Line].
N = X 5X 4X 3X 2X 1X 0 + 2, eg. N = 111111b + 2 = 65 (POR)
10101001
X 7X 6X 5X 4X 3X 2X 1X 0
X1X0: Set Bias Ratio
X1X 0 = 00: 1/8, 1/6
X1X 0 = 01: 1/6, 1/5
X1X 0 = 10: 1/9, 1/7 (POR)
X1X 0 = 11: Prohibited
X4X3X 2: Set TC Value
X4X 3X 2 = 000: -0.01%/C (TC0, POR)
X4X 3X 2 = 010: -0.10%/C (TC2)
X4X 3X 2 = 100: -0.18%/C (TC4)
X4X 3X 2 = 111: -0.25%/C (TC7)
X4X 3X 2 = 001, 011, 101, 110: Reserved
X7X6X 5: Modify Osc. Freq.
Increase the value of X7X6X5 will increase the oscillator frequency
and vice versa. This command is not recommended to be used.
X7X 6X 5 = 011(POR)
1010101X0
X0: Set 1/4 Bias Ratio
X0 = 0: use Normal Setting (POR)
X0 = 1: fixed at 1/4 Bias
11010010
0X6X500010
X6X5: Set Total Frame Phases
The On/Off of the Static Icon is given by 3 phases/1 phase overlapping of the M and MSTAT signals. This command set how many
phases of dividing the M/MSTAT signals for each frame.
The more the phases, the less the overlapping and thus the lower
the effective driving voltage.
X6X 5 = 00: 3 phases
X6X 5 = 01: 5 phases
X6X 5 = 10: 7 phases (POR)
X6X 5 = 11: 16 phases
11010011
00X5X4X3X2X1X0
X5X4X 3X 2X 1X 0: Set Display Offset
After POR, X5X4X3X2X1X0 = 0
(for mux ratio has been After setting mux ratio less than 64, data will be displayed at Center
set less than 64 only)
of matrix. See Table 1.
To move display towards Row 0 by L, X5X4X3X2X1X 0 = L
To move display away from Row 0 by L, X5X4X3X2X1X 0 = 64-L
Note: max. value of L = (64 - display mux)/2
Note: Patterns other than that given in Command Table and Extended Command Table are prohibited to enter to the chip
as a command. Otherwise, unexpected result will occurs.
SOLOMON
REV 1.5
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SSD1815
15
Data Read / Write
To read data from the GDDRAM, input High to R/W(WR) pin and D/C pin for 6800-series parallel mode, Low to E(RD) pin and High to
D/C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be
increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a
dummy read is required before the first data read. See Figure 3 in Functional Description.
To write data to the GDDRAM, input Low to R/W(WR) pin and High to D/C pin for 6800-series parallel mode. For serial interface, it will
always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write.
Address Increment Table (Automatic)
D/C
R/W(WR) Comment
Address Increment
0
0
Write Command
No
0
1
Read Status
No
1
0
Write Data
Yes
1
1
Read Data
Yes
Remarks
*1
GDDRAM*2
Address Increment is done automatically after data read write. The column address pointer of
Remarks: 1. If read data is issued in read-modify-write mode, address will NOT be increased.
2. Column Address will NOT wrap round to zero when overflow.
is affected.
Commands Required for R/W(WR) Actions on RAM
R/W(WR) Actions on RAMs
Commands Required
Read/Write Data from/to GDDRAM.
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
Save/Restore GDDRAM Column Address.
(1011X3X2X 1X 0)*
(0001X3X2X 1X 0)*
(0000X3X2X 1X 0)
(X7X6X5X4X3X 2X 1X 0)
Save GDDRAM Column Address by read-modify- (11100000)
write mode
Restore GDDRAM Column Address by end of read- (11101110)
modify-write mode
Note: 1. No need to resend the command again if it is set previously.
2. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM
content whether the target RAM content is being displayed or not.
SSD1815
16
REV 1.5
03/2000
SOLOMON
Command Description
used.
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column
address of the display data RAM. The column address will be
incremented by each data access after it is pre-set by the MCU.
Set Entire Display On/Off
This command forces the entire display, including the icon
row, to be “ON”regardless of the contents of the display data
RAM. This command has priority over normal/reverse display. This command will be used with “Set Display Display
ON/OFF” command to form a compound command for entering power save mode. See “Set Power Save Mode”.
Set Higher Column Address
This command specifies the higher nibble of the 8-bit column
address of the display data RAM. The column address will be
incremented by each data access after it is pre-set by the MCU.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator
resistor network (IRS pin pulled high). Please refer to Block Diagram Description section for detail calculation of the LCD driving voltage.
Set Power Control Register
This command turns on/off the various power circuits associated with the chip.
Set Normal/Reverse Display
This command sets the display to be either normal/
reverse. In normal display, a RAM data of 1 indicates an “ON”
pixel while in reverse display, a RAM data of 0 indicates an
“ON” pixel. In icon mode, the icon line is not reversed by this
command.
Set Display On/Off
This command alternatively turns the display on and off.
When display off is issued with entire display on, power save
mode will be entered. See “Set Power Save Mode” for
details.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is
mapped to COM0. With value equals to 1, D1 of Page0 is
mapped to COM0. The display start line values of 0 to 63 are
assigned to Page 0 to 7.
Set Page Address
This command positions the page address from 0 to 8 possible positions in GDDRAM. Refer to Figure 5 for mapping.
Set Contrast Control Register
This commands adjusts the contrast of the LCD panel by
changing VL6 of the LCD drive voltage provided by the On-Chip
power circuits. VL6 is set with 64 steps (6-bit) contrast control
register. It is a compound commands:
Set Read-Modify-Write Mode
This command puts the chip in read-modify-write mode in
which:
1. the column address is saved before entering the mode
2. the column address is incremented by display data write
but not by display data read
Set Contrast Control Register
Contrast Level Data
No
Changes
Complete?
Yes
Set Segment Re-map
This commands changes the mapping between the display
data column address and segment driver. It allows flexibility in
layout during LCD module assembly. Refer to Figure 5 for example.
Set LCD Bias
This command selects a suitable bias ratio (1/7 or 1/9)
required for driving the particular LCD panel in use. The POR
default for SSD1815 is set to 1/9 bias. For setting 1/4, 1/5, 1/6
and 1/8 bias, an extended compound command should be
SOLOMON
Set COM Output Scan Direction
This command sets the scan direction of the COM output
allowing layout flexibility in LCD module assembly.
Software Reset
This command causes some of the internal status registers
of the chip to be initialized:
1. Static indicator is turned OFF
2. Display start line register is set to 0
3. Column address counter is set to 0
4. Page address is set to 0
5. Normal scan direction of the COM outputs
6. Contrast control register is set to 0
7. Test mode is turned OFF
Set End of Read-Modify-Write Mode
This command relieves the chip from read-modify-write
mode. The column address that is saved before entering
read-modify-write mode will be restored.
Set Indicator On/Off
This command turns on and off the static drive indicators. It
also controls whether standby mode or sleep mode will be
REV 1.5
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SSD1815
17
entered after the power save compound command. See “Set
Power Save Mode”.
When the “Set Indicator On” command is sent, the “Indicator
Display Mode”must be followed in the next command. The “Set
Indicator Off” command is a single byte command and no following command is required.
NOP
A command causing No Operation.
Set Test Mode
This command force the driver chip into its test mode for
internal testing of the chip. Under normal operation, user should
NOT use this command.
Set Power Save Mode
To enter Standby or Sleep Mode, it should be done by using
a compound command composed of “Set Display ON/OFF”and
“Set Entire Display ON/OFF”commands. When “Set Entire Display ON” is issued when display is OFF, either Standby Mode
or Sleep Mode will be entered.
The status of the Static Indicator will determine which power
save mode is entered. If static indicator is off, the Sleep Mode
will be entered:
1. Internal oscillator and LCD power supply circuits are
stopped
2. Segment and Common drivers output VDD level
3. The display data and operation mode before sleep are
held
4. Internal display RAM can still be accessed
If the static indicator is on, the chip enters Standby Mode
which is similar to sleep mode except:
1. Internal oscillator is on
2. Static drive system is on
Note also that if the software reset command is issued during
Standby Mode, Sleep Mode will be entered. Both power save
modes can be exited by the issue of a new software command
or by pulling Low at hardware pin RES.
Status register Read
This command is issued by pulling D/C Low during a data read
(refer to Figure 9 and 10 for parallel interface waveforms). It allows the MCU to monitor the internal status of the chip. No status
read is provided for serial mode.
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to
trigger the enhanced features, on top of general ones, designed
for the chip.
Set Multiplex Ratio
This command switches default 64 multiplex mode to any
multiplex mode from 2 to 64. The chip pads ROW0-ROW63 will
be switched to corresponding COM signal output, see Table 1
for examples of different multiplex settings.
SSD1815
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REV 1.5
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Set Bias Ratio
Except the 1/4 bias, all the available bias ratios (1/5, 1/6, 1/7,
1/8 and 1/9) could be set using this command plus the Set LCD
Bias. When changing the display multiplex ratio, the bias ratio
also need to be adjusted to make display contrast consistent.
Set Temperature Coefficient (TC) Value
4 different temperature coefficient settings is selected by this
command in order to match various liquid crystal temperature
grades.
Modify Oscillator Frequency
The oscillator frequncy can be fine tuned by applying this command. Since the oscillator frequency will be affected by some
other factors, this command is not recommended for general
usage. Please contact our application engineer for more detail
explaination on this command.
Set 1/4 Bias Ratio
This command sets the bias ratio directly to 1/4 bias. This ratio
is especially for use in under 12mux display.
In order to restore to other bias ratio, this command must be
executed, with LSB=0, before the “Set Multiplex ratio” or “Set
LCD Bias”command is sent.
Set Total Frame Phases
The total number of phases for one display frame is set by this
command.
The Static Icon is generated by the overlapping of the M and
MSTAT signals. To turn on the Static Icon, 3 phases overlapping
will be applied to these signals, while 1 phase overlapping will be
given to the Off status.
The more the total number of phasesin one frame, the less the
overlapping time and thus the lower the effective driving voltage
at the Static Icon on the LCD panel.
Set Display Offset
This command should be sent ONLY when the multiplex ratio
is set less than 64.
When the mulitplex ratio less than 64 is set, the display will be
mapped in the middle (y-direction) of the LCD, see Table 1. Use
this command could move the display vertically within the 64 commons.
To make the Reduced-Mux Com 0 (Com 0 after reducing the
multiplex ratio) towards the Row 0 direction for L lines, the 6-bit
data in second command should be given by L.
To move in the other direction by L lines, the 6-bit data should
be given by 64-L.
Please note that the display is confined within the un-reduced
64 mux. That is maximum value of L is given by the half of 64 minus the reduced-multiplex ratio. For an odd display mux after reduction, moving away from Row 0 direction will has 1 more step.
SOLOMON
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
Supply Voltage
VEE
Vin
I
Input Voltage
Value
Unit
-0.3 to +4.0
V
0 to -12.0
V
VSS-0.3 to VDD+0.3
V
25
mA
Current Drain Per Pin Excluding VDD and
VSS
TA
Operating Temperature
-30 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage
higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the
range VSS < or = (Vin or Vout) < or = VDD. Reliability
of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left
open. This device may be light sensitive. Caution
should be taken to avoid exposure of this device to
any light source during normal operation. This
device is not radiation protected.
DC CHARACTERISTICS (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85°C.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
2.4
1.8
2.7
-
3.5
3.5
V
V
VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled, Write accessing, Tcyc =3.3MHz, Osc.
Freq.=17kHz, Display On.
-
300
600
µA
Display Mode Supply Current Drain (VDD Pins)
VDD = 2.7V, VEE = -8.1V, Voltage Generator Disabled, R/W(WR) Halt, Osc. Freq. = 17kHz, Display
On, VL6 - VDD = -8.1V.
-
60
100
µA
IDP2
Display Mode Supply Current Drain (VDD Pins)
VDD = 2.7V, VEE = -8.1V, Voltage Generator On, 4x
DC-DC Converter Enabled, R/W(WR) Halt, Osc.
Freq. = 17kHz, Display On, VL6 - VDD = -8.1V.
-
150
200
µA
ISB
Standby Mode Supply Current Drain (VDD Pins)
VDD=2.7V, LCD Driving Waveform Off, Osc. Freq. =
17kHz, R/W(WR) halt.
-
3.5
10
µA
Sleep Mode Supply Current Drain (VDD Pins)
VDD = 2.7V, LCD Driving Waveform Off, Oscillator
Off, R/W(WR) halt.
-
0.2
5
µA
LCD Driving Voltage Generator Output (VEE Pin)
Display On, Voltage Generator Enabled, DC/DC
Converter Enabled, Osc. Freq.=17kHz, Regulator
Enabled, Divider Enabled.
-12.0
-
-1.8
V
VDD
Logic Circuit Supply Voltage Range
Recommend Operating Voltage
Possible Operating Voltage
IAC
Access Mode Supply Current Drain (VDD Pins)
IDP1
ISLEEP
VEE
VLCD
LCD Driving Voltage Input (VEE Pin)
Voltage Generator Disabled.
-12.0
-
-1.8
V
VOH1
Logic High Output Voltage
Iout=100µA
0.9*VDD
-
VDD
V
VOL1
Logic Low Output Voltage
Iout=100µA
0
-
0.1*VDD
V
LCD Driving Voltage Source (VL6 Pin)
Regulator Enabled (VL6 voltage depends on Int/Ext
Contrast Control)
VEE-0.5
-
VDD
V
Regulator Disable
VL6
VL6
LCD Driving Voltage Source (VL6 Pin)
-
Floating
-
V
VIH1
Logic High Input voltage
0.8*VDD
-
VDD
V
VIL1
Logic Low Input voltage
0
-
0.2*VDD
V
SOLOMON
REV 1.5
03/2000
SSD1815
19
VL2
VL3
VL4
VL5
VL6
LCD Display Voltage Output
(VL2, VL3, VL4, VL5, VL6 Pins)
Voltage reference to VDD, Bias Divider Enabled, 1:7
bias ratio
-
1/7*VL6
2/7*VL6
5/7*VL6
6/7*VL6
VL6
-
V
V
V
V
V
VL2
VL3
VL4
VL5
VL6
LCD Display Voltage Output
(VL2, VL3, VL4, VL5, VL6 Pins)
Voltage reference to VDD, Bias Divider Enabled, 1:9
bias ratio
-
1/9*VL6
2/9*VL6
7/9*VL6
8/9*VL6
VL6
-
V
V
V
V
V
VL2
VL3
VL4
VL5
VL6
LCD Display Voltage Input
(VL2, VL3,VL4, VL5, VL6 Pins)
Voltage reference to VDD, External Voltage Generator, Bias Divider Disabled
VL3
VL4
VL5
VL6
-12V
-
VDD
VL2
VL3
VL4
VL5
V
V
V
V
V
IOH
Logic High Output Current Source
Vout = VDD-0.4V
50
-
-
µA
IOL
Logic Low Output Current Drain
Vout = 0.4V
-
-
-50
µA
IOZ
IIL/IIH
CIN
Logic Output Tri-state Current Drain Source
-1
-
1
µA
Logic Input Current
-1
-
1
µA
-
5
7.5
pF
-
±3
-
%
0
-0.075
-0.15
-0.20
-0.01
-0.10
-0.18
-0.25
-0.075
-0.15
-0.20
-
%/C
%/C
%/C
%/C
Logic Pins Input Capacitance
∆VL6
Variation of VL6 Output (VDD is fixed)
PTC0
PTC2
PTC4
PTC7
Temperature Coefficient Compensation
Flat Temperature Coefficient (POR)
Temperature Coefficient 2*
Temperature Coefficient 4*
Temperature Coefficient 7*
Regulator Enabled, Internal Contrast
Enabled, Set Contrast Control Register = 0
Control
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
* The formula for the temperature coefficient is:
TC(%)=
Vref at 50°C - Vref at 0°C
X
50°C - 0°C
1
X100%
Vref at 25°C
AC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85°C.)
Symbol
Parameter
Test Condition
FOSC
Oscillation Frequency of Display Timing Generator
Internal Oscillator Enabled, VDD = 2.7V
FFRM
Frame Frequency
Display ON, Set 132 X 64 Graphic Display
Mode
SSD1815
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REV 1.5
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Min
Typ
Max
Unit
15
17
19
kHz
-
FOSC
4*65
-
Hz
SOLOMON
TABLE 3. 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85°C)
Symbol
tcycle
Parameter
Clock Cycle Time
Min
Typ
Max
Unit
300
-
-
ns
tAS
Address Setup Time
0
-
-
ns
tAH
Address Hold Time
0
-
-
ns
tDSW
Write Data Setup Time
40
-
-
ns
tDHW
Write Data Hold Time
15
-
-
ns
tDHR
Read Data Hold Time
20
-
-
ns
tOH
Output Disable Time
-
-
70
ns
-
-
140
ns
PWCSL
tACC
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
Access Time
120
60
-
-
ns
ns
PWCSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
ns
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
R/W
D/C
tAH
tAS
E
tcycle
PWCSL
PWCSH
CS1
(CS2=1)
tR
tF
tDSW
D0-D7
(Write data to driver)
Valid Data
tACC
D0-D7
(Read data from driver)
tDHW
tDHR
Valid Data
tOH
Figure 9 - 6800-series MPU Parallel Interface Characteristics
SOLOMON
REV 1.5
03/2000
SSD1815
21
TABLE 4. 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85°C)
Symbol
tcycle
Parameter
Min
Clock Cycle Time
Typ
Max
Unit
300
-
-
ns
0
-
-
ns
Address Hold Time
0
-
-
ns
Write Data Setup Time
40
-
-
ns
tDHW
Write Data Hold Time
15
-
-
ns
tDHR
Read Data Hold Time
20
-
-
ns
tOH
Output Disable Time
-
-
70
ns
tACC
Access Time
-
-
140
ns
tAS
Address Setup Time
tAH
tDSW
PWCSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
-
-
ns
ns
PWCSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
ns
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
D/C
tAH
tAS
CS1
(CS2=1)
tcycle
PWCSL
PWCSH
RD
WR
tR
tF
tDSW
D0-D7
(Write data to driver)
Valid Data
tACC
D0-D7
(Read data from driver)
tDHW
tDHR
Valid Data
tOH
Figure 10 - 8080-series MPU Parallel Interface Characteristics
SSD1815
22
REV 1.5
03/2000
SOLOMON
TABLE 5. Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85°C)
Symbol
tcycle
Parameter
Clock Cycle Time
Min
Typ
Max
Unit
250
-
-
ns
tAS
Address Setup Time
150
-
-
ns
tAH
Address Hold Time
150
-
-
ns
tCSS
Chip Select Setup Time (for D7 input)
120
-
-
ns
tCSH
Chip Select Hold Time (for D0 input)
60
-
-
ns
tDSW
Write Data Setup Time
100
-
-
ns
tDHW
Write Data Hold Time
100
-
-
ns
tCLKL
Clock Low Time
100
-
-
ns
tCLKH
Clock High Time
100
-
-
ns
tR
Rise Time
-
-
15
ns
tF
Fall Time
-
-
15
ns
D/C
tAS
CS1
(CS2=1)
tAH
tCSS
tCSH
tcycle
tCLKH
tCLKL
SCK
tR
tF
tDHW
tDSW
SDA
Valid Data
D/C
CS1
(CS2=1)
SCK
D7
D6 D5
D4 D3
D2 D1
D0
SDA
Figure 11 - Serial Interface Characteristics
SOLOMON
REV 1.5
03/2000
SSD1815
23
Figure 12 - Application Circuit: External VEE with internal regulator and divider mode [Command: 2B] in 64 Mux.
ICONS
COM0
:
COM10
COM11
:
COM30
COM31
DISPLAY PANEL SIZE
132 x 64 + 2 X ICON LINES
COM32
COM33
:
:
:
COM63
ICONS
SEG0 --------------------------------------------- SEG131
SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0
SSD1815 IC
64 MUX
( DIE FACE UP)
COM20
:
COM26
COM27
:
COM31
ICONS
COM63
:
COM57
COM56
:
COM53
COM32
COM33
COM34
:
:
:
:
:
:
:
:
COM51
COM52
VDD VL2 VL3 VL4 VL5 VL6
VF
[Command: C8]
SCAN Direction
Remapped COM
VEE
Remapped COM
SCAN Direction
[Command: C8]
IRS
VSS[GND]
D/C
/CS1
RES
R/W
R2
D0 - D7
ICONS
COM0
:
COM4
COM5
COM6
COM7
:
:
:
COM18
COM19
Remapped COM
SCAN Direction
[Command: C8]
Remapped COM
SCAN Direction
[Command: C8]
Segment Remapped
[Command: A1]
0.1~0.47uF x 5
R1
VDD=2.75V
Optional for External
Resistors Gain Control
[IRS pulled to GND]
External Vneg=-9.5V
Logic pin connections not specified above:
Pins connected to VDD: CS2, RD, M/S, CLS, C68/80, P/S, HPM
Pins connected to VSS: VSS1
Pins floating: DOF, CL, VFS
SSD1815
24
REV 1.5
03/2000
SOLOMON
Figure 13 - Application Circuit: ALL internal power mode [Command: 2F] in 64 Mux.
ICONS
COM0
:
COM10
COM11
:
COM30
COM31
DISPLAY PANEL SIZE
132 x 64 + 2 X ICON LINES
COM32
COM33
:
:
:
COM63
ICONS
SEG0 --------------------------------------------- SEG131
SEG131 --------------------------------------------------------------------------------------------------------------------------------SEG0
SSD1815 IC
64 MUX
( DIE FACE UP)
COM20
:
COM25
COM26
:
COM31
ICONS
COM63
:
COM59
COM58
:
COM53
COM32
COM33
COM34
:
:
:
:
:
:
:
:
COM51
COM52
VSS VEE C3N C1P C1N C2N C2P
VDD VL2 VL3 VL4 VL5 VL6
ICONS
COM0
:
COM4
COM5
COM6
COM7
:
:
:
COM18
COM19
VF
[Command: C8]
SCAN Direction
Remapped COM
Remapped COM
SCAN Direction
[Command: C8]
D0 - D7 and Control Bus
R2
0.47~1uF x 4
0.1~0.47uF x 5
VSS [GND]
Remapped COM
SCAN Direction
[Command: C8]
Remapped COM
SCAN Direction
[Command: C8]
Segment Remapped
[Command: A1]
R1
VDD=2.75V
Optional for External
Resistors Gain Control
[IRS pulled to GND]
Logic pin connections not specified above:
Pins connected to VDD: CS2, RD, M/S, CLS, C68/80, P/S, HPM
Pins connected to VSS: VSS1
Pins floating: DOF, CL, VFS
SOLOMON
REV 1.5
03/2000
SSD1815
25
APPENDIX A0-1. SDD1815T TAB Drawing
SSD1815
26
REV 1.5
03/2000
SOLOMON
APPENDIX A0-2. SDD1815T TAB Drawing
Copper View Pin Assignment
SOLOMON
REV 1.5
03/2000
SSD1815
27
APPENDIX A1-1. SDD1815T1 TAB Drawing
SSD1815
28
REV 1.5
03/2000
SOLOMON
APPENDIX A1-2. SDD1815T1 TAB Drawing
Copper View Pin Assignment
SOLOMON
REV 1.5
03/2000
SSD1815
29
APPENDIX A2-1. SDD1815T2 TAB Drawing
SSD1815
30
REV 1.5
03/2000
SOLOMON
APPENDIX A2-2. SDD1815T2 TAB Drawing
Internal Connections:
VDD: CS2, M/S
VSS: VSS1
Copper View Pin Assignment
SOLOMON
REV 1.5
03/2000
SSD1815
31
APPENDIX A3-1. SDD1815T3 TAB Drawing
SSD1815
32
REV 1.5
03/2000
SOLOMON
APPENDIX A3-2. SDD1815T3 TAB Drawing
Internal Connections:
VDD: CS2, M/S, P/S, HPM, IRS
VSS: C68/80, VSS1
Floating: VFS
Copper View Pin Assignment
SOLOMON
REV 1.5
03/2000
SSD1815
33
APPENDIX B0. R330 TAB Wheel Mechnical Drawing
A
3.5mm
330mm
CORE DIA. 25.8mm
KEYWAY = 4.2mm
37mm±0.5
A
SECTION AA
MATERIAL: HIGH IMPACT POLYSTYRENE (HIPS)
SURFACE RESISTIVITY: 1 X 105 OHM MIN
1 X 109 OHM MAX
TAPE LENGTH = 20m
SSD1815
34
REV 1.5
03/2000
SOLOMON
Solomon reserves the right to make changes without further notice to any products herein. Solomon makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Solomon assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical”parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon does not convey any license under its patent rights nor the rights of others.Solomon products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of unintended
or unauthorized application, Buyer shall indemnify and hold Solomon and its offices, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Solomon was negligent regarding the design or manufacture of the part.
SSD1815