TI SN74ALVCH16269DL

SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16269 is used in applications in
which two separate ports must be multiplexed
onto, or demultiplexed from, a single port. The
device is particularly suitable as an interface
between synchronous DRAMs and high-speed
microprocessors.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
OEB2
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
Data is stored in the internal B-port registers on
26
31
the low-to-high transition of the clock (CLK) input
27
30
when the appropriate clock-enable (CLKENA)
28
29
inputs are low. Proper control of these inputs
allows two sequential 12-bit words to be
NC – No internal connection
presented as a 24-bit word on the B port. For data
transfer in the B-to-A direction, a single storage
register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by
the active-low output enables (OEA, OEB1, OEB2).
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active
state of the outputs cannot be determined before the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16269 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
Function Tables
OUTPUT ENABLE
OUTPUTS
INPUTS
CLK
OEA
OEB
A
1B, 2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A-TO-B STORAGE
(OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
1B
2B
L
H
↑
L
L
L
H
↑
H
H
2B0†
2B0†
L
L
↑
L
L
L
L
L
↑
H
H
H
H
L
↑
L
H
L
↑
H
1B0†
1B0†
H
L
H
H
X
X
1B0† 2B0†
† Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE (OEA = L)
INPUTS
OUTPUT
A
CLK
SEL
1B
2B
X
H
X
X
X
L
X
X
↑
H
L
X
L
↑
H
H
X
H
↑
L
X
L
L
↑
L
X
H
H
A0†
A0†
† Output level before the indicated steady-state
input conditions were established
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
logic diagram (positive logic)
CLK
OEB1
29
C1
2
1D
C1
OEB2
CLKENA1
CLKENA2
56
1D
30
55
C1
SEL
OEA
28
1D
1
1D
1 of 12 Channels
C1
G1
A1
8
C1
1
1D
23
1B1
1
CE
C1
1D
6
2B1
CE
C1
1D
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3
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
Low-level input voltage
MIN
MAX
1.65
3.6
2
0.35 × VCC
0.7
0
0
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
V
0.8
Output voltage
VCC = 2.7 V
VCC = 3 V
V
1.7
Input voltage
High level output current
High-level
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
Control inputs
Cio
A or B ports
1.7
2.7 V
2.2
3V
2.4
3V
2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
VI = 0.58 V
VI = 1.07 V
1.65 V
25
1.65 V
–25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
–45
VI = 0.8 V
VI = 2 V
3V
75
3V
–75
IO = 0
Other inputs at VCC or GND
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
750
µA
3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
UNIT
V
3.6 V
VI = VCC or GND,
One input at VCC – 0.6 V,
∆ICC
Ci
2
2.3 V
0.2
VI = 0 to 3.6 V‡
VO = VCC or GND
IOZ§
ICC
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
II(hold)
(
)
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
3.3 V
3.5
3.3 V
9
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
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5
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
Clock frequency
Hold time
MIN
MAX
VCC = 2.7 V
MIN
135
MAX
VCC = 3.3 V
± 0.3 V
MIN
135
3.3
3.3
3.3
A data before CLK↑
†
2
2
1.7
B data before CLK↑
†
2.2
2.1
1.8
SEL before CLK↑
†
1.6
1.6
1.3
CLKENA1 or CLKENA2 before CLK↑
†
1
1.2
0.9
OE before CLK↑
†
1.5
1.6
1.3
A data after CLK↑
†
0.7
0.6
0.6
B data after CLK↑
†
0.7
0.6
0.6
SEL after CLK↑
†
1.1
0.7
0.7
CLKENA1 or CLKENA2 after CLK↑
†
1
0.8
1.1
OE after CLK↑
†
0.8
0.8
0.8
UNIT
MAX
135
†
Pulse duration, CLK high or low
Setup time
MAX
†
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
† This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
fmax
tpd
d
CLK
ten
CLK
tdis
di
CLK
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
135
VCC = 2.7 V
MIN
MAX
135
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
135
MHz
B
†
1
8.2
7.3
1
6.2
A
†
1
6.4
5.8
1
5
B
†
1
7.9
6.7
1
6.1
A
†
1
7.6
6.2
1
5.9
B
†
1
8.1
6.9
1
6.1
A
†
1
7.5
6.8
1
5.6
ns
ns
ns
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
per exchanger
TEST CONDITIONS
VCC = 1.8 V
TYP
All outputs enabled
All outputs disabled
CL = 50 pF,
pF
f = 10 MHz
† This information was not available at the time of publication.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
†
87
120
†
80.5
118
UNIT
pF
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
Output
Control
(low-level
enabling)
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
VOL + 0.3 V
tPZH
tPHL
VOH
1.5 V
2.7 V
1.5 V
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
0V
0V
tsu
Input
1.5 V
Input
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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9
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1999, Texas Instruments Incorporated