TI SN75LPE185NTE4

SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
Single-Chip RS-232 Interface for IBM
PC-Compatible Serial Port
Designed to Transmit and Receive 4-µs Pulses
(Equivalent to 256 kbit/s)
Standby Power Is Less Than 750 µW Maximum
Wide Supply-Voltage Range . . . 4.75 V to 15 V
Driver Output Slew Rates Are Internally
Controlled to 30 V/µs Maximum
RS-232 Bus-Pin ESD Protection Exceeds:
– 15 kV, Human-Body Model
Receiver Input Hysteresis . . . 1000 mV Typical
Three Drivers and Five Receivers Meet or
Exceed the Requirements of TIA/EIA-232-F and
ITU v.28 Standards
Complements the SN75LP196
One Receiver Remains Active During WAKE-UP
Mode (100 µA Maximum)
Matches Flow-Through Pinout of
Industry-Standard SN75185, SN75C185, and
SN75LP185, With Additional Control Pins
Package Options Include Plastic Shrink
Small-Outline (DB), Small-Outline (DW), and
Thin Shrink Small-Outline (PW) Packages, and
Standard Plastic (NT) DIPs
DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
VDD
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
VSS
EN
MODE
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
GND
NC
NC
NC – No internal connection
description
The SN75LPE185 is a low-power bipolar device containing three drivers and five receivers, with 15-kV ESD
protection on the bus pins, with respect to each other. Bus pins are defined as those pins that tie directly to the
serial-port connector, including GND. The pinout matches the flow-through design of the industry-standard
SN75185, SN75C185, and SN75LP185, with the addition of four pins for control signals. The flow-through
pinout of the device allows easy interconnection of the universal asynchronous receiver/transmitter (UART) and
serial-port connector of the IBM PC compatibles. The SN75LPE185 provides a rugged, low-cost solution for
this function, with the combination of bipolar processing and 15-kV ESD protection.
The SN75LPE185 has an internal slew-rate control to provide a maximum rate of change in the output signal
of 30 V/µs. The driver output swing is clamped at ±6 V to enable the higher data rates associated with this device
and to reduce EMI emissions. Although the driver outputs are clamped, the outputs can handle voltages up to
±15 V without damage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM is a trademark of International Business Machines Corporation.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
description (continued)
The device has flexible control options for power management when the serial port is inactive. A common
disable for all of the drivers and receivers is provided with the active-low enable (EN) input. The mode-control
(MODE) input selects between the STANDBY and WAKE-UP modes. With a low-level input on MODE and a
high-level input on EN, one receiver remains active, while the remaining drivers and receivers are disabled to
implement the WAKE-UP mode. With a high-level input on both MODE and EN, all drivers and receivers are
disabled to implement the STANDBY mode. The outputs of the drivers are in the high-impedance state when
the device is powered off. To ensure the outputs of the receivers are in a known output level (as listed in the
Application Information section of this data sheet) when the device is powered off, in STANDBY mode, or in
WAKE-UP mode, external pullup/pulldown circuitry must be provided. All the logic inputs accept 3.3-V or 5-V
input signals.
The SN75LPE185 complies with the requirements of TIA/EIA-232-F and ITU v.28 standards. These standards
are for data interchange between a host computer and peripheral at signaling rates up to 20 kbit/s. The switching
speeds of the SN75LPE185 support rates up to 256 kbit/s.
The SN75LPE185 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC SHRINK
SMALL OUTLINE
(DB)
PLASTIC
SMALL OUTLINE
(DW)
PLASTIC
THIN SHRINK
SMALL OUTLINE
(PW)
PLASTIC
DIP
(NT)
0°C to 70°C
SN75LPE185DBR
SN75LPE185DW
SN75LPE185PWR
SN75LPE185NT
The DB and PW packages are only available taped and reeled. The DW package is also available taped and
reeled. Add the suffix R to device type (e.g., SN75LPE185DWR).
Function Tables
DRIVERS
INPUT
DA
ENABLE
EN
OUTPUT
DY
X
H
Z
H
L
L
L
L
H
Open
L
L
H
Open
L
L
Open
H
H = high level, L = low level,
X = irrelevant, Z = high impedance (off)
2
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
Function Tables (Continued)
RECEIVERS
ENABLE
INPUTS
INPUTS
OUTPUTS
RA1–RA4
RA5
EN
MODE
RY1–RY4
RY5
H
H
L
X
L
L
L
L
L
X
H
H
X
H
H
L
Z
L
X
L
H
L
Z
H
X
X
H
H
Z
Z
Open
Open
L
X
H
H
H
H
L
Open
L
L
L
L
L
Open
H
H
X
H
H
Open
Z
L
X
L
H
Open
Z
H
H
H
Open
X
L
L
L
L
Open
X
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
functional logic diagram (positive logic)
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
EN
MODE
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
11
12
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Positive supply voltage range: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V
Negative supply voltage range, VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to –15 V
Receiver input voltage range, VI (RA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V
Driver input voltage range, VI (DA, EN, MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.4 V
Receiver output voltage range, VO (RY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Driver output voltage range, VO (DY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to 15 V
Electrostatic discharge, bus pins: Human-body model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . Class 3: 15 kV
Machine model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3: 500 V
Electrostatic discharge, all pins: Human-body model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3: 5 kV
Machine model (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3: 200 V
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
(see Note 4): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal unless otherwise noted.
2. Per MIL-STD-883 Method 3015.7
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-3.
recommended operating conditions
NOM
MAX
UNIT
5
5.25
V
12
15
V
–12
–15
V
Supply voltage (see Note 5)
Supply voltage
9
VSS
VIH
Supply voltage
–9
High-level input voltage
DA, EN, MODE
VIL
VI
Low-level input voltage
DA, EN, MODE
Receiver input voltage range
RA
IOH
IOL
High-level output current
Low-level output current
2
V
25
V
RY
–1
mA
RY
2
mA
70
°C
–25
0
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V
0.8
TA
Operating free-air temperature
NOTE 5: VCC cannot be greater than VDD.
4
MIN
4.75
VCC
VDD
• DALLAS, TEXAS 75265
SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
supply currents over the recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
IDD
Supplyy current for VCC
Supplyy current for VDD
TEST CONDITIONS
No load,
All inputs at
minimum VOH
or maximum VOL
No load,
All inputs at
minimum VOH
or maximum VOL
MIN
TYP
VDD = 9 V, VSS = –9 V, EN at GND,
See Note 6
ISS
Supply
y current for VSS
UNIT
1000
VDD = 12 V, VSS = –12 V, EN at GND
EN, MODE at VCC
1000
µA
µ
650
EN at VCC, MODE at GND
700
VDD = 9 V, VSS = –9 V, EN at GND,
See Note 6
800
VDD = 12 V, VSS = –12 V, EN at GND
EN, MODE at VCC
800
µA
µ
20
EN at VCC, MODE at GND
No load,
All inputs at
minimum VOH
or maximum VOL
MAX
20
VDD = 9 V, VSS = –9 V, EN at GND,
See Note 6
–625
VDD = 12 V, VSS = –12 V, EN at GND
–625
EN, MODE at VCC
µA
µ
–50
EN at VCC, MODE at GND
NOTE 6: Minimum RS-232 driver output voltages are not attained with ±5-V supplies.
–50
driver electrical characteristics over the recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD = 9 V, VSS = –9 V, EN at GND,
See Note 6
5
5.8
6.6
VDD = 12 V, VSS = –12 V,
EN at GND, See Note 7
5
5.8
6.6
VDD = 9 V, VSS = –9 V, EN at GND,
See Note 6
–5
–5.8
–6.9
VDD = 12 V, VSS = –12 V,
EN at GND, See Note 7
–5
–5.8
–6.9
High-level
g
output voltage
VI = 0.8 V,, RL = 3 kΩ,,
See Figure 1
Low-level
output voltage
VI = 2 V,, RL = 3 K,,
See Figure 1
High-level input current
Low-level input current
VI at VCC
VI at GND
IOZ
High-impedance
output current
VCC = 5 V, VDD = 12 V, VSS = –12 V, –5 V ≤ VO ≤ 5 V
IOS(H)
Short-circuit high-level
output current
VO = GND or VSS,
See Figure 2 and Note 8
IOS(L)
Short-circuit low-level
output current
VO = GND or VSS,
See Figure 2 and Note 8
VOH
VOL
IIH
IIL
UNIT
V
V
1
µA
–1
µA
±100
µA
–30
–55
mA
30
55
mA
VDD = VSS = VCC = 0,
VO = 2 V
300
Ω
NOTES: 6. Minimum RS-232 driver output voltages are not attained with ±5-V supplies.
7. Maximum output swing is limited to ±5.5 V to enable the higher data rates associated with this device and to reduce EMI emissions.
8. Not more than one output should be shorted at one time.
ro
Output resistance
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
driver switching characteristics over operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CL = 15 pF, See Figure 1
300
800
1600
ns
RL = 3 kΩ to 7 kΩ,
CL = 15 pF, See Figure 1
300
800
1600
ns
Driver output-enable time
to low-level output
RL = 3 kΩ to 7 kΩ,
CL = 15 pF
STANDBY or WAKE-UP modes,
See Figures 1 and 6 and Note 7
50
100
µs
tPZH
Driver output-enable time
to high-level output
RL = 3 kΩ to 7 kΩ,
CL = 15 pF
STANDBY or WAKE-UP modes,
See Figures 1 and 6 and Note 7
50
100
µs
tPLZ
Driver output-disable time
from low-level output
RL = 3 kΩ to 7 kΩ,
CL = 15 pF
STANDBY or WAKE-UP modes,
See Figures 1 and 6 and Note 7
50
100
µs
tPHZ
Driver output-disable time
from high-level output
RL = 3 kΩ to 7 kΩ,
CL = 15 pF
STANDBY or WAKE-UP modes,
See Figures 1 and 6 and Note 7
50
100
µs
tPHL
Propagation delay time,
high- to low-level output
RL = 3 kΩ to 7 kΩ,
tPLH
Propagation delay time,
low- to high-level output
tPZL
tTLH
Transition time,,
low- to high-level output
VCC = 5 V,
VDD = 12 V,
VSS = –12
12 V,
V
RL = 3 kΩ to 7 kΩ,
See Figure 1 and Note 7
Using 10%-to-90% transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
Using ±3-V transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
Using ±2-V transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
Using ±3-V transition region,
Driver speed = 125 kbit/s,
CL = 2500 pF
Using 10%-to-90% transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
tTHL
Transition time,,
high- to low-level output
VCC = 5 V,
VDD = 12 V,
VSS = –12
12 V,
V
RL = 3 kΩ to 7 kΩ,
See Figure 1 and Note 7
Using ±3-V transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
Using ±2-V transition region,
Driver speed = 250 kbit/s,
CL = 15 pF
375
2240
200
1500
ns
133
1000
2750
375
2240
200
1500
ns
133
1000
Using ±3-V transition region,
Driver speed = 125 kbit/s,
CL = 2500 pF
SR
Output slew rate
VCC = 5 V,
VDD = 12 V,
VSS = –12 V,
RL = 3 kΩ to 7 kΩ,
CL = 15 pF,
See Note 7
Using ±3-V transition region,
Driver speed = 0 to 250 kbit/s
2750
4
20
30
V/µs
NOTE 7: Maximum output swing is limited to ±5.5 V to enable the higher data rates associated with this device and to reduce EMI emissions.
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
receiver electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.6
2
2.55
V
0.6
1
1.45
600
1100
VIT+
VIT–
Positive-going input threshold voltage
See Figure 3
Negative-going input threshold voltage
See Figure 3
VHYS
VOH
Input hysteresis, VIT+ – VIT–
See Figure 3
High-level output voltage
2.5
3.9
VOL
Low-level output voltage
IOH = –1 mA
IOL = 2 mA
IIH
High level input current
High-level
VI = 3 V
VI = 25 V
IIL
Low level input current
Low-level
VI = –3 V
VI = –25 V
IOS(H)
IOS(L)
Short-circuit high-level output current
IOZ
RIN
High-impedance output current
Short-circuit low-level output current
VO = 0,
VO = VCC,
V
0.33
0.5
0.43
0.6
1
3.6
5.1
8.3
–0.43
–0.6
–1
–3.6
–5.1
–8.3
V
mA
mA
See Figure 5 and Note 8
–20
mA
See Figure 5 and Note 8
20
mA
±100
µA
7
kΩ
VCC= 0 or 5 V,
0.3 V ≤ VO ≤ VCC
VI = ±3 V to ±25 V
Input resistance
V
mV
3
5
NOTE 8: Not more than one output should be shorted at one time.
receiver switching characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPHL
tPLH
Propagation delay time, high- to low-level output
400
900
ns
Propagation delay time, low- to high-level output
400
900
ns
tTLH
tTHL
Transition time low- to high-level output
200
500
ns
Transition time high- to low-level output
200
400
ns
tSK(P)
tPZL
Pulse skew |tPLH – tPHL|
200
425
ns
50
100
µs
tPZH
tPLZ
Receiver output-enable time to high-level output
50
100
µs
Receiver output-disable time from low-level output
50
100
µs
tPHZ
tPHL
Receiver output-disable time from high-level output
50
100
µs
Propagation delay time, high- to low-level output (WAKE-UP mode)
500
1500
ns
tPLH
Propagation delay time, low- to high-level output (WAKE-UP mode)
500
1500
ns
STANDBY mode
CL = 50 pF,
S Figures
See
Fi
4 and
d7
Receiver output-enable time to low-level output
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
tw
Inputs
50%
VI
II
IO
VI
3V
Outputs
0V
CL
VO
50%
tPLH
RL
VO
tPHL
VTR+ VTR+
50%
VTR–
50%
VTR–
VOH
VOL
tTHL
tTLH
NOTES: A. The pulse generator has the following characteristics:
For CL < 1000 pF: tw = 4 µs, PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns.
For CL = 2500 pF: tw = 8 µs, PRR = 125 kbit/s, ZO = 50 Ω, tr = tf < 50 ns.
B. CL includes probe and jig capacitance.
Figure 1. Driver Parameter Test Circuit and Waveform
Inputs
Outputs
II
VDD
VCC
GND
VSS
IO
VI
VO
Figure 2. Driver IOS Test
Inputs
Outputs
II
VI
IO
VO
Figure 3. Receiver VIT Test
tw
Inputs
Outputs
II
50%
VIL
IO
tPLH
CL
VI
VIH
50%
VI
VO
VO
tPHL
50%
10%
90%
tTLH
90%
50%
10%
8
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• DALLAS, TEXAS 75265
VOL
tTHL
NOTES: A. The pulse generator has the following characteristics: tw = 4 µs, PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns.
B. CL includes probe and jig capacitance.
Figure 4. Receiver Parameter Test Circuit and Waveform
VOH
SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
Inputs
Outputs
II
IO
VI
VCC
GND
VO
Figure 5. Receiver IOS Test
From Output
Under Test
3V
CL = 15 pF
(see Note A)
RL
50%
VI
0V
tPZL
LOAD CIRCUIT
50%
tPLZ
0V
VO
Waveform 1
(see Note B)
50%
tPZH
VO
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50%
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 6. Driver 3-State Parameter Load Circuit and Voltage Waveforms
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
4V
From Output
Under Test
S1
5 kΩ
TEST
S1
tPHL/tPLH
tPLZ/tPZL
tPHZ/tPZH
Open
4V
GND
Open
GND
CL = 50 pF
(see Note A)
LOAD CIRCUIT
3V
50%
VI
50%
0V
tPLZ
tPZL
4V
VO
Waveform 1
(see Note B)
50%
tPHZ
tPZH
VO
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
50%
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, tr = tf < 50 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 7. Receiver 3-State Parameter Load Circuit and Voltage Waveforms
10
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SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
receiver output states
RECEIVER KNOWN OUTPUT STATES
DURING POWER-DOWN, STANDBY, OR WAKE-UP MODES
RECEIVER NUMBER
SIGNAL NAME
RECEIVER OUTPUT
RY1
DCD
High
RY2
DSR
High
RY3
RX
Low
RY4
CTS
High
RY5
RI
High
fault protection during power down
Diodes placed in series with the VDD and VSS leads protect the SN75LPE185 in the fault condition, in which the
device outputs are shorted to ±15 V and the power supplies are at low voltage and provide low-impedance paths
to ground.
VDD
Output
SN75LPE185
Output
SN75LPE185
VSS
Figure 8. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F
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11
SN75LPE185
LOW-POWER MULTIPLE RS-232 DRIVERS/RECEIVERS
WITH ENABLE
SLLS256F – DECEMBER 1996 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
WAKE-UP mode
While in the WAKE-UP mode, all the drivers and receivers of the SN75LPE185 device are in the high-impedance
state, except for receiver 5, which can be used as a ring indicator function. In this mode, the current drawn from
the power supplies is low, to conserve power.
In today’s PCs, board designers are becoming more concerned about power consumption. The flexibility of the
SN75LPE185 during WAKE-UP mode allows the designer to operate the device at auxiliary power-supply
voltages below specified levels. The SN75LPE185 functions properly during WAKE-UP mode, using the
following power-supply conditions:
(a) VCC = 4.75 V, VDD = 9 V, and VSS = –9 V (data-sheet specifications)
(b) VCC = 5 V, VDD = 5 V, and VSS = –5 V
(c) VCC = 5 V, VDD = open, and VSS = open
(d) VCC = 5 V, VDD = 5 V, and VSS is shorted to the most negative supply.
Condition (a) describes the minimum supply voltages necessary for the device to comply fully to specifications.
Conditions (b) and (d) describe the condition where a –5-V supply is not available during auxiliary power. In this
case, VSS must be shorted to the most negative supply (i.e., GND or a voltage source close to, but below GND).
Condition (c) states VDD and VSS power supplies can be shut off.
In all cases, GND is understood to be 0 V, and the power-supply voltages should never exceed the absolute
maximum ratings.
12
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75LPE185DBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPD
Level-1-260C-UNLIM
SN75LPE185DBRE4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPD
Level-1-260C-UNLIM
SN75LPE185DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LPE185DWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LPE185DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LPE185DWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LPE185NT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LPE185NTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LPE185PWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LPE185PWRE4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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