TI TMS28F400BZ

TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
D
D
D
D
D
D
D
D
D
D
524 288 by 8 Bits
262 144 by 16 Bits
Array-Blocking Architecture
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– Three 128K-Byte Main Blocks
– One 16K-Byte Protected Boot Block
– Top or Bottom Boot Locations
All Inputs / Outputs TTL Compatible
Maximum Access/Minimum Cycle Time
VCC ± 10%
’28F400BZx80
80 ns
’28F400BZx90
90 ns
(x = top (T) or bottom (B) boot-block
configuration ordered)
10 000 Program/Erase-Cycles
Two Temperature Ranges
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
Low Power Dissipation ( VCC = 5.5 V )
– Active Write . . . 330 mW ( Byte Write)
– Active Read . . . 330 mW ( Byte Read)
– Active Write . . . 358 mW ( Word Write)
– Active Read . . . 330 mW ( Word Read)
– Block Erase . . . 165 mW
– Standby . . . 0.55 mW (CMOS-Input
Levels)
– Deep Power-Down Mode . . . 0.0066 mW
Fully Automated On-Chip Erase and
Word / Byte-Program Operations
Write Protection for Boot Block
Industry Standard Command State Machine
(CSM)
– Erase Suspend/Resume
– Algorithm-Selection Identifier
DBJ PACKAGE
( TOP VIEW )
Organization . . .
VPP
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A –1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
PIN NOMENCLATURE
A0 – A17
BYTE
DQ0 – DQ14
DQ15/A –1
E
G
NC
RP
VCC
VPP
VSS
W
Address Inputs
Byte Enable
Data In / Out
Data In / Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
5-V Power Supply
12-V Power Supply for
Program / Erase
Ground
Write Enable
description
The TMS28F400BZx is a 524 288 by 8-bit / 262 144 by 16-bit (4 194 304-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F400BZx is organized in a blocked architecture
consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and
three 128K-byte main blocks. The device can be ordered with either a top or bottom boot-block configuration.
Operation as a 512K-byte (8-bit) or a 256K-word (16-bit) organization is user-definable.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
description (continued)
Embedded program and block-erase functions are fully automated by an on-chip write state machine (WSM),
simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status
can be monitored by the on-chip status register to determine progress of program / erase tasks. The device
features user-selectable block erasure.
The TMS28F400BZx flash memory is offered in a 44-pin PSOP. It is available in two temperature ranges:
0°C to 70°C and – 40°C to 85°C.
device symbol nomenclature
TMS28F400BZT
80
B
DBJ
L
Temperature Range Designator
L =
0°C to 70°C
E = – 40°C to 85°C
Program/Erase Endurance
B = 10 000 Cycles
Boot Block Location Indicator
T = Top Location
B = Bottom Location
2
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Package Designator
DBJ = Plastic Small-Outline Package
Speed Designator
80 = 80 ns (± 10% VCC tolerance)
90 = 90 ns (± 10% VCC tolerance)
• HOUSTON, TEXAS 77251–1443
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
functional block diagram
DQ8 – DQ15/A –1
DQ0 – DQ7
8
8
8
DQ15/A –1
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
Data
Register
Identification
Register
Status
Register
Input
Buffer
PowerReduction
Control
BYTE
E
W
G
Command
State
Machine
Output
Multiplexer
A0 – 18
A17
I/O Logic
RP
Data
Comparator
Write
State
Machine
Program/
Erase
Voltage
Switch
VPP
Address
Latch
Y Gating / Sensing
Y Decoder
Address
Counter
X Decoder
16K-Byte
Boot
Block
8K-Byte
8K-Byte
Parameter Parameter
Block
Block
96K-Byte
Main
Block
128K-Byte 128K-Byte 128K-Byte
Main
Main
Main
Block
Block
Block
architecture
The TMS28F400BZx uses a blocked architecture to allow independent erasure of selected memory blocks. The
block to be erased is selected by using any valid address within that block.
block memory maps
The TMS28F400BZx is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F400BZB (bottom boot block ) is mapped with the 16K-byte boot block located at the low-order address
range (00000h to 01FFFh). The TMS28F400BZT (top boot block ) is inverted with respect to the
TMS28F400BZB (bottom boot block) since the boot block is located at the high-order address range (3E000h
to 3FFFFh). Both of these address ranges are for word-wide mode. Figure 1 and Figure 2 show the memory
maps for these configurations.
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3
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
block memory maps (continued)
Address
Range
7FFFFh
7C000h
7BFFFh
7A000h
79FFFh
78000h
77FFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
00000h
×8 Configuration
×16 Configuration
Boot Block
16K Addresses
Boot Block
8K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
DQ15/A –1 Is LSB Address
Address
Range
3FFFFh
3E000h
3DFFFh
3D000h
3CFFFh
3C000h
3BFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
00000h
A0 Is LSB Address
Figure 1. TMS28F400BZT ( Top Boot Block ) Memory Map
Address
Range
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
×8 Configuration
×16 Configuration
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Boot Block
16K Addresses
Boot Block
8K Addresses
DQ15/A –1 Is LSB Address
Address
Range
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
A0 Is LSB Address
Figure 2. TMS28F400BZB (Bottom Boot Block ) Memory Map
4
POST OFFICE BOX 1443
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. To
protect data within this memory sector, the RP pin can be used to provide a lockout to eliminate either accidental
erase or program operations. When RP is operated with normal TTL / CMOS logic levels, the contents of the
boot block cannot be erased or reprogrammed. Changes to the contents of the boot block can be made only
when RP is at VHH (nominally 12 V ) during normal write/erase operations.
parameter block
Two parameter blocks of 8K bytes each can be used as a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution should be exercised because the parameter block does not
have the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F400BZx is located in four main blocks. Three of the blocks have storage
capacity for 128K bytes and the fourth block has storage capacity for 96K bytes.
command state machine
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. The available commands are listed in Table 1 and
the description of these commands are shown in Table 2. When a program or erase command is issued to the
CSM, the WSM controls the internal sequences and the CSM only responds to status reads. After the WSM
completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the
full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0 – DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
Table 1. Command State Machine Codes for Device Mode Selection
COMMAND
CODE ON
DQ0 – DQ7†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
DEVICE MODE
Invalid / Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
† DQ0 is the least significant bit. DQ8 – DQ15 can be any valid 2-state
level.
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
command definition
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 2 for the CSM command definitions and
data for each of the bus cycles.
Following the read-algorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code. The codes are shown in Table 4 and Table 5.
Table 2. Command Definitions
FIRST BUS CYCLE
BUS
CYCLES
REQUIRED
OPERATION
Read Array
1
Write
Read Algorithm-Selection Code
3
Read Status Register
2
Clear Status Register
1
COMMAND
SECOND BUS CYCLE
CSM
INPUT
OPERATION
ADDRESS
DATA
IN / OUT
X
FFh
Read
X
Data Out
Write
X
90h
Read
A0
M/D
Write
X
70h
Read
X
SRB
Write
X
50h
40h or 10h
Write
PA
PD
ADDRESS
Read Operations
Program Mode
Program Setup / Program
(byte / word)
2
Write
PA
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
Write
BEA
20h
Write
BEA
D0h
Erase-Suspend/
Erase-Resume
2
Write
X
B0h
Write
X
D0h
Legend:
BEA
M/D
PA
PD
SRB
X
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent/ device-equivalent code
Address to be programmed
Data to be programmed at PA
Status-register data byte that can be found on DQ0 – DQ7
Don’t care
status register
The status register allows the user to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0 – DQ7. This is valid for operation in either the byte- or word-wide mode.
When writing to the CSM in word-wide mode, the high order I/Os (DQ8 – DQ15) can be set to any valid 2-state
level. When reading the status bits during word-wide read operation, the high order I/Os (DQ8 – DQ15) are set
to 00h internally so the user only needs to interpret the low order I/Os (DQ0 – DQ7).
After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status-register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register
input change during a status-register read. To ensure that the status-register output contains updated status
data, E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 3 defines the
status-register bits and their functions.
6
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
status register (continued)
Table 3. Status-Register Bit Definitions and Functions
STATUS
BIT
SB7
FUNCTION
Write state machine status
Write-state-machine
DATA
COMMENTS
1 = Readyy
0 = Busy
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling
operations can be performed. Until this occurs, the other status
valid If the WSM status bit shows busy (0),
(0) the user
bits are not valid.
must periodically toggle E or G to determine when the WSM has
completed an operation (SB7 = 1 ) since SB7 is not automatically
updated at the completion of a WSM task.
SB6
Erase-suspend status
(ESS)
1 = Erase suspended
0 = Erase in progress or
completed
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1) indicating that the
erase operation has been suspended. The WSM status bit is also
set high (SB7 = 1) indicating that the erase-suspend operation
has been successfully completed. The ESS bit remains at a
logic-high level until an erase-resume command is input to the
CSM (code D0h ).
SB5
Erase status
(ES)
1 = Block-erase error
0 = Block-erase good
SB5 = 0 indicates that a successful block erasure has occurred.
SB5 = 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
completely erase the device.
SB4
Program status
(PS)
1 = Byte / word-program error
0 = Byte / word-program good
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to correctly program the addressed block location.
SB3
VPP status
(VPPS)
1 = Program abort:
VPP range error
0 = VPP good
SB3 provides information on the status of VPP during
programming. If VPP is lower than VPPL after a program or erase
command has been issued, SB3 is set to a 1 indicating that the
programming operation is aborted. If VPP is between VPPH and
VPPL, SB3 is not set.
SB2 –
SB0
Reserved
These bits should be masked out when reading the status
register.
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8 – DQ15 and
a lower-half that outputs data through DQ0 – DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to, or read from, I/O pins DQ0 – DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to, or read from, I/O pins DQ0 – DQ7. In the
byte-wide mode, I/O pins DQ8 – DQ14 are placed in the high-impedance state and DQ15/A –1 becomes the
low-order address pin and selects either the upper or lower half of the array. Array data from the upper half
(DQ8– DQ15) and the lower half (DQ0 – DQ7) are multiplexed in order to appear on DQ0 – DQ7. Table 4 and
Table 5 summarize operations for word-wide mode and byte-wide mode, respectively.
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
byte-wide or word-wide mode selection (continued)
Table 4. Operation Modes for Word-Wide Mode (BYTE = VIH)
MODE
Read
Algorithm-selection mode
Output disable
Standby
E
G
RP
W
A9
A0
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
X
VPP
X
VID
VIL
X
Manufacturer-equivalent code 0089h
Device-equivalent code 4470h
(top boot block)
VIL
VIL
VIH
VIH
VID
VIH
X
VIL
VIH
VIH
X
VIH
VIH
VIH
X
X
X
X
Hi-Z
X
X
X
Hi-Z
X
X
VIL
VIH or
VHH
X
X
X
X
Hi-Z
X
VPPL or
VPPH
Reset / deep power down
Write (see Note 1)
DQ0 – DQ15
Data out
VIL
VIH
VIL
X
Device-equivalent code 4471h
(bottom boot block)
Data in
X = Don’t care
NOTE 1: When writing commands to the ’28F400BZx, VPP must be VPPH for block-erase or program commands to be executed and RP must
be held at VHH for the entire boot-block program or erase operation.
Table 5. Operation Modes for Byte-Wide Mode (BYTE = VIL )
MODE
Read lower byte
Read upper byte
Algorithm-selection
g
mode
E
G
RP
W
A9
A0
VPP
DQ15 / A –1
DQ8 – DQ14
DQ0 – DQ7
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
X
X
Data out
X
X
VIL
VIH
Hi-Z
X
Hi-Z
Data out
VIL
VIL
VIH
VIH
VID
VIL
X
X
Hi-Z
Manufacturer-equivalent
code 89h
Device-equivalent
code
q
70h (top boot block)
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi Z
Hi-Z
VIL
VIH
VIH
X
VIH
VIH
VIH
X
X
X
X
X
Hi-Z
Hi-Z
X
X
X
X
Hi-Z
Hi-Z
Reset / deep power
down
X
X
VIL
X
X
X
X
X
Hi-Z
Hi-Z
Write (see Note 1)
VIL
VIH
VIH or
VHH
VIL
X
X
VPPL
or
VPPH
X
Hi-Z
Data in
Output disable
Standby
Device-equivalent code
71h (bottom boot block)
X = Don’t care
NOTE 1: When writing commands to the ’28F400BZx, VPP must be VPPH for block-erase or program commands to be executed and RP must
be held at VHH for the entire boot-block program or erase operation.
command state machine operations
The CSM decodes instructions for clear status-register, read array, read algorithm-selection code, read
status-register, program, erase, erase-suspend, and erase-resume operations. The 8-bit command code is
input to the device on DQ0 – DQ7 (see Table 1 for CSM codes). During a program or erase cycle, the CSM
informs the WSM that a program or erase cycle has been requested. During a program cycle, the WSM controls
the program sequences and the CSM responds only to status reads.
8
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
command state machine operations (continued)
During an erase cycle, the CSM responds to status read and the erase-suspend commands. When the WSM
has completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range
( VPPH). For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the VPP status bit (SB3), the program status bit (SB4) and the erase status
bit (SB5) of the status register. The clear status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize internal operations. When the status bits are cleared, the device returns
to the read array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D
Read array
The array is read by entering the command code FFh on DQ0 – DQ7. Control pins E and G must be at a
logic-low level ( VIL ) and W and RP must be at a logic-low level ( VIH ) to read data from the array. Data is
available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode ). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
D
Read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0 – DQ7. Two bus cycles are
required for this operation. The first bus cycle is used to enter the command code and the second bus cycle
is used to read the device-equivalent code. Control pins E and G must be at a logic-low level ( VIL ) and W and
RP must be at a logic-high level ( VIH). Two identifier bytes are accessed by toggling A0. The
manufacturer-equivalent code is obtained on DQ0 – DQ7 with A0 at a logic-low level ( VIL ). The
device-equivalent code is obtained when A0 is set to a logic-low level ( VIH). Alternatively, the manufacturerand device-equivalent codes can be read by applying VID (nominally 12 V ) to A9 and selecting the desired
code by toggling A0 high or low. All other addresses are in the “don’t care” category (see Table 2, Table 4,
and Table 5).
D
Read status register
The status register is read by entering the command code 70h on DQ0 – DQ7. Control pins E and G must be
at a logic-low level ( VIL ) and W and RP must be at a logic-low level ( VIH ). Two bus cycles are required for this
operation: one to enter the command code and a second to read the status register. In a given read cycle, the
status-register contents are updated on the falling edge of E or G, whichever occurs last within the cycle.
boot-block programming/erasing
Should changes to the boot block be required, RP must be set to VHH (12 V ) and VPP must be set to the
programming voltage level ( VPPH). If an attempt is made to write, erase or erase-suspend the boot block without
RP at VHH, an error signal is generated on SB4 (program-status bit) or SB5 (erase-status bit).
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to status
reads. When the WSM status bit (SB7) is set to a logic-low level, signifying termination of the nonprogram
operation, all commands to the CSM become valid again.
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
normal programming
There are two CSM commands for programming: program setup and alternate program setup
(see Table 1 ). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM cannot normally be interrupted until the program algorithm has
been completed (see Figure 3 and Figure 4). Taking RP to VIL during programming aborts the program
operation. During programming, VPP must remain at VPPH. Only 0s are written and compared during a program
operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh ( in byte-wide mode) or FFFFh ( in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
erase operations
There are two erase operations that can be performed by the TMS28F400BZx devices: block erase and erase
suspend/ erase resume. An erase operation must be used to initialize all bits in an array block to 1s. After
block-erase confirm is issued, the CSM responds only to status reads or erase-suspend commands until the
WSM completes its task.
D
Block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single address locations within the array cannot be individually erased.
The block to be erased is selected by using any valid address within that block. RP must be at VHH for
changing the data content of the boot block. Block erasure is initiated by a command sequence to the CSM:
block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A two-command erase
sequence protects against accidental erasure of memory contents.
Erase setup and confirm commands are latched on the rising edge of E or W, whichever occurs first. Block
addresses are latched during the block-erase-confirm command on the rising edge of E or W (see Figure 10
and Figure 11 ). When the block-erase-confirm command is complete, the WSM automatically executes a
sequence of events to complete the block erasure. During this sequence, the block is programmed with
logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all
bits are correctly erased. Monitoring of the erase operation is possible through the status register (see the
subsection, “read status register”).
D
Erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h ) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data should be read from a block other than the one being erased. To
resume the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear
the suspend state previously set (see Figure 5 and Figure 6).
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read. During this time, the
device switches to the automatic power-saving (APS) mode. When the device switches to this mode, ICC is
typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is maintained until another read
operation is initiated. In this mode, the I/O pins retain the data from the last memory-address read until a new
address is read. This mode is entered automatically if no address or control pins toggle within a 200-ns time-out
period. At least one transition on E must occur after power up to activate this mode.
10
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BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
reset/ deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, an ICC value on the order of 0.2 µA, or 1 µW
of power, is achievable. This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum
of td(RP) is required before data is valid, and a minimum of trec(RPHE) and / or trec(RPHW) in deep power-down
mode is required before data input to the CSM can be recognized. With RP at ground, the WSM is reset and
the status register is cleared, effectively eliminating accidental programming to the array during system reset.
After restoration of power, the device does not recognize any operation command until RP is returned to a VIH
or VHH level.
Should RP go low during a program or erase operation, the device will power down and, therefore, will become
nonfunctional and data being written or erased will be invalid or indeterminate, requiring that the operation be
performed again after power restoration.
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SMJS400E – JUNE 1994 – REVISED JANUARY 1998
Start
BUS
OPERATION
Issue Program-Setup
Command and Byte Address
Issue Byte
Address/Data
COMMAND
Write
Writeprogram
setup
Data = 40h or 10h
Addr = Address of
byte to be
programmed
Write
Write data
Data = Byte to be
programmed
Addr = Address of
byte to be
programmed
Read Status-Register Bits
SB7 = 1
?
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Check SB7
1 = Ready, 0 = Busy
No
Yes
Full Status-Register
Check (optional)
COMMENTS
Repeat for subsequent bytes.
Write FFh after the last byte-programming operation to
reset the device to read-array mode.
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
SB3 = 0
?
No
BUS
OPERATION
VPP Range Error
Standby
Byte-Program
Failed
Standby
COMMAND
Yes
SB4 = 0
?
No
COMMENTS
Check SB3
1 = Detect VPP low
(see Note B)
Check SB4
1 = Byte-program error
(see Note C)
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flowchart
12
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SMJS400E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
COMMAND
Write
Writeprogram
setup
Data = 40h or 10h
Addr = Address of
word to be
programmed
Write
Write data
Data = Word to be
programmed
Addr = Address of
word to be
programmed
Issue Program-Setup Command
and Word Address
Issue Word Address/Data
Read Status-Register Bits
SB7 = 1
?
No
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Check SB7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register Check
(optional)
COMMENTS
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
SB3 = 0
?
No
VPP Range Error
COMMAND
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4
1 = Word-program
failed
(see Note C)
Yes
SB4 = 0
?
No
COMMENTS
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flowchart
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SMJS400E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write-erase
setup
Data = 20h
Block Addr = Address
within
block to
be
erased
Write
Erase
Data = D0h
Block Addr = Address
within
block to
be
erased
Issue Erase-Setup Command and
Block Address
Issue Block-Erase-Confirm
Command and Block Address
Read
Status-Register Bits
No
SB7 = 1
?
No
EraseSuspend
?
EraseSuspend
Loop
Yes
Read
Status-register data.
Toggle G or E to update
status register
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Full Status-Register
Check (optional)
See Note A
Repeat for subsequent blocks.
Write FFh after the last block-erase operation to reset the
device to read array mode.
Block-Erase Completed
FULL STATUS-REGISTER CHECK FLOW
Read Status-Register
Bits
SB3 = 0
?
BUS
OPERATION
No
VPP Range Error
COMMAND
COMMENTS
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4 and SB5
1 = Block-erase
command error
Standby
Check SB5
1 = Block-erase failed
(see Note C)
Yes
SB4 = 1,
SB5 = 1
?
No
Yes
SB5 = 0
?
No
Command-Sequence
Error
Block-Erase Failed
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flowchart
14
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BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
Write
Issue Erase-Suspend
Command
Read Status-Register
Bits
SB7 = 1
?
No
Yes
SB6 = 1
?
COMMENTS
Data = B0h
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Check SB7
1 = Ready
Standby
Check SB6
1 = Suspended
Erase Completed
Write
Issue Memory-Read
Command
Read
memory
Read
No
Issue Erase-Resume
Command
Erase Continued
Erasesuspend
No
Yes
Finished
Reading
?
Yes
COMMAND
Write
Data = FFh
Read data from block
other than that being
erased.
Eraseresume
Data = D0h
See Note A
NOTE A: Refer to automated block-erase flowchart for complete erasure procedure.
Figure 6. Erase-Suspend / Resume Flowchart
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BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
RP, A9 (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Operating free-air temperature range, TA, during read/erase/program: L suffix . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. All voltage values are with respect to VSS.
3. The voltage on any input can undershoot to – 2 V for periods less than 20 ns.
4. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
recommended operating conditions
VCC
Supply voltage
During write/read/erase/erase-suspend
During read only ( VPPL )
VPP
Supply voltage
VIH
High level dc input voltage
High-level
CMOS
TTL
VLKO
VHH
VCC lock-out voltage from write/erase
RP unlock voltage
MAX
4.5
5
5.5
V
6.5
V
12.6
V
VCC + 0.5
VCC + 0.5
V
11.4
TTL
Low level dc input voltage
Low-level
NOM
0
During write/erase/erase-suspend ( VPPH)
VIL
MIN
CMOS
12
2
VCC – 0.5
– 0.5
UNIT
0.8
VSS – 0.2
2
V
V
VSS + 0.2
V
V
11.5
12
13
V
word/byte-write and block-erase performance (see Notes 5 and 6)
’28F400BZx 80
’28F400BZx 90
PARAMETER
MIN
TYP
UNIT
MAX
Main-block erase time
2.2
14
s
Main-block byte-program time
3.2
4.2
s
1.6
2.1
s
0.32
7
s
Main-block word-program time
Parameter/ boot-block-erase time
NOTES: 5. Excludes system-level overhead
6. Typical values shown are at TA = 25°C, VPP = 12 V.
16
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BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, using test conditions given in Table 6 (unless otherwise noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
VID
Low-level output voltage
TEST CONDITIONS
TTL
IOH = – 2.5 mA,
IOH = – 100 µA,
CMOS
VCC = 4.5 V,
IID
IRP
A9 selection code current
A9 = VID
IO
IPPS
Output current (leakage)
IPPL
IPP1
VCC = 4.5 V
IOL = 5.8 mA
VI = 0 V to 5.5 V
RP boot-block unlock current
VPP standby current (standby)
VPP supply current (reset / deep power-down mode)
VCC = 5.5 V,
VPP ≤ VCC
VO = 0 V to VCC
RP = VSS ± 0.2 V, VPP < VCC
VPP > VCC
UNIT
V
VCC – 0.4
11.5
VCC = 5.5 V,
MAX
2.4
A9 selection code voltage
Input current (leakage), except for A9 when A9 = VID
(see Note 7)
II
MIN
VCC = 4.5 V
0.45
V
13
V
±1
µA
500
µA
500
µA
±10
µA
10
µA
5
µA
200
µA
IPP2
VPP supply current (active read)
VPP supply current (active byte-write)
(see Notes 8 and 9)
VPP = VPPH,
Programming in progress
30
mA
IPP3
VPP supply current (active word-write)
(see Notes 8 and 9)
VPP = VPPH,
Programming in progress
40
mA
IPP4
VPP supply current (block-erase) (see Notes 8 and 9)
VPP = VPPH,
Block-erase in progress
30
mA
IPP5
VPP supply current (erase-suspend)
(see Notes 8 and 9)
VPP = VPPH,
Block-erase suspended
200
µA
ICCS
VCC supply current (standby)
E = RP = VIH
1.5
mA
E = RP = VIH
ICCL
ICC1
TTL-input level
CMOS-input level
VCC supply current (reset / deep power-down
power down mode)
VCC = 5.5 V,
VCC = 5.5 V,
RP = VSS ± 0.2
02V
100
µA
0°C to 70°C
1.2
µA
– 40°C to 85°C
12
1.2
µA
TTL-input level
VCC = 5.5 V,
f = 10 MHz,
E = VIL,
IOUT = 0 mA
60
mA
CMOS-input level
VCC = 5.5 V,
f = 10 MHz,
E = VSS ± 0.2 V,
IOUT = 0 mA
55
mA
VCC supply current (active read)
ICC2
VCC supply current (active byte-write)
(see Notes 8 and 9)
VCC = 5.5 V,
Programming in progress
60
mA
ICC3
VCC supply current (active word-write)
(see Notes 8 and 9)
VCC = 5.5 V,
Programming in progress
65
mA
ICC4
VCC supply current (block-erase) (see Notes 8 and 9)
VCC = 5.5 V,
Block-erase in progress
30
mA
ICC5
VCC supply current (erase-suspend)
(see Notes 8 and 9)
VCC = 5.5 V,
E = VIH,
Block-erase suspended
10
mA
NOTES: 7. DQ15/A–1 is tested for output leakage only.
8. Characterization data available
9. All current values are root mean square (RMS) unless otherwise noted.
Table 6. AC Test Conditions
IOL
(mA)
IOH
(mA)
VZ†
(V)
VOL
(V)
2.1
– 0.4
1.5
0.8
† VZ is the measured value used to detect high impedance.
VOH
(V)
VIL
(V)
VIH
(V)
CLOAD
(pF)
tf
(ns)
tr
(ns)
2.0
0.45
2.4
100
< 10
< 10
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BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz, VI = 0 V
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TEST CONDITIONS
MIN
VO = 0 V
MAX
UNIT
8
pF
12
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
read operations
ALT.
SYMBOL
PARAMETER
ta(A)
ta(E)
Access time from A0 – A17 (see Note 10)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
Access time from E
Cycle time, read
MAX
UNIT
ns
90
ns
tGLQV
tAVAV
40
45
ns
Hold time, DQ valid from A0 – A17, E, or G, whichever occurs first
(see Note 10)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
td(RP)
tdis(BL)
Output delay time from RP high
POST OFFICE BOX 1443
MIN
90
th(D)
18
’28F400BZx 90
80
Disable time, G to high-impedance output
ta(BH)
Access time from BYTE going high
NOTE 10: A–1 – A17 for byte-wide
MAX
80
tEHQZ
tGHQZ
Disable time, BYTE low to DQ8 – DQ15 in high-impedance state
MIN
tAVQV
tELQV
tELQX
tGLQX
Delay time, G low to low-impedance output
’28F400BZx 80
80
90
ns
0
0
ns
0
0
ns
30
35
ns
30
35
ns
0
0
ns
5
5
ns
tPHQV
tFLQV
300
300
ns
30
35
ns
tFHQV
80
90
ns
• HOUSTON, TEXAS 77251–1443
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
write/erase operations — W-controlled writes
ALT.
SYMBOL
tc( W )
tc( W )OP
Cycle time, write
tc( W )ERB
tc( W )ERP
Cycle time, erase operation (boot block)
tc( W )ERM
Cycle time, erase operation (main block)
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
th(RP)
Hold time, VPP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 – A17 (see Note 10)
tsu(E)
tsu(RP)
Setup time, E before write operation
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
trec( RPHW )
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Hold time, A0 – A17 (see Note 10)
tAVAV
tWHQV1
tWHQV2
tWHQV3
tWHQV4
tPHBR
tWHAX
tWHDX
tWHEH
Hold time, E
Hold time, RP at VHH from valid status-register bit
tQVVL
tQVPH
tAVWH
’28F400BZx 80
MIN
MAX
’28F400BZx 90
MIN
MAX
UNIT
80
90
ns
6
7
µs
0.3
0.4
s
0.3
0.4
s
0.6
0.7
100
s
100
ns
10
10
ns
0
0
ns
10
10
ns
0
0
ns
0
0
ns
50
50
ns
tDVWH
tELWL
50
50
ns
0
0
ns
tPHHWH
tVPWH
100
100
ns
100
100
ns
tWLWH
tWLWL
60
60
ns
Pulse duration, W high
20
30
ns
Recovery time, RP high to W going low
tPHWL
215
215
ns
Setup time, DQ
Setup time, RP at VHH to W going high
Pulse duration, W low
NOTE 10: A–1 – A17 for byte-wide
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
write/erase operations — E-controlled writes
ALT.
SYMBOL
tc( W )
tc(E)OP
Cycle time, write using E
tc(E)ERB
tc(E)ERP
Cycle time, erase operation using E (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation using E (main block)
th(A)
th(D)
Hold time, A0 – A17 (see Note 10)
th( W )
th (VPP)
Hold time, W
th(RP)
tsu(A)
Hold time, RP at VHH from valid status-register bit
tsu(D)
tsu( W )
Setup time, DQ valid
tsu(RP)
tsu( VPP)2
Setup time, RP at VHH to E going high
tw(E)
tw(EH)
Pulse duration, E low, write using E
Cycle time, duration of programming operation using E
Cycle time, erase operation using E (parameter block)
Delay time, boot-block relock
Hold time, DQ valid
Hold time, VPP from valid status-register bit
Setup time, A0 – A17 (see Note 10)
Setup time, W before E
Setup time, VPP to E going high
Pulse duration, E high, write using E
trec(RPHE) Recovery time, RP high to E going low
NOTE 10: A–1 – A17 for byte-wide
20
POST OFFICE BOX 1443
tAVAV
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tPHBR
tEHAX
tEHDX
tEHWH
tQVVL
’28F400BZx 80
MIN
MAX
’28F400BZx90
MIN
MAX
UNIT
80
90
ns
6
7
µs
0.3
0.4
s
0.3
0.4
s
0.6
0.7
100
10
s
100
ns
10
ns
0
0
ns
10
10
ns
0
0
ns
0
0
ns
50
50
ns
tDVEH
tWLEL
50
50
ns
0
0
ns
tPHHEH
tVPEH
100
100
ns
100
100
ns
tELEH
tEHEL
50
50
ns
30
40
ns
tPHEL
215
215
ns
tQVPH
tAVEH
• HOUSTON, TEXAS 77251–1443
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
tc(R)
A –1 – A17
(byte-wide)
A0 – A17
(word-wide)
Address Valid
ta(A)
E
tdis(E)
ta(E)
G
tdis(G)
ta(G)
W
td(G)
th(D)
td(E)
DQ0 – DQ7 (byte-wide)
DQ0 – DQ15 (word-wide)
VCC
Hi-Z
Hi-Z
td(RP)
RP
Figure 7. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A17 Standby
(byte-wide)
A0 – A17
(word-wide)
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte / Word
Programming
Write
Read-Array
Command
Read StatusRegister Bits
tc(W)
tsu(A)
th(A)
E
tsu(E)
th(E)
G
tc( W )OP
tw( WH )
W
DQ0 – DQ7
(byte-wide)
DQ0 – DQ15
(word-wide)
tw( W )
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
FFh
Hi-Z
40h or 10h
trec(RPHW)
tsu(RP)
th(RP)
V
V
RP
th( VPP)
tsu( VPP)1
V
VPP
V
Figure 8. Write-Cycle Timing ( W-Controlled Write)
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power
Up and
A –1 – A17 Standby
(byte-wide)
A0 – A17
(word-wide)
Write
Program-Setup
Command
Automated
Byte / Word
Programming
Write Valid
Address
And Data
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
W
tsu( W )
th( W )
G
tc(E)OP
tw(EH)
E
DQ0–DQ7
(byte-wide)
DQ0–DQ15
(word-wide)
tw(E)
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
FFh
Hi-Z
40h or 10h
trec(RPHE)
tsu(RP)
th(RP)
RP
tsu( VPP)2
th( VPP)
VPPH
VPP
VPPL
Figure 9. Write-Cycle Timing (E-Controlled Write)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power
Up and
A –1 – A17 Standby
(byte-wide)
A0 – A17
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
E
tsu(E)
th(E)
G
tc( W )ERB
tc( W )ERP
tc( W )ERM
tw( WH)
W
DQ0 –DQ7
(byte-wide)
DQ0 –DQ15
(word-wide)
tw( W )
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHW)
FFh
Hi-Z
tsu(RP)
th(RP)
VHH
VIH
RP
tsu( VPP)1
th( VPP)
VPPH
VPPL
VPP
Figure 10. Erase-Cycle Timing (W-Controlled Write)
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A17 Standby
(byte-wide)
A0 – A17
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
W
tsu( W )
th( W )
G
tc(E)ERB
tc(E)ERP
tc(E)ERM
tw(EH)
E
DQ0 – DQ7
(byte-wide)
DQ0 – DQ15
(word-wide)
tw(E)
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHE)
FFh
Hi-Z
tsu(RP)
th(RP)
RP
tsu( VPP)2
th( VPP)
VPP
Figure 11. Erase-Cycle Timing (E-Controlled Write)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
A0 – A17
Address Valid
tc( R )
ta(A)
E
ta(E)
tdis(E)
G
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
DQ0 – DQ7
Hi-Z
Hi-Z
Byte DQ0 – DQ7
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
ta(A)
tdis(BL)
Word DQ8 – DQ14
DQ15/A –1
Hi-Z
A –1 Input
Word DQ15
Figure 12. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Hi-Z
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
A0 – A17
Address Valid
tc( R )
ta(A)
E
ta(E)
tdis(E)
G
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
Byte DQ0 – DQ7
ta(BH)
DQ0 – DQ7
Hi-Z
Hi-Z
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
Word DQ8 – DQ14
Word DQ15
DQ15/A –1
A –1 Input
Hi-Z
Hi-Z
Figure 13. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
1,27
0,16 M
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°– 8°
0,80
Seating Plane
2,625 MAX
0,50 MIN
0,10
4073325 / A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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