TI TMS28F004AEB

524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
D Organization . . . 524 288 By 8 Bits
D
D
D
D
D
D
D
D
262 144 By 16 Bits
Array-Blocking Architecture
− One 16K-Byte Protected Boot Block
− Two 8K-Byte Parameter Blocks
− One 96K-Byte Main Block
− Three 128K-Byte Main Blocks
− Top or Bottom Boot Locations
’28F400Axy Offers a User-Defined 8-Bit
(Byte) or 16-Bit (Word) Organization
’28F004Axy Offers Only the 8-Bit
Organization
Maximum Access / Minimum Cycle Time
− Commercial and Extended
5-V VCC ± 10%
3.3-V VCC ± 0.3 V
’28F400Axy60 60 ns 110 ns
’28F400Axy70 70 ns 130ns
’28F400Axy80 80 ns 150 ns
− Automotive (offered for only 5-V VCC
voltage configurations)
5-V VCC ± 10%
’28F400Axy70 70 ns
’28F400Axy80 80 ns
’28F400Axy90 90 ns
(x = S, E, F, M, or Z Depending on VCC / VPP
Configuration)
(y = T or B for Top or Bottom Boot-Block
Configuration)
100 000 and 10 000 Program / Erase Cycle
Versions
Three Temperature Ranges
− Commercial . . . 0°C to 70°C
− Extended . . . − 40°C to 85°C
− Automotive . . . − 40°C to 125°C
Industry Standard Packages Offered in
− 40-Pin TSOP (DCD Suffix)
− 44-Pin PSOP (DBJ Suffix)
− 48-Pin TSOP (DCD Suffix)
Low Power Dissipation ( VCC = 5.5 V )
− Active Write . . . 248 mW ( Byte Write)
− Active Read . . . 330 mW ( Byte Read)
− Active Write . . . 248 mW ( Word Write)
− Active Read . . . 330 mW ( Word Read)
− Block Erase . . . 165 mW
− Standby . . . 0.72 mW (CMOS-Input
Levels)
DBJ PACKAGE
( TOP VIEW )
VPP
DU/WP
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A −1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
PIN NOMENCLATURE
A0 −A17
BYTE
DQ0 −DQ14
DQ15/A −1
E
G
NC
RP
VCC
VPP
VSS
W
DU/WP
Address Inputs
Byte Enable
Data In / Out
Data In / Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power-Down
Power Supply
Power Supply for Program / Erase
Ground
Write Enable
Do Not Use for ’AMy or ’AZy /Write Protect
D Fully Automated On-Chip Erase and
Word / Byte Program Operations
D Write Protection for Boot Block
D Industry Standard Command-State Machine
D
D
(CSM)
− Erase Suspend/Resume
− Algorithm-Selection Identifier
Three Different Combinations of Supply
Voltages Offered
All Inputs / Outputs TTL Compatible
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (
#% %$!'"($%
%$#,#!, /#!!#$- !,'&$ )!&(%%0 ,(% $ (&(%%#!+ &+',(
$(%$0 #++ )#!#"($(!%-
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1
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
DCD PACKAGE-40 PIN
(TOP VIEW)
A16
A15
A14
A13
A12
A11
A9
A8
W
RP
VPP
DU/WP
A18
A7
A6
A5
A4
A3
A2
A1
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
A17
GND
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
G
GND
E
A0
DCD PACKAGE-48 PIN
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
VPP
DU/WP
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
2
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
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A16
BYTE
GND
DQ15/A −1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
GND
E
A0
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . .
block memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
reset / deep power-down mode . . . . . . . . . . . . . . . . . . . . . . .
boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
power-supply detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TMS28F004ASy and TMS28F400ASy . . . . . . . . . . . . . . . . . . .
command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . 8
TMS28F004AEy and TMS28F400AEy . . . . . . . . . . . . . . . . . . .
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TMS28F004AMy and TMS28F400AMy . . . . . . . . . . . . . . . . . .
command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TMS28F004AFy and TMS28F400AFy . . . . . . . . . . . . . . . . . . .
status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TMS28F004AZy and TMS28F400AZy . . . . . . . . . . . . . . . . . . .
byte-wide or word-wide mode selection . . . . . . . . . . . . . . . . 11
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . .
command-state machine (CSM) operations . . . . . . . . . . . 13
mechanical data − DBJ (R-PDSO-G44) . . . . . . . . . . . . . . . . .
clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
mechanical data − DCD (R-PDSO-G**) . . . . . . . . . . . . . . . . .
14
14
15
15
15
16
21
22
23
33
44
52
62
71
78
79
description
The TMS28F400Axy is a 524288 by 8 bits/ 262 144 by 16 bits (4194 304-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F400Axy is organized in a blocked architecture
consisting of:
D
D
D
D
One 16K-byte protected boot block
Two 8K-byte parameter blocks
One 96K-byte main block
Three 128K-byte main blocks
Table 1 lists the five different voltage configurations available for ordering. Operation as a 512K-byte (8-bit) or
a 256K-word (16-bit) organization is user-definable.
Table 1. VCC/VPP Voltage Configurations, Temperature, and Speeds Matrix
DEVICE CONFIGURATION
DEVICE
READ (VCC)
PROGRAM/ERASE (VPP)
TMS28F400ASy
3.3 V± 0.3 V or 5 V±10%
5 V±10% or 12 V±5%
TMS28F400AEy
2.7 to 3.6 V or 5 V±10%
5 V±10% or 12 V±5%
TMS28F400AMy
3.3 V± 0.3 V or 5 V±10%
12 V±10%
TMS28F400AFy
TMS28F400AZy
5 V±10%
5V
V±10%
10%
5 V±10% or 12 V±5%
12 V
V±10%
10%
TEMPERATURE
(TA)
ACCESS SPEEDS − 5-V(3.3-V) VCC
0°C to 70°C
60(110), 70(130), 80(150) ns
−40°C to 85°C
60(110), 70(130), 80(150) ns
0°C to 70°C
60(110), 70(130), 80(150) ns
−40°C to 85°C
60(110), 70(130), 80(150) ns
0°C to 70°C
60(110), 70(130), 80(150) ns
−40°C to 85°C
60(110), 70(130), 80(150) ns
0°C to 70°C
60, 70, 80 ns
−40°C to 85°C
60, 70, 80 ns
−40°C to 125°C†
70, 80, 90 ns
0°C to 70°C
60, 70, 80 ns
−40°C to 85°C
60, 70, 80 ns
−40°C to 125°C†
70, 80, 90 ns
† Only the 44-pin PSOP is offered in the −40°C to 125°C temperature range.
NOTE 1: All configurations are available in the TMS28F004Axy (8 bit configuration only) and top or bottom boot.
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description (continued)
The TMS28F004Axy is offered in a 512K-byte organization only. The operation for this device is the same as
the TMS28F400Axy and is offered in the same voltage configurations. TMS28F004Axy can be substituted for
the byte-wide TMS28F400Axy with the latter being the generic name for this device family.
Embedded program and block-erase functions are fully automated by the on-chip write state machine (WSM),
simplifying these operations and relieving the system microcontroller of secondary tasks. WSM status can be
monitored by an on-chip status register to determine progress of program / erase tasks. The device features
user-selectable block erasure.
The configurations are as follows:
D The TMS28F400ASy configuration has the auto-select feature that allows the user alternative read and
program / erase voltages. Memory reads can be performed using 3.3-V VCC for optimum power
consumption or 5-V VCC for device performance. Erasing or programming the device can be accomplished
with 5-V VPP, which eliminates having to use a 12-V source and / or in-system voltage converters.
Alternatively,12-V VPP operation exists for systems that already have a 12-V power supply, which provides
faster programming and erasing times. This configuration is offered in two temperature ranges: 0°C to 70°C
and −40°C to 85°C.
D The TMS28F400AEy configuration offers the auto-select feature of the TMS28F400ASy with an extended
VCC range of 2.7-V to 3.6-V (3-V nominal). Memory reads can be performed using 3-V VCC, for more efficient
power consumption than the ’ASy device.
D The TMS28F400AMy configuration offers a 3-V or 5-V memory read with a 12-V program and erase. This
configuration is intended for low 3.3-V reads and the fast programming offered with the 12-V VPP and 5-V
VCC. This configuration is offered in two temperature ranges: 0°C to 70°C and − 40°C to 85°C.
D The TMS28F400AFy configuration offers a 5-V memory read with a 5-V or 12-V program and erase. This
configuration is intended for systems using a single 5-V power supply. This configuration is offered in three
temperature ranges: 0°C to 70°C, − 40°C to 85°C, and − 40°C to 125°C.
D The TMS28F400AZy configuration offers a 5-V memory read with a 12-V program and erase for fast
programming and erasing times. This configuration is offered in three temperature ranges: 0°C to 70°C,
− 40°C to 85°C, and − 40°C to 125°C.
The y in the device name represents a T for top or B for bottom boot-block configuration.
All configurations of the TMS28F400Axy are offered in a 44-pin plastic small-outline package (PSOP) and a
48-pin thin small-outline package (TSOP). The TMS28F004Axy is offered in a 40-pin TSOP only. Both the 40-pin
and 48-pin TSOP are offered for the 0°C to 70°C and − 40°C to 85°C temperature ranges only.
4
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
device symbol nomenclature
TMS28F400AS
T
60
C
DBJ
L
Temperature Range Designator
L =
0°C to 70°C
E = − 40°C to 85°C
Q = − 40°C to 125°C
Program/Erase Endurance
C = 100 000 Cycles
B = 10 000 Cycles
Boot-Block Location Indicator
T = Top Location
B = Bottom Location
S
E
M
F
Z
Package Designator
DBJ = 44 Lead PSOP
DCD= 40 Lead TSOP
DCD= 48 Lead TSOP
Speed Designator
60 = 60 ns
70 = 70 ns
80 = 80 ns
90 = 90 ns
= (3.3 V ± 0.3 V or 5 V ± 10%) VCC and (5 V ± 10% or 12 V ± 5%) VPP
= (2.7 V to 3.6 V or 5 V ± 10%) VCC and (5 V ± 10% or 12 V ± 5%) VPP
= (3.3 V ± 0.3 V or 5 V ± 10%) VCC and (12 V ± 5%) VPP
= 5 V ± 10% VCC and (5 V ± 10% or 12 V ± 5%) VPP
= 5 V ± 10% VCC and 12V ± 5% VPP
Configuration
400 = 256K 16-bit or 512K 8-bit
004 = 512K 8-bit
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
functional block diagram
DQ8 − DQ15/A −1
DQ0 − DQ7
8
8
8
DQ15/A −1
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
Data
Register
I/O Logic
Identification
Register
Output
Multiplexer
Status
Register
A0 − 17
A17
Input
Buffer
PowerReduction
Control
Data
Comparator
E
W
G
Command
State
Machine
Write
State
Machine
BYTE
RP
WP
Program/
Erase
Voltage
Switch
VPP
Address
Latch
Y Decoder
Address
Counter
X Decoder
Y Gating / Sensing
16K-Byte
Boot
Block
8K-Byte
8K-Byte
Parameter Parameter
Block
Block
96K-Byte
Main
Block
128K-Byte 128K-Byte 128K-Byte
Main
Main
Main
Block
Block
Block
architecture
The TMS28F400Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The
block to be erased is selected by using any valid address within that block.
block memory maps
The TMS28F400Axy is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F400AxB (bottom boot block) is mapped with the 16K-byte boot block located at the low-order address
range (00000h to 01FFFh). The TMS28F400AxT (top boot block) is inverted with respect to the TMS28F400AxB
with the boot block located at the high-order address range (3E000h to 3FFFFh). Both of these address ranges
are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations. The
TMS28F004Axy is mapped as the 8-bit configuration of the TMS28F400Axy, except that the least significant
bit (LSB) is A0 instead of A−1.
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block memory maps (continued)
Address
Range 8-Bit Configuration
7FFFFh
7C000h
7BFFFh
7A000h
79FFFh
78000h
77FFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
00000h
16-Bit
Configuration
Address
Range
Boot Block
16K Addresses
Boot Block
8K Addresses
3FFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
3E000h
3DFFFh
3D000h
3CFFFh
3C000h
3BFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
00000h
DQ15/A −1 Is LSB Address
A0 Is LSB Address
NOTE A: The TMS28F004AxT is mapped the same as the 8-bit configuration of the TMS28F400AxT except that the LSB is A0.
Figure 1. TMS28F400AxT ( Top Boot Block ) Memory Map (See Note A)
Address
Range 8-Bit Configuration
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
16-Bit
Configuration
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Boot Block
16K Addresses
Boot Block
8K Addresses
DQ15/A −1 Is LSB Address
Address
Range
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
A0 Is LSB Address
NOTE A: The TMS28F004AxB is mapped the same as the 8-bit configuration of the TMS28F400AxB except that the LSB is A0.
Figure 2. TMS28F400AxB (Bottom Boot Block ) Memory Map (See Note A)
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boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data
in this block can be secured by using different combinations of the reset/ power-down pin (RP), the write protect
pin (WP) and VPP supply levels. Table 2 provides a list of these combinations.
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution must be exercised because the parameter block does not have
the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F400Axy is located in four main blocks. Three of the blocks have storage
capacity for 128K bytes and the fourth block has storage capacity for 96K bytes.
data protection
Data is secured or unsecured by using different combinations of the reset / power-down pin (RP), the write
protect pin (WP), and VPP supply levels. Table 2 provides a list of these combinations.
There are two configurations to secure the entire memory against inadvertant alteration of data. The VPP supply
pin can be held below the VPP lock-out voltage level (VPPLK) or the reset / deep power-down pin (RP) can be
pulled to a logic-low level. Note if RP is held low, the device resets which means it powers down and, therefore,
cannot be read. Typically this pin tied to the system reset for additional protection during system power up.
The boot block sector has an additional security feature through the WP pin (’ASy, ’AEy, and ’AFy device
configurations only). When the RP pin is at a logic-high level, the WP pin controls whether the boot block sector
is protected. When WP is held at the logic-low level, the boot block is protected. When WP is held at the
logic-high level, the boot block is unprotected along with the rest of the other sectors. Alternatively, the entire
memory for all voltage configurations can be unprotected by pulling the RP pin to VHH (12 V).
Table 2. Data-Protection Combinations
’ASy, ’AEy, OR ’AFy
DATA PROTECTION PROVIDED
All blocks locked
All blocks locked (reset)
All blocks unlocked
’AMy OR ’AZy
VPP
VIL
RP
WP†
X
X
X
VIL
VHH
VIH
>VPPLK
>VPPLK
VPP
VIL
RP
WP†
X
X
X
X
VHH
VIL
VHH
X
X
X
VIH
Only boot block locked
>VPPLK
VIH
VIL
VHH
VIH
X
† For the TMS28F400AZy and TMS28F400AMy 12-V VPP-only products, the WP pin is disabled and can be left
floating. To unlock blocks, RP must be at VHH.
command-state machine (CSM)
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. The available commands are listed in Table 3 and
the descriptions of these commands are shown in Table 4. When a program or erase command is issued to the
CSM, the WSM controls the internal sequences and the CSM responds only to status reads. After the WSM
completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the
full command set again.
8
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operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0 −DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 3 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0 −DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
Table 3. CSM Codes for Device Mode Selection
COMMAND
CODE ON
DQ0 −DQ7†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
DEVICE MODE
Invalid / Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
† DQ0 is the least significant bit. DQ8 −DQ15 can be any valid 2-state
level.
command definitions
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and
data for each of the bus cycles. Table 5 lists the status register bits and definitions.
Following the read-algorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code. Table 6, Table 7, and Table 8 list the code.
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command definitions (continued)
Table 4. Command Definitions
COMMAND
BUS
CYCLES
REQUIRED
FIRST BUS CYCLE
OPERATION
ADDRESS
SECOND BUS CYCLE
CSM
INPUT
OPERATION
ADDRESS
DATA
IN / OUT
Data Out
Read Operations
Read Array
1
Write
X
FFh
Read
X
Read Algorithm-Selection Code
2
Write
X
90h
Read
A0
M/D
Read-Status Register
2
Write
X
70h
Read
X
SRB
Clear-Status Register
1
Write
X
50h
40h or 10h
Write
PA
PD
Program Mode
Program Setup / Program
(byte / word)
2
Write
PA
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
Write
BEA
20h
Write
BEA
D0h
Erase Suspend/
Erase Resume
2
Write
X
B0h
Write
X
D0h
Legend:
BEA
M/D
PA
PD
SRB
X
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent/ device-equivalent code
Address to be programmed
Data to be programmed at PA
Status-register data byte that can be found on DQ0 −DQ7
Don’t care
status register
The status register allows the user to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0−DQ7. This is valid for operation in either the byte- or word-wide mode.
When writing to the CSM in word-wide mode, the high order I/O pins (DQ8−DQ15) can be set to any valid 2-state
level. When reading the status bits during a word-wide read operation, the high order I/Os (DQ8 −DQ15) are
set to 00h internally, so the user needs to interpret only the low order I/O pins (D0 −DQ7).
After a read-status command has been given, the data appearing on DQ0−DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring if the register input
change during a status-register read. To ensure that the status-register output contains updated status data,
E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the status
register bits and their functions.
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status register (continued)
Table 5. Status-Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
DATA
COMMENTS
1 = Ready
0 = Busy
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling
operations can be performed. Until this occurs, the other status
bits are not valid. If the WSM status bit shows busy (0), the user
must toggle E or G periodically to determine when the WSM has
completed an operation (SB7 = 1) since SB7 is not updated
automatically at the completion of a WSM task.
Erase-suspend status (ESS)
1 = Erase suspended
0 = Erase in progress or
completed
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1) indicating that the
erase operation has been suspended. The WSM status bit also
is set high (SB7 = 1) indicating that the erase-suspend operation
has been completed successfully. The ESS bit remains at a
logic-high level until an erase-resume command is input to the
CSM (code D0h ).
SB5
Erase status (ES)
1 = Block erase error
0 = Block erase good
SB5 = 0 indicates that a successful block erasure has occurred.
SB5 = 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
erase the device completely.
SB4
Program status (PS)
1 = Byte/word program error
0 = Byte/word program good
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to program the addressed block location correctly.
SB3
VPP status (VPPS)
1 = Program abort:
VPP range error
0 = VPP good
SB3 provides information on the status of VPP during
programming. If VPP is lower than VPPL after a program or erase
command has been issued, SB3 is set to a 1 indicating that the
programming operation is aborted. If VPP is between VPPH and
VPPL, SB3 is not set.
SB2 −
SB0
Reserved
SB7
Write-state-machine status
SB6
These bits must be masked out when reading the status register.
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8−DQ15, and
a lower-half that outputs data through DQ0 −DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to, or read from, I/O pins DQ0−DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0−DQ7. In the byte-wide
mode, I/O pins DQ8 −DQ14 are placed in the high-impedance state and DQ15/A −1 becomes the low-order
address pin and selects either the upper or lower half of the array. Array data from the upper half (DQ8−DQ15)
and the lower half (DQ0 −DQ7) are multiplexed to appear on DQ0 −DQ7. Table 6, Table 7, and Table 8
summarize operational modes.
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byte-wide or word-wide mode selection (continued)
Table 6. Operation Modes for Word-Wide Mode (BYTE = VIH) (see Note 2)
MODE
WP
E
G
RP
W
A9
A0
X
VIL
VIL
VIH
VIH
X
X
VPP
X
X
VIL
VIL
VIH
VIH
VID
VIL
X
Read
DQ0 −DQ15
Data out
Manufacturer-equivalent code
0089h
Device-equivalent code 4470h
(top boot block)
Algorithm-selection mode
X
VIL
VIL
VIH
VIH
VID
VIH
X
Output disable
X
VIH
X
VIH
VIH
VIH
X
X
X
Hi-Z
X
VIL
VIH
X
X
Standby
X
X
X
Hi-Z
X
VIL
VIH
or
VHH
X
X
X
X
Hi-Z
X
VPPL
or
VPPH
Reset / deep power down
X
VIL
or
VIH
Write (see Note 3)
VIL
VIH
VIL
X
Device-equivalent code 4471h
(bottom boot block)
Data in
NOTES: 2. X = don’t care
3. When writing commands to the ’28F400Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).
Table 7. Operation Modes for Byte-Wide Mode (BYTE = VIL ) (see Note 2)
WP
E
G
RP
W
A9
A0
VPP
DQ15 / A −1
DQ8 −DQ14
Read lower byte
MODE
X
VIH
VIH
VIH
VIH
X
X
Data out
X
X
X
VIL
VIH
Hi-Z
X
VIL
VIL
X
Read upper byte
VIL
VIL
Hi-Z
Data out
X
VIL
VIL
VIH
VIH
VID
VIL
X
X
Hi-Z
Manufacturer-equivalent
code 89h
Algorithm-selection
mode
DQ0 −DQ7
Device-equivalent code
70h (top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi-Z
Output disable
X
VIH
VIH
VIH
X
X
X
X
Hi-Z
Hi-Z
X
VIH
X
X
Standby
VIL
VIH
X
X
X
X
Hi-Z
Hi-Z
Reset / deep power
down
X
X
X
VIL
X
X
X
X
X
Hi-Z
Hi-Z
Write (see Note 3)
VIL
or
VIH
VIL
VIH
VIH
or
VHH
VIL
X
X
VPPL
or
VPPH
X
Hi-Z
Data in
Device-equivalent code
71h (bottom boot block)
NOTES: 2. X = don’t care
3. When writing commands to the ’28F400Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).
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byte-wide or word-wide mode selection (continued)
Table 8. Operation Modes for TMS28F004Axy
MODE
WP
E
G
RP
W
A9
X
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
VIL
VIL
VIH
VIH
Output disable
X
Standby
X
VIL
VIH
X
VIH
X
VIH
VIH
X
VIL
VIH
or
VHH
Read
Algorithm-selection mode
Reset / deep power down
Write (see Note 3)
A0
VPP
DQ0 −DQ7
X
X
X
Data out
VID
VIL
X
Manufacturer-equivalent code 89h
VID
VIH
X
Device-equivalent code 79h (bottom boot
block)
VIH
X
X
X
X
Hi-Z
X
X
X
Hi-Z
X
X
X
X
Hi-Z
X
VPPL
or
VPPH
Device-equivalent code 78h (top boot block)
X
VIL
or
VIH
VIL
VIH
VIL
X
Data in
NOTES: 2. X = don’t care
3. When writing commands to the ’28F004Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for a list of the combinations).
command-state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0−DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range.
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the VPP status (SB3), the program status bit (SB4), and the erase status bit
(SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read array mode.
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read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D read array
The array level is read by entering the command code FFh on DQ0−DQ7. Control pins E and G must be at a
logic-low level (VIL ) and W and RP must be at a logic-high level (VIH ) to read data from the array. Data is
available on DQ0−DQ15 (word-wide mode) or DQ0−DQ7 (byte-wide mode). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
D read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0 −DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins E and G must be at a logic-low level ( VIL ) and W and RP must be at a logic-high level
( VIH). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
DQ0−DQ7 with A0 at a logic-low level ( VIL ). The device-equivalent code is obtained when A0 is set to a
logic-high level (VIH). Alternatively, the manufacturer- and device-equivalent codes can be read by applying
VID (nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
“don’t cares” (see Table 4, Table 6, Table 7, Table 8).
D read status register
The status register is read by entering the command code 70h on DQ0−DQ7. Control pins E and G must be
at a logic-low level (VIL ) and W and RP must be at a logic-high level (VIH ). Two bus cycles are required for
this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the
cycle.
programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 3 ). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain in
the appropriate VPP voltage range, as shown in the recommended operating conditions table. Different
combinations of RP, WP, and VPP pin voltage levels ensure that data in certain blocks are secure, and, therefore,
cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared during a
program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
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erase operations
There are two erase operations that can be performed by the TMS28F004Axy and TMS28F400Axy devices:
block erase and erase suspend/ erase resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
D block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single address locations within the array cannot be erased individually.
The block to be erased is selected by using any valid address within that block. Note that different
combinations of RP, WP and VPP pin voltage levels ensure that data in certain blocks are secure and,
therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command
sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against accidental erasure of memory contents.
Erase setup and confirm commands are latched on the rising edge of E or W, whichever occurs first. Block
addresses are latched during the block-erase-confirm command on the rising edge of E or W (see Figure 14
and Figure 15). When the block-erase-confirm command is complete, the WSM automatically executes a
sequence of events to complete the block erasure. During this sequence, the block is programmed with
logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all
bits are correctly erased. Monitoring of the erase operation is possible through the status register (see the
subsection, “read status register”).
D erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data must be read from a block other than the one being erased. To resume
the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear the
suspend state previously set (see Figure 5 and Figure 6).
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read and the device is in the
active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device
switches to this mode, ICC is typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is
maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last
memory address read until a new address is read. This mode is entered automatically if no address or control
pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power
up to activate this mode.
reset/ deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower ICC value or power is achievable.
This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a
minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and trec(RPHW) in deep
power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a VIH or VHH level.
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reset/ deep power-down mode (continued)
If RP goes low during a program or erase operation, the device powers down and, therefore, becomes
nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the
operation be performed again after power restoration.
power-supply detection
RP must be connected to the system reset / power good signal to ensure that proper synchronization is
maintained between the CPU and the flash memory operating modes. The default state after power up and exit
from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that
the operating supply voltage can be established (3 V, 3.3 V or 5 V). Figure 10 shows the proper power-up
sequence. To reset the operating supply voltage, the device must be completely powered off (VCC = 0 V) before
the new supply voltage is detected.
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Start
BUS
OPERATION
Issue Program-Setup
Command and Byte Address
Issue Byte
Address/Data
COMMAND
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of
byte to be
programmed
Write
Write data
Data = Byte to be
programmed
Addr = Address of
byte to be
programmed
Read Status-Register
Bits
SB7 = 1
?
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Check SB7
1 = Ready, 0 = Busy
No
Yes
Full Status-Register
Check (optional)
COMMENTS
Repeat for subsequent bytes
Write FFh after the last byte-programming operation to
reset the device to read-array mode.
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read
Status-Register Bits
SB3 = 0
?
No
BUS
OPERATION
VPP Range Error
Standby
Byte-Program
Failed
Standby
COMMAND
Yes
SB4 = 0
?
No
COMMENTS
Check SB3
1 = Detect VPP low
(see Note B)
Check SB4
1 = Byte-program error
(see Note C)
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flow Chart
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BUS
OPERATION
Start
Read Status-Register
Bits
No
SB7 = 1
?
COMMENTS
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of
word to be
programmed
Write
Write data
Data = Word to be
programmed
Addr = Address of
word to be
programmed
Issue Program-Setup
Command and Word
Address
Issue Word
Address/Data
COMMAND
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Check SB7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register
Check (optional)
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
SB3 = 0
?
No
VPP Range Error
COMMAND
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4
1 = Word-program
error
(see Note C)
Yes
SB4 = 0
?
No
COMMENTS
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flow Chart
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BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write erase
setup
Data = 20h
Block Addr = Address
within
block to
be
erased
Write
Erase
Data = D0h
Block Addr = Address
within
block to
be
erased
Issue Erase-Setup Command
and Block Address
Issue Block-Erase-Confirm
Command and
Block Address
Read Status-Register Bits
No
SB7 = 1
?
No
Erase
Suspend
?
EraseSuspend
Loop
Status-register data.
Toggle G or E to update
status register
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Yes
Full Status-Register
Check (optional)
Read
See Note A
Repeat for subsequent blocks
Write FFh after the last block-erase operation to reset the
device to read-array mode.
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
SB3 = 0
?
BUS
OPERATION
No
SB4 = 1,
SB5 = 1
?
No
Yes
SB5 = 0
?
No
Command Sequence
Error
COMMENTS
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4 and SB5
1 = Block-erase
error
Standby
Check SB5
1 = Block-erase error
(see Note C)
VPP Range Error
Yes
COMMAND
Block-Erase Failed
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flow Chart
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BUS
OPERATION
Start
Write
Issue Erase-Suspend
Command
Read Status-Register
Bits
SB7 = 1
?
No
Erase
suspend
Standby
Check SB7
1 = Ready
Standby
Check SB6
1 = Suspended
Read
memory
No
Write
Erase
Completed
Erase
resume
No
Issue Erase-Resume
Command
Erase Continued
See Note A
NOTE A: See block-erase flowchart for complete erasure procedure.
Figure 6. Erase-Suspend / Resume Flow Chart
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Data = FFh
Read data from block
other than that being
erased.
Issue Memory-Read
Command
Finished
Reading
?
Yes
Data = B0h
Status-register data.
Toggle G or E to update
status register.
Read
Yes
COMMENTS
Read
Write
Yes
SB6 = 1
?
COMMAND
Data = D0h
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 7 V
Supply voltage range, VPP (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to VCC + 1 V
RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 13.5 V
Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to VCC + 1 V
Operating free-air temperature range, TA , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . . − 40°C to 85°C
Q suffix . . . . . . . . . . − 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to VSS.
5. The voltage on any input or output can undershoot to − 2 V for periods less than 20 ns. See Figure 8.
6. The voltage on any input or output can overshoot to 7 V for periods less than 20 ns. See Figure 9.
IOL
VIH
Output
Under
Test
VZ
VOH
VOL
VIL
VOLTAGE WAVEFORMS
CL
(see Note A)
IOH
NOTES: A. CL includes probe and fixture capacitance.
B. AC test conditions are driven at VIH and VIL, Timing measurements are made at VOH and VOL levels on both inputs and outputs.
See Table 9 for values based on VCC operating range..
C. Each device must have a 0.1 mF ceramic capacitor connected to VCC and VSS as close as possible to the device pins.
Figure 7. Load Circuit and Voltage Waveforms
Table 9. AC Test Conditions
VCC RANGE
5 V ± 10%
IOL
2.1
IOH
−0.4
VZ†
1.5
VOL
0.8
VOH
2.0
VIL
0.45
VIH
2.4
CL
tf
tr
100
< 10
< 10
3.3 ± 0.3 V
0.5
−0.5
1.5
1.5
1.5
0.0
3.0
50
< 10
< 10
2.7 to 3.6 V
0.1
−0.1
1.35
1.35
1.35
0.0
2.7
50
< 10
< 10
† VZ is the measured value used to detect high impedance.
5 ns
5 ns
+0.8 V
−0.6 V
− 2.0 V
20 ns
Figure 8. Maximum Negative Overshoot Waveform
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
21
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
20 ns
7V
VCC + 0.5 V
2.0 V
5 ns
5 ns
Figure 9. Maximum Positive Overshoot Waveform
capacitance over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
Ci
Input capacitance
Co
Output capacitance
22
TEST CONDITIONS
VO = 0 V
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MIN
MAX
UNIT
8
pF
12
pF
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
TMS28F004ASy and TMS28F400ASy
The TMS28F004ASy and the TMS28F400ASy configurations have the auto-select feature that allows
alternative read and program/ erase voltages. Memory reads can be performed using VCC = 3.3 V for optimal
power consumption or at VCC = 5 V for device performance. Erasing or programming the device can be
accomplished with VPP = 5 V, which eliminates having to use a 12-V source and / or in-system voltage
converters. Alternatively, the 12-V VPP operation exists for systems that already have a 12-V power supply that
provides faster programming and erasing times. This configuration is offered in two temperature ranges (0°C
to 70°C and −40°C to 85°C).
recommended operating conditions for TMS28F004ASy and TMS28F400ASy
VCC
Supply voltage
3.3-V VCC range
During write/read/erase/erase suspend
During read only ( VPPL )
VPP
Supply voltage
During write/erase/erase suspend
VIH
3.3-V VCC range
3
3.3
3.6
5
5.5
VPPL
5-V VPP range
0
4.5
5
5.5
12-V VPP range
11.4
12
12.6
2
CMOS
VIL
Low-level dc input
voltage
CMOS
TTL
5-V VCC range
CMOS
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase
TA
Operating free-air temperature
V
V
VCC + 0.5
VCC + 0.2
VCC + 0.3
VCC + 0.2
VCC − 0.2
− 0.5
TTL
UNIT
6.5
VCC − 0.2
2
TTL
3.3-V VCC range
MAX
4.5
CMOS
5-V VCC range
NOM
5-V VCC range
TTL
High-level dc input
voltage
MIN
0.8
VSS − 0.2
− 0.3
VSS + 0.2
0.8
VSS − 0.2
2
VSS + 0.2
11.4
V
V
V
13
V
0
12
1.5
V
L Suffix
0
70
E Suffix
− 40
85
°C
NOTE 7: Mimimum value at TA = 25°C.
word/byte typical write and block-erase performance for TMS28F004ASy and TMS28F400ASy
(see Notes 8 and 9)
5-V VPP RANGE
PARAMETER
3.3-V VCC
RANGE
MIN
TYP
12-V VPP RANGE
5-V VCC
RANGE
MAX
MIN
TYP
3.3-V VCC
RANGE
MAX
MIN
TYP
5-V VCC
RANGE
MAX
MIN
TYP
MAX
Main block-erase time
2.4
1.9
1.3
1.1
14
Main block-byte program time
1.7
1.4
1.6
1.2
4.2
Main block-word program time
1.1
0.9
0.8
0.6
2.1
0.84
0.8
0.44
0.34
7
Parameter/ boot-block erase time
NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions.
9. Excludes system-level overhead (all times in seconds)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
23
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, using test conditions listed in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TTL
VOH
High-level dc output voltage
VOL
VID
Low-level dc output voltage
CMOS
VCC = VCC MIN, IOH = − 2.5 mA
VCC = VCC MIN, IOH = − 100 µA
II
Input current (leakage), except for A9 when
A9 = VID (see Note 10)
VCC = VCC MAX, VI = 0 V to VCC MAX,
RP = VHH
IID
A9 selection code current
IRP
RP boot-block unlock current
IO
Output current (leakage)
IPPL
VPP supply current (reset / deep
power-down mode)
IPP1
VPP supply current (active read)
IPP2
IPP3
IPP4
VPP supply current (active byte-write)
(see Notes 11 and 12)
VPP supply current (active word-write)
(see Notes 11 and 12)
VPP supply current (block-erase
(see Notes 11 and 12)
0.45
V
12.6
V
±1
µA
A9 = VID
500
µA
RP = VHH
500
µA
VCC = VCC MAX, VO = 0 V to VCC MAX
3.3-V VCC range
VPP ≤ VCC
5-V VCC range
3.3-V VCC range
RP = VSS ± 0.2 V, VPP ≤ VCC
5-V VCC range
3.3-V VCC range
VPP ≥ VCC
5-V VCC range
5-V VPP range,
3.3-V VCC range
±10
µA
Programming in progress
Programming in progress
Block-erase in progress
POST OFFICE BOX 1443
11.4
15
10
5
5
200
200
25
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
20
5-V VPP range,
3.3-V VCC range
30
5-V VPP range,
5-V VCC range
25
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
20
5-V VPP range,
3.3-V VCC range
30
5-V VPP range,
5-V VCC range
20
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
15
• HOUSTON, TEXAS 77251−1443
µA
A
µA
A
A
µA
30
5-V VPP range,
5-V VCC range
NOTES: 10. DQ15/A−1 is tested for output leakage only.
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
24
UNIT
V
VCC − 0.4
VCC = VCC MIN, IOL = 5.8 mA
During read algorithm-selection mode
VPP standby current (standby)
MAX
2.4
A9 selection code voltage
IPPS
MIN
mA
mA
mA
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, (as on the previous page) using test conditions
listed in Table 9 (unless otherwise noted) (continued)
PARAMETER
IPP5
ICCS
ICCL
TEST CONDITIONS
VPP supply current (erase-suspend)
(see Notes 11 and 12)
ICC3
UNIT
200
5-V VPP range,
5-V VCC range
200
12-V VPP range,
3.3-V VCC range
200
12-V VPP range,
5-V VCC range
200
1.5
mA
2
mA
µA
A
VCC = VCC MAX,
E = RP =VIH
3.3-V VCC range
VCC = VCC MAX,
E = RP= VCC± 0.2 V
3.3-V VCC range
110
CMOS-input level
µA
5-V VCC range
130
µA
VCC supply current
(standby)
VCC supply current (reset / deep
power-down mode)
RP = VSS ± 0.2 V; VCC = VCC MAX
VCC supply
current (active
read)
CMOS-input level
ICC2
MAX
TTL-input level
TTL-input level
ICC1
Block-erase suspended
MIN
5-V VPP range,
3.3-V VCC range
VCC supply current (active byte write)
(see Notes 11 and 12)
VCC supply current (active word-write)
(see Notes 11 and 12)
5-V VCC range
0°C to 70°C
8
− 40°C to 85°C
8
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VIH
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VIH
5-V VCC range
65
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VCC
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VCC
5-V VCC range
60
5-V VPP range,
3.3-V VCC range
30
5-V VPP range,
5-V VCC range
50
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
45
5-V VPP range,
3.3-V VCC range
30
5-V VPP range,
5-V VCC range
50
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
45
VCC = VCC MAX,
Programming in progress
VCC = VCC MAX,
Programming in progress
A
µA
mA
mA
mA
mA
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
25
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, (as on the previous page) using test conditions
listed in Table 9 (unless otherwise noted) (continued)
PARAMETER
ICC4
ICC5
TEST CONDITIONS
VCC supply current (block-erase)
(see Notes 11 and 12)
VCC = VCC MAX,
Block-erase in progress
VCC supply current (erase suspend)
(see Notes 11 and 12)
VCC = VCC MAX, E = VIH,
Block erase suspended
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MIN
MAX
5-V VPP range,
3.3-V VCC range
30
5-V VPP range,
5-V VCC range
35
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
30
3.3-V VCC range
5-V VCC range
UNIT
mA
8
10
mA
Hold time, VCC at 4.5 V (MIN) to RP
high
Setup time, RP high to data valid
Address valid to data valid
t5VPH
tAVQV
tPHQV
tPL5V
tPL3V
ALT.
SYMBOL
2
0
110
800
2
2
0
450
60
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
th(RP3)
Hold time, VCC at 3 V (MIN) to RP high
t3VPH
2
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
th(RP5)
ta(DV)
tsu(DV)
tsu(VCC)
Setup time, RP low to VCC at
4.5 V MIN (to VCC at 3 V MIN or
3.6 V MAX) (see Note 14)
PARAMETER
’28F004ASy60
’28F400ASy 60
2
2
0
MIN
800
130
MAX
3.3-V VCC
RANGE
2
2
0
MIN
450
70
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy 70
2
2
0
MIN
800
150
MAX
3.3-V VCC
RANGE
2
2
0
MIN
450
80
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy 80
µs
µs
ns
ns
ns
UNIT
power-up and reset switching characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of supply
voltage (commercial and extended temperature ranges)(see Notes 11, 12, and 13)
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
27
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tGLQX
tEHQZ
tGHQZ
tAXQX
tPHQV
tFLQZ
Delay time, E low to low-impedance
output
Delay time, G low to low-impedance
output
Disable time, E to high-impedance
output
Disable time, G to high-impedance
output
Hold time, DQ valid from A0 −A17, E, or
G, whichever occurs first
(see Note 15)
Setup time, BYTE from E low
Output delay time from RP high
Disable time, BYTE low to DQ8 −DQ15
in high-impedance state
td(E)
td(G)
tdis(E)
tdis(G)
th(D)
tsu(EB)
td(RP)
tdis(BL)
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
tELQX
Cycle time, read
tc(R)
tFHQV
tELFL
tELFH
tELQV
tGLQV
tAVAV
Access time from G
Access time from E
tAVQV
Access time from A0 −A17
(see Note 15)
ta(E)
ta(G)
ta(A)
ALT.
SYMBOL
PARAMETER
read operations
0
0
0
110
110
45
800
5
45
55
65
110
110
0
0
0
60
60
25
450
5
25
25
35
60
60
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004ASy60
’28F400ASy 60
0
0
0
130
MIN
130
55
800
5
55
70
80
130
130
MAX
3.3-V VCC
RANGE
0
0
0
70
MIN
70
30
450
5
30
30
40
70
70
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy 70
0
0
0
150
MIN
150
60
800
5
60
80
90
150
150
MAX
3.3-V VCC
RANGE
0
0
0
80
MIN
80
30
450
5
30
30
40
80
80
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy 80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
switching characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of supply voltage
(commercial and extended temperature ranges)
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
tWHQV4
tPHBR
tWHAX
Cycle time, erase operation
(main block)
Delay time, boot-block relock
Hold time, A0 −A17
(see Note 15)
tc( W )ERP
tc( W )ERM
td(RPR)
th(A)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tQVPH
tWHPL
tELPH
tAVWH
tDVWH
tELWL
Hold time, RP at VHH from
valid status register bit
Hold time, WP from valid status
register bit
Setup time, WP before write
operation
Setup time, A0 −A17
(see Note 15)
Setup time, DQ
Setup time, E before write
operation
th( VPP)
th(RP)
th(WP)
tsu(WP)
tsu(A)
tsu(D)
tsu(E)
NOTE 15: A−1 −A17 for byte-wide
tQVVL
Hold time, VPP from valid
status register bit
Hold time, E
tWHDX
tWHEH
tWHQV3
Cycle time, erase operation
(parameter block)
tc( W )ERB
Hold time, DQ valid
tWHQV2
Cycle time, erase operation
(boot block)
tc( W )OP
th(D)
th(E)
tWHQV1
Cycle time, duration of
programming operation
tAVAV
Cycle time, write
tc( W )
ALT.
SYMBOL
write/erase operations — W-controlled writes
0
90
90
90
0
0
0
0
0
0
0.6
0.3
0.3
6
200
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
60
100
MAX
MIN
MAX
MIN
110
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004ASy60
’28F400ASy 60
timing requirements for TMS28F004ASy and TMS28F400ASy
0
105
105
105
0
0
0
0
0
0
0.6
0.3
0.3
6
130
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
70
MIN
100
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy70
0
120
120
120
0
0
0
0
0
0
0.6
0.3
0.3
6
150
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
80
MIN
100
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
µs
ns
UNIT
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
29
30
trec(RPHW)
Recovery time, RP high to W
going low
Pulse duration, W high
tPHWL
tWLWH
tWHWL
tsu( VPP)1
Pulse duration, W low
tVPWH
Setup time, VPP to W going
high
tsu(RP)
tw( W )
tw( WH)
tPHHWH
Setup time, RP at VHH to W
going high
ALT.
SYMBOL
write/erase operations — W-controlled writes
800
20
90
200
200
450
10
50
100
100
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004ASy60
’28F400ASy 60
800
25
105
200
200
MIN
MAX
3.3-V VCC
RANGE
450
20
50
100
100
MIN
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy70
timing requirements for TMS28F004ASy and TMS28F400ASy (continued)
800
30
120
200
200
MIN
MAX
3.3-V VCC
RANGE
450
30
50
100
100
MIN
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy80
ns
ns
ns
ns
ns
UNIT
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tEHQV3
tEHQV4
Cycle time, erase operation
(parameter block)
Cycle time, erase operation (main
block)
tc(E)ERB
tc(E)ERP
tc(E)ERM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Setup time, W before write operation
NOTE 15: A−1 −A17 for byte-wide
Setup time, DQ
tsu( W )
90
0
90
90
tWLEL
tELPH
Setup time, WP before write
operation
tsu(WP)
0
0
0
0
0
0
0.6
0.3
0.3
6
200
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
60
100
MAX
MIN
MAX
MIN
110
5-V VCC
RANGE
’28F004ASy60
’28F400ASy 60
3.3-V VCC
RANGE
tAVEH
tDVEH
tWHPL
Hold time, WP from valid status
register bit
th(WP)
Setup time, A0 −A17 (see Note 15)
tQVPH
Hold time, RP at VHH from valid
status-register bit
th(RP)
tsu(A)
tsu(D)
tQVVL
tEHDX
tEHWH
th (VPP)
Hold time, W
Hold time, DQ valid
Hold time, VPP from valid
status-register bit
th(D)
th( W )
Hold time, A0 −A17 (see Note 15)
tPHBR
tEHAX
tEHQV2
Cycle time, erase operation (boot
block)
tc(E)OP
Delay time, boot-block relock
tEHQV1
Cycle time, duration of programming
operation
td(RPR)
th(A)
tAVAV
Cycle time, write
tc( E )
ALT.
SYMBOL
write/erase operations — E-controlled writes
timing requirements for TMS28F004ASy and TMS28F400ASy
0
105
105
105
0
0
0
0
0
0
0.6
0.3
0.3
6
130
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
70
MIN
100
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy70
0
120
120
120
0
0
0
0
0
0
0.6
0.3
0.3
6
150
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
50
0
0
0
0
0
0
0.6
0.3
0.3
6
80
MIN
100
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
µs
ns
UNIT
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
31
32
tEHEL
tPHEL
Pulse duration, E high
Recovery time, RP high to E going
low
tw( EH)
trec(RPHE)
tVPEH
tELEH
Pulse duration, E low
Setup time, VPP to E going high
tPHHEH
tsu( VPP)2
tw(E)
tsu(RP)
Setup time, RP at VHH to E going
high
ALT.
SYMBOL
write/erase operations — E-controlled writes
800
20
90
200
200
450
10
50
100
100
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004ASy60
’28F400ASy 60
800
25
105
200
200
MIN
MAX
450
20
50
100
100
MIN
MAX
5-V VCC
RANGE
’28F004ASy 70
’28F400ASy70
3.3-V VCC
RANGE
timing requirements for TMS28F004ASy and TMS28F400ASy (continued)
800
30
120
200
200
MIN
MAX
3.3-V VCC
RANGE
450
30
50
100
100
MIN
MAX
5-V VCC
RANGE
’28F004ASy 80
’28F400ASy80
ns
ns
ns
ns
ns
UNIT
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
TMS28F004AEy and TMS28F400AEy
The TMS28F004AEy and the TMS28F400AEy configurations offer the auto-select feature of the
TMS28F400ASy with an extended VCC from a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be
performed using a VCC = 3 V, allowing for more efficient power consumption than the ’ASy device.
recommended operating conditions for TMS28F004AEy and TMS28F400AEy
VCC
Supply voltage
During write/read/erase/erase suspend
During read only ( VPPL )
VPP
Supply voltage
During write/erase/erase suspend
MIN
NOM
MAX
3-V VCC range
2.7
3
3.6
5-V VCC range
4.5
5
5.5
VPPL
5-V VPP range
0
4.5
5
5.5
12-V VPP range
11.4
12
12.6
TTL
VIH
High-level dc input
voltage
3-V VCC range
CMOS
VIL
Low-level dc input
voltage
3-V VCC range
CMOS
TTL
5-V VCC range
CMOS
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase
TA
Operating free-air temperature
VCC + 0.3
VCC + 0.2
VCC − 0.2
− 0.5
TTL
V
VCC + 0.5
VCC + 0.2
VCC − 0.2
2
TTL
5-V VCC range
V
6.5
2
CMOS
UNIT
V
0.8
VSS − 0.2
− 0.3
VSS + 0.2
0.8
VSS − 0.2
2
VSS + 0.2
V
V
11.4
13
V
0
12
1.5
V
L Suffix
0
70
E Suffix
− 40
85
°C
NOTE 7: Mimimum value at TA = 25°C.
word/byte typical write and block-erase performance for TMS28F004AEy and TMS28F400AEy
(see Notes 8 and 9)
5-V VPP RANGE
PARAMETER
12-V VPP RANGE
3-V VCC RANGE
5-V VCC RANGE
3-V VCC RANGE
5-V VCC RANGE
MIN
MIN
MIN
MIN
TYP
MAX
Main block-erase time
2.4
1.9
1.3
1.1
14
Main block-byte program time
1.7
1.4
1.6
1.2
4.2
Main block-word program time
1.1
0.9
0.8
0.6
2.1
0.84
0.8
0.44
0.34
7
Parameter/ boot-block erase time
TYP
MAX
TYP
MAX
TYP
MAX
NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions.
9. Excludes system-level overhead (all times in seconds)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
33
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions listed in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TTL
VOH
High-level dc output voltage
VOL
VID
Low-level dc output voltage
CMOS
VCC = VCC MIN, IOH = − 2.5 mA
VCC = VCC MIN, IOH = − 100 µA
MAX
UNIT
2.4
V
VCC − 0.4
VCC = VCC MIN, IOL = 5.8 mA
During read algorithm-selection mode
A9 selection code voltage
MIN
11.4
0.45
V
12.6
V
±1
µA
Input current (leakage), except for A9 when
A9 = VID (see Note 10)
VCC = VCC MAX,VI = 0 V to VCC MAX, RP = VHH
IID
IRP
A9 selection code current
A9 = VID
500
µA
RP boot-block unlock current
RP = VHH
500
µA
IO
Output current (leakage)
±10
µA
IPPS
VPP standby current (standby)
IPPL
VPP supply current (reset / deep
power-down mode)
IPP1
VPP supply current (active read)
VCC = VCC MAX,VO = 0 V to VCC MAX
3-V VCC range
VPP ≤ VCC
5-V VCC range
3-V VCC range
RP = VSS ± 0.2 V, VPP ≤ VCC
5-V VCC range
3-V VCC range
VPP ≥ VCC
5-V VCC range
5-V VPP range,
3-V VCC range
II
IPP2
IPP3
VPP supply current (active byte-write)
(see Notes 11 and 12)
VPP supply current (active word-write)
(see Notes 11 and 12)
Programming in progress
Programming in progress
POST OFFICE BOX 1443
10
5
5
200
200
25
12-V VPP range,
3-V VCC range
25
12-V VPP range,
5-V VCC range
20
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
25
12-V VPP range,
3-V VCC range
12-V VPP range,
5-V VCC range
• HOUSTON, TEXAS 77251−1443
µA
A
µA
A
µA
A
30
5-V VPP range,
5-V VCC range
NOTES: 10. DQ15/A−1 is tested for output leakage only.
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
34
15
mA
mA
25
20
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
IPP4
IPP5
ICCS
ICCL
TEST CONDITIONS
VPP supply current (block-erase)
(see Notes 11 and 12)
Block-erase in progress
VPP supply current (erase-suspend)
(see Notes 11 and 12)
30
5-V VPP range,
5-V VCC range
20
12-V VPP range,
3-V VCC range
25
12-V VPP range,
5-V VCC range
15
5-V VPP range,
3-V VCC range
200
5-V VPP range,
5-V VCC range
200
12-V VPP range,
3-V VCC range
200
12-V VPP range,
5-V VCC range
200
mA
µA
A
µA
A
3-V VCC range
1.5
5-V VCC range
2
VCC = VCC MAX,
E = RP = WP = VCC ± 0.2 V
3-V VCC range
110
CMOS-input level
5-V VCC range
130
VCC supply current
(standby)
VCC supply current (reset / deep
power-down mode)
RP = VSS ± 0.2 V; VCC = VCC MAX
VCC supply
current (active
read)
VCC supply current (active byte-write)
(see Notes 11 and 12)
0°C to 70°C
8
− 40°C to 85°C
8
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VIH
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VIH
5-V VCC range
65
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VCC
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VCC
5-V VCC range
60
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
50
VCC = VCC MAX,
Programming in progress
UNIT
mA
VCC = VCC MAX
E = RP =VIH
CMOS-input level
ICC2
MAX
TTL-input level
TTL-input level
ICC1
Block-erase suspended
MIN
5-V VPP range,
3-V VCC range
mA
µA
A
µA
A
mA
mA
12-V VPP range,
3-V VCC range
12-V VPP range,
5-V VCC range
mA
25
45
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
35
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
ICC3
ICC4
ICC5
TEST CONDITIONS
VCC supply current (active word-write)
(see Notes 11 and 12)
VCC supply current (block-erase)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
VCC = VCC MAX,
Block-erase in progress
VCC supply current (erase-suspend)
(see Notes 11 and 12)
VCC = VCC MAX, E = VIH,
Block-erase suspended
MIN
30
5-V VPP range,
3-V VCC range
50
12-V VPP range,
3-V VCC range
25
12-V VPP range,
5-V VCC range
45
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
35
12-V VPP range,
3-V VCC range
25
12-V VPP range,
5-V VCC range
30
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UNIT
mA
mA
3-V VCC range
3.3-V VCC range
5-V VCC range
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
MAX
5-V VPP range,
3-V VCC range
8
10
mA
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AEy and TMS28F400AEy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AEy 60
’28F400AEy 60
ALT.
SYMBOL
PARAMETER
3-V VCC
RANGE
MIN
MAX
5-V VCC
RANGE
MIN
UNIT
MAX
Setup time, RP low to VCC at 4.5 V MIN (to VCC at
2.7 V MIN or 3.6 V MAX) (see Note 14)
tPL5V
tPL3V
ta(DV)
tsu(DV)
Address valid to data valid
th(RP5)
th(RP3)
Hold time, VCC at 4.5 V (MIN) to RP high
tAVQV
tPHQV
t5VPH
2
2
µs
Hold time, VCC at 2.7 V (MIN) to RP high
t3VPH
2
2
µs
tsu(VCC)
Setup time, RP high to data valid
0
’28F004AEy 70
’28F400AEy 70
ALT.
SYMBOL
PARAMETER
3-V VCC
RANGE
MIN
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP low to VCC at 4.5 V
MIN (to VCC at
2.7 V MIN or 3.6 V MAX)
(see Note 14)
0
110
60
ns
800
450
ns
’28F004AEy 80
’28F400AEy 80
5-V VCC
RANGE
MIN
ns
3-V VCC
RANGE
MAX
0
MIN
MAX
0
UNIT
5-V VCC
RANGE
MIN
MAX
0
ns
Setup time, RP high to data valid
tAVQV
tPHQV
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP
high
t5VPH
2
2
2
2
µs
th(RP3)
Hold time, VCC at 2.7 V (MIN) to RP
high
t3VPH
2
2
2
2
µs
NOTES: 11.
12.
13.
14.
Address valid to data valid
tPL5V
tPL3V
MAX
0
150
70
150
80
ns
800
450
800
450
ns
Characterization data available
All ac current values are RMS unless otherwise noted.
E and G are switched low after power up.
The power supply can switch low concurrently with RP going low.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
37
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
’28F004AEy 60
’28F400AEy 60
ALT.
SYMBOL
PARAMETER
3-V VCC
RANGE
MIN
ta(A)
Access time from A0 −A17
(see Note 15)
’28F004AEy 70
’28F400AEy 70
5-V VCC
RANGE
MAX
MIN
3-V VCC
RANGE
MAX
MIN
5-V VCC
RANGE
MAX
MIN
UNIT
MAX
tAVQV
110
60
130
70
ns
110
60
130
70
ns
65
35
80
40
ns
110
60
130
70
ns
ta(E)
ta(G)
Access time from E
tc(R)
Cycle time, read
tELQV
tGLQV
tAVAV
td(E)
Delay time, E low to low-impedance
output
tELQX
0
0
0
0
ns
td(G)
Delay time, G low to low-impedance
output
tGLQX
0
0
0
0
ns
tdis(E)
Disable time, E to high-impedance
output
tEHQZ
55
25
70
30
ns
tdis(G)
Disable time, G to high-impedance
output
tGHQZ
45
25
55
30
ns
th(D)
Hold time, DQ valid from A0 −A17, E,
or G, whichever occurs first
(see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
5
5
5
5
ns
td(RP)
Output delay time from RP high
tPHQV
800
450
800
450
ns
tdis(BL)
Disable time, BYTE low to
DQ8 −DQ15 in the high-impedance
state
tFLQZ
45
25
55
30
ns
tFHQV
110
60
130
70
ns
Access time from G
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
38
POST OFFICE BOX 1443
0
0
• HOUSTON, TEXAS 77251−1443
0
0
ns
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage (commercial and extended temperature ranges) (continued)
’28F004AEy 80
’28F400AEy 80
ALT.
SYMBOL
PARAMETER
3-V VCC
RANGE
MIN
ta(A)
ta(E)
Access time from A0 −A17 (see Note 15)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
tAVQV
tELQV
Access time from E
tGLQV
tAVAV
Cycle time, read
tELQX
tGLQX
Delay time, G low to low-impedance output
Disable time, G to high-impedance output
tEHQZ
tGHQZ
th(D)
Hold time, DQ valid from A0 −A17, E, or G, whichever occurs first
(see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
td(RP)
tdis(BL)
Output delay time from RP high
Disable time, BYTE low to DQ8 −DQ15 in the high-impedance state
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
POST OFFICE BOX 1443
UNIT
5-V VCC
RANGE
MAX
MIN
MAX
150
80
ns
150
80
ns
40
ns
90
150
80
ns
0
0
ns
0
0
ns
80
30
ns
60
30
ns
0
0
ns
5
5
ns
tPHQV
tFLQZ
800
450
ns
60
30
ns
tFHQV
150
80
ns
• HOUSTON, TEXAS 77251−1443
39
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy
write/erase operations — W-controlled writes
’28F004AEy 60
’28F400AEy 60
ALT.
SYMBOL
3-V VCC
RANGE
MIN
tc( W )
tc( W )OP
Cycle time, write
tAVAV
tc( W )ERB
tc( W )ERP
Cycle time, erase operation (boot block)
tc( W )ERM
Cycle time, erase operation (main block)
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
th(RP)
Hold time, VPP from valid status register bit
th(WP)
tsu(WP)
Hold time, WP from valid status register bit
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
tsu(E)
tsu(RP)
Setup time, E before write operation
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
trec(RPHW)
Cycle time, duration of programming operation
tWHQV1
tWHQV2
Cycle time, erase operation (parameter block)
tWHQV3
tWHQV4
tPHBR
tWHAX
Hold time, A0 −A17 (see Note 15)
MIN
UNIT
MAX
110
60
ns
6
6
µs
0.3
0.3
s
0.3
0.3
s
0.6
0.6
200
s
100
ns
0
0
ns
tWHDX
tWHEH
0
0
ns
0
0
ns
tQVVL
tQVPH
tWHPL
0
0
ns
0
0
ns
0
0
ns
tELPH
tAVWH
90
50
ns
90
50
ns
tDVWH
tELWL
90
50
ns
0
0
ns
tPHHWH
tVPWH
200
100
ns
200
100
ns
90
50
ns
Pulse duration, W high
tWLWH
tWHWL
20
10
ns
Recovery time, RP high to W going low
tPHWL
800
450
ns
Hold time, E
Hold time, RP at VHH from valid status register bit
Setup time, WP before write operation
Setup time, DQ
Setup time, RP at VHH to W going high
Pulse duration, W low
NOTE 15: A−1 −A17 for byte-wide
40
MAX
5-V VCC
RANGE
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy (continued)
write/erase operations — W-controlled writes
’28F004AEy 70
’28F400AEy 70
ALT.
SYMBOL
3.0-V VCC
RANGE
MIN
tc( W )
Cycle time, write
tc( W )OP
Cycle time, duration of
programming operation
tc( W )ERB
MAX
5-V VCC
RANGE
MIN
MAX
3.0-V VCC
RANGE
MIN
MAX
5-V VCC
RANGE
MIN
UNIT
MAX
130
70
150
80
ns
tWHQV1
6
6
6
6
µs
Cycle time, erase operation (boot
block)
tWHQV2
0.3
0.3
0.3
0.3
s
tc( W )ERP
Cycle time, erase operation
(parameter block)
tWHQV3
0.3
0.3
0.3
0.3
s
tc( W )ERM
Cycle time, erase operation
(main block)
tWHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
tAVAV
’28F004AEy80
’28F400AEy80
0
0
0
0
ns
Hold time, DQ valid
tPHBR
tWHAX
tWHDX
0
0
0
0
ns
Hold time, E
tWHEH
0
0
0
0
ns
th( VPP)
Hold time, VPP from valid status
register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH from valid
status register bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid status
register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before write
operation
tELPH
105
50
120
50
ns
tsu(A)
Setup time, A0 −A17
(see Note 15)
tAVWH
105
50
120
50
ns
tsu(D)
Setup time, DQ
tDVWH
105
50
120
50
ns
tsu(E)
Setup time, E before write
operation
tELWL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to W
going high
tPHHWH
200
100
200
100
ns
200
100
200
100
ns
105
50
120
50
ns
25
20
30
30
ns
800
450
800
450
ns
Hold time, A0 −A17 (see Note 15)
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
Pulse duration, W high
tVPWH
tWLWH
tWLWL
trec(RPHW)
Recovery time, RP high to W
going low
tPHWL
Pulse duration, W low
200
100
200
100
ns
NOTE 15: A−1 −A17 for byte-wide
POST OFFICE BOX 1443
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41
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy
write/erase operations — E-controlled writes
’28F004AEy 60
’28F400AEy 60
ALT.
SYMBOL
3-V VCC
RANGE
MIN
tc( E )
tc(E)OP
Cycle time, write
tAVAV
tc(E)ERB
tc(E)ERP
Cycle time, erase operation (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 −A17 (see Note 15)
th( W )
th (VPP)
Hold time, W
th(RP)
th(WP)
Hold time, RP at VHH from valid status-register bit
tsu(WP)
tsu(A)
Setup time, WP before write operation
tsu(D)
tsu( W )
tsu(RP)
tsu( VPP)2
Setup time, RP at VHH to E going high
tw(E)
tw( EH)
Pulse duration, E low
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Delay time, boot-block relock
tEHQV3
tEHQV4
tPHBR
tEHAX
MIN
UNIT
MAX
110
60
ns
6
6
µs
0.3
0.3
s
0.3
0.3
s
0.6
0.6
200
s
100
ns
0
0
ns
tEHDX
tEHWH
tQVVL
0
0
ns
0
0
ns
0
0
ns
tQVPH
tWHPL
0
0
ns
0
0
ns
90
50
ns
90
50
ns
Setup time, DQ
tELPH
tAVEH
tDVEH
90
50
ns
Setup time, W before write operation
tWLEL
0
0
ns
tPHHEH
tVPEH
200
100
ns
200
100
ns
tELEH
tEHEL
90
50
ns
20
10
ns
tPHEL
800
450
ns
Hold time, DQ valid
Hold time, VPP from valid status-register bit
Hold time, WP from valid status register bit
Setup time, A0 −A17 (see Note 15)
Setup time, VPP to E going high
Pulse duration, E high
trec(RPHE) Recovery time, RP high to E going low
NOTE 15: A−1 −A17 for byte-wide
42
tEHQV1
tEHQV2
MAX
5-V VCC
RANGE
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy (continued)
write/erase operations — E-controlled writes
’28F004AEy70
’28F400AEy70
ALT.
SYMBOL
3-V VCC
RANGE
MIN
tc( E )
Cycle time, write
tc(E)OP
Cycle time, duration of
programming operation
tc(E)ERB
MAX
5-V VCC
RANGE
MIN
MAX
3-V VCC
RANGE
MIN
MAX
5-V VCC
RANGE
MIN
UNIT
MAX
130
70
150
80
ns
tEHQV1
6
6
6
6
µs
Cycle time, erase operation (boot
block)
tEHQV2
0.3
0.3
0.3
0.3
s
tc(E)ERP
Cycle time, erase operation
(parameter block)
tEHQV3
0.3
0.3
0.3
0.3
s
tc(E)ERM
Cycle time, erase operation (main
block)
tEHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th( W )
Hold time, DQ valid
tAVAV
’28F004AEy80
’28F400AEy80
tPHBR
tEHAX
200
100
200
100
ns
0
0
0
0
ns
0
0
0
0
ns
Hold time, W
tEHDX
tEHWH
0
0
0
0
ns
th (VPP)
Hold time, VPP from valid
status-register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH from valid
status-register bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid status
register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before write
operation
tELPH
105
50
120
50
ns
105
50
120
50
ns
Setup time, DQ
tAVEH
tDVEH
105
50
120
50
ns
tsu( W )
Setup time, W before write
operation
tWLEL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to E going
high
tPHHEH
200
100
200
100
ns
tsu(A)
tsu(D)
Hold time, A0 −A17 (see Note 15)
Setup time, A0 −A17 (see Note 15)
tsu( VPP)2
tw(E)
Setup time, VPP to E going high
tVPEH
tELEH
200
100
200
100
ns
Pulse duration, E low
105
50
120
50
ns
tw( EH)
Pulse duration, E high
tEHEL
25
20
30
30
ns
trec(RPHE)
Recovery time, RP high to E going
low
tPHEL
800
450
800
450
ns
NOTE 15: A−1 −A17 for byte-wide
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
TMS28F004AMy and TMS28F400AMy
The TMS28F004AMy and the TMS28F400AMy configurations offer a 3-V or 5-V memory read with a 12-V
program and erase. This configuration is intended for low 3.3-V reads and the fast programming offered with
the 12-V VPP = 12 V and 5-V VCC. This configuration is offered in two different temperature ranges: 0°C to 70°C
and − 40°C to 85°C.
recommended operating conditions for TMS28F004AMy and TMS28F400AMy
VCC
Supply voltage
VPP
Supply voltage
During write/read/erase/erase suspend
During read only ( VPPL )
During write/erase/erase suspend
3.3-V VCC range
5-V VCC range
VPPL
12-V VPP range
TTL
VIH
High-level dc
input voltage
3.3 V VCC range
CMOS
VIL
3.3 V VCC range
CMOS
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase
TA
Operating free-air temperature
3
3.3
3.6
4.5
5
5.5
0
CMOS
CMOS
UNIT
V
6.5
11.4
12
V
12.6
VCC + 0.5
VCC + 0.2
VCC + 0.3
VCC + 0.2
VCC − 0.2
− 0.5
TTL
5 V VCC range
MAX
VCC − 0.2
2
TTL
Low-level dc input
voltage
NOM
2
TTL
5 V VCC range
MIN
0.8
VSS − 0.2
− 0.3
VSS + 0.2
0.8
VSS − 0.2
2
VSS + 0.2
11.4
V
V
V
12
13
V
0
1.5
V
L Suffix
0
70
E Suffix
− 40
85
°C
NOTE 7: Mimimum value at TA = 25°C.
word/byte typical write and block-erase performance for TMS28F004AMy and TMS28F400AMy
(see Notes 8 and 9)
12-V VPP RANGE
3.3-V VCC
RANGE
PARAMETER
MIN
TYP
5-V VCC RANGE
MAX
MIN
TYP
MAX
Main block-erase time
1.3
1.1
14
Main block-byte program time
1.6
1.2
4.2
Main block-word program time
0.8
0.6
2.1
Parameter/ boot-block erase time
0.44
0.34
7
NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions.
9. Excludes system-level overhead (all times in seconds)
44
POST OFFICE BOX 1443
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TTL
VOH
High-level dc output voltage
VOL
VID
Low-level dc output voltage
CMOS
VCC = VCC MIN, IOH = − 2.5 mA
VCC = VCC MIN, IOH = − 100 µA
MAX
UNIT
2.4
V
VCC − 0.4
VCC = VCC MIN, IOL = 5.8 mA
During read algorithm-selection mode
A9 selection code voltage
MIN
11.4
0.45
V
12.6
V
±1
µA
Input current (leakage), except for A9
when A9 = VID (see Note 10)
VCC = VCC MAX, VI = 0 V to VCCMAX, RP = VHH
IID
IRP
A9 selection code current
A9 = VID
500
µA
RP boot-block unlock current
RP = VHH
500
µA
IO
Output current (leakage)
±10
µA
IPPS
VPP standby current (standby)
IPPL
VPP supply current (reset / deep
power-down mode)
200
IPP1
VPP supply current (active read)
IPP2
VPP supply current (active byte-write)
(see Notes 11 and 12)
VCC = VCCMAX,VO = 0 V to VCCMAX
3.3-V VCC range
VPP ≤ VCC
5-V VCC range
3.3-V VCC range
RP = VSS ± 0.2 V, VPP ≤ VCC
5-V VCC range
3.3-V VCC range
VPP ≥ VCC
5-V VCC range
12-V VPP range,
3.3-V VCC range
Programming in progress
12-V VPP range,
5-V VCC range
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
20
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
15
12-V VPP range,
3.3-V VCC range
200
12-V VPP range,
5-V VCC range
200
1.5
mA
2
mA
II
IPP3
IPP4
IPP5
ICCS
ICCL
VPP supply current (active word-write)
(see Notes 11 and 12)
VPP supply current (block-erase)
(see Notes 11 and 12)
Block-erase in progress
VPP supply current (erase-suspend)
(see Notes 11 and 12)
VCC supply current (standby)
VCC supply current (reset / deep
power-down mode)
Programming in progress
Block-erase suspended
15
10
5
5
200
µA
A
µA
A
µA
A
25
mA
20
mA
mA
A
µA
TTLinput
level
VCC = VCC MAX,
E = RP =VIH
3.3-V VCC range
CMOSinput
level
VCC = VC CMAX,
E = RP = VCC± 0.2 V
3.3-V VCC range
110
µA
5-V VCC range
130
µA
RP = VSS ± 0.2 V; VCC = VCC
MAX
0°C to 70°C
8
− 40°C to 85°C
8
5-V VCC range
µA
NOTES: 10. DQ15/A−1 is tested for output leakage only.
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
POST OFFICE BOX 1443
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45
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TTL-input level
ICC1
VCC supply
current (active
read)
CMOS-input level
ICC2
ICC3
ICC4
ICC5
MAX
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VIH
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VIH
5-V VCC range
65
E = VIL, IOUT = 0 mA, f = 5 MHz,
G = VCC
3.3-V VCC range
30
E = VIL, IOUT = 0 mA, f = 10 MHz,
G = VCC
5-V VCC range
60
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
45
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
45
12-V VPP range,
3.3-V VCC range
25
12-V VPP range,
5-V VCC range
30
VCC supply current (active byte-write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
VCC supply current (active word-write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
VCC supply current (block-erase)
(see Notes 11 and 12)
VCC = VCC MAX,
Block-erase in progress
VCC supply current (erase-suspend)
(see Notes 11 and 12)
VCC = VCC MAX, E = VIH,
Block-erase suspended
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
46
MIN
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UNIT
mA
mA
3.3-V VCC range
5-V VCC range
mA
mA
mA
8
10
mA
Hold time, VCC at 4.5 V (MIN) to RP
high
Setup time, RP high to data valid
Address valid to data valid
t5VPH
tAVQV
tPHQV
tPL5V
tPL3V
ALT.
SYMBOL
2
0
110
800
2
2
0
450
60
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
th(RP3)
Hold time, VCC at 3 V (MIN) to RP high
t3VPH
2
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13 E and G are switched low after power up.
14 The power supply can switch low concurrently with RP going low.
th(RP5)
ta(DV)
tsu(DV)
tsu(VCC)
Setup time, RP low to VCC at
4.5 V MIN (to VCC at 3 V MIN or
3.6 V MAX) (see Note 14)
PARAMETER
’28F004AMy 60
’28F400AMy 60
2
2
0
MIN
800
130
MAX
3.3-V VCC
RANGE
2
2
0
MIN
450
70
MAX
5-V VCC
RANGE
’28F004AMy 70
’28F400AMy 70
2
2
0
MIN
800
150
MAX
3.3-V VCC
RANGE
2
2
0
MIN
450
80
MAX
5-V VCC
RANGE
’28F004AMy 80
’28F400AMy 80
µs
µs
ns
ns
ns
UNIT
power-up and reset switching characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of supply
voltage (commercial and extended temperature ranges)(see Notes 11, 12, and 13)
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
47
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tGLQX
tEHQZ
tGHQZ
tAXQX
tPHQV
tFLQZ
Delay time, E low to low-impedance
output
Delay time, G low to low-impedance
output
Disable time, E to high-impedance
output
Disable time, G to high-impedance
output
Hold time, DQ valid from A0 −A17, E, or
G, whichever occurs first
(see Note 15)
Setup time, BYTE from E low
Output delay time from RP high
Disable time, BYTE low to DQ8 −DQ15
in high-impedance state
td(E)
td(G)
tdis(E)
tdis(G)
th(D)
tsu(EB)
td(RP)
tdis(BL)
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
tELQX
Cycle time, read
tc(R)
tFHQV
tELFL
tELFH
tELQV
tGLQV
tAVAV
Access time from G
Access time from E
tAVQV
Access time from A0 −A17
(see Note 15)
ta(E)
ta(G)
ta(A)
ALT.
SYMBOL
PARAMETER
read operations
0
0
0
110
110
45
800
5
45
55
65
110
110
0
0
0
60
60
25
450
5
25
25
35
60
60
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004AMy 60
’28F400AMy 60
0
0
0
130
MIN
130
55
800
5
55
70
80
130
130
MAX
3.3-V VCC
RANGE
0
0
0
70
MIN
70
30
450
5
30
30
40
70
70
MAX
5-V VCC
RANGE
’28F004AMy 70
’28F400AMy 70
0
0
0
150
MIN
150
60
800
5
60
80
90
150
150
MAX
3.3-V VCC
RANGE
0
0
0
80
MIN
80
30
450
5
30
30
40
80
80
MAX
5-V VCC
RANGE
28F004AMy 80
’28F400AMy 80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
switching characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of supply voltage
(commercial and extended temperature ranges)
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
tWHQV4
tPHBR
tWHAX
Cycle time, erase operation
(main block)
Delay time, boot-block relock
Hold time, A0 −A17
(see Note 15)
tc( W )ERP
tc( W )ERM
td(RPR)
th(A)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tQVPH
tAVWH
tDVWH
tELWL
Hold time, RP at VHH from
valid status register bit
Setup time, A0 −A17
(see Note 15)
Setup time, DQ
Setup time, E before write
operation
th( VPP)
th(RP)
tsu(A)
tsu(D)
tsu(E)
NOTE 15: A−1 −A17 for byte-wide
tQVVL
Hold time, VPP from valid
status register bit
Hold time, E
tWHDX
tWHEH
tWHQV3
Cycle time, erase operation
(parameter block)
tc( W )ERB
Hold time, DQ valid
tWHQV2
Cycle time, erase operation
(boot block)
tc( W )OP
th(D)
th(E)
tWHQV1
Cycle time, duration of
programming operation
tAVAV
Cycle time, write
tc( W )
ALT.
SYMBOL
write/erase operations — W-controlled writes
0
90
90
0
0
0
0
0
0.6
0.3
0.3
6
200
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
60
100
MAX
MIN
MAX
MIN
110
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004AMy 60
’28F400AMy 60
timing requirements for TMS28F004AMy and TMS28F400AMy
0
105
105
0
0
0
0
0
0.6
0.3
0.3
6
130
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
70
MIN
100
MAX
5-V VCC
RANGE
’28F004AMy 70
’28F400AMy70
0
120
120
0
0
0
0
0
0.6
0.3
0.3
6
150
MIN
200
MAX
3.3-V VCC
RANGE
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
80
MIN
100
MAX
5-V VCC
RANGE
28F004AMy 80
’28F400AMy80
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
µs
ns
UNIT
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
49
50
Recovery time, RP high to W
going low
NOTE 15: A−1 −A17 for byte-wide
trec(RPHW)
Pulse duration, W high
tPHWL
tWLWH
tWHWL
tsu( VPP)1
Pulse duration, W low
tVPWH
Setup time, VPP to W going
high
tsu(RP)
tw( W )
tw( WH)
tPHHWH
Setup time, RP at VHH to W
going high
ALT.
SYMBOL
write/erase operations — W-controlled writes
800
20
90
200
200
450
10
50
100
100
MAX
MIN
MIN
MAX
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004AMy 60
’28F400AMy 60
800
25
105
200
200
MIN
MAX
3.3-V VCC
RANGE
450
20
50
100
100
MIN
MAX
5-V VCC
RANGE
’28F004AMy 70
’28F400AMy70
timing requirements for TMS28F004AMy and TMS28F400AMy (continued)
800
30
120
200
200
MIN
MAX
3.3-V VCC
RANGE
450
30
50
100
100
MIN
MAX
5-V VCC
RANGE
28F004AMy 80
’28F400AMy80
ns
ns
ns
ns
ns
UNIT
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tEHQV3
tEHQV4
Cycle time, erase operation
(parameter block)
Cycle time, erase operation (main
block)
tc(E)ERB
tc(E)ERP
tc(E)ERM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
tPHEL
Recovery time, RP high to E going
low
trec(RPHE)
NOTE 15: A−1 −A17 for byte-wide
tEHEL
Pulse duration, E high
tw( EH)
tVPEH
tELEH
Pulse duration, E low
Setup time, RP at VHH to E going
high
tsu(RP)
Setup time, VPP to E going high
tPHHEH
Setup time, W before write operation
tsu( VPP)2
tw(E)
tWLEL
Setup time, DQ
tAVEH
tDVEH
tsu( W )
Setup time, A0 −A17 (see Note 15)
tQVPH
Hold time, RP at VHH from valid
status-register bit
th(RP)
tsu(A)
tsu(D)
tQVVL
tEHDX
tEHWH
th (VPP)
Hold time, W
Hold time, DQ valid
Hold time, VPP from valid
status-register bit
th(D)
th( W )
Hold time, A0 −A17 (see Note 15)
tPHBR
tEHAX
tEHQV2
Cycle time, erase operation (boot
block)
tc(E)OP
Delay time, boot-block relock
tEHQV1
Cycle time, duration of programming
operation
td(RPR)
th(A)
tAVAV
Cycle time, write
tc( E )
ALT.
SYMBOL
write/erase operations — E-controlled writes
800
20
90
200
200
0
90
90
0
0
0
0
0
0.6
0.3
0.3
6
200
450
10
50
100
100
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
60
100
MAX
MIN
MAX
MIN
110
5-V VCC
RANGE
3.3-V VCC
RANGE
’28F004AMy 60
’28F400AMy 60
timing requirements for TMS28F004AMy and TMS28F400AMy
800
25
105
200
200
0
105
105
0
0
0
0
0
0.6
0.3
0.3
6
130
MIN
200
MAX
3.3-V VCC
RANGE
450
20
50
100
100
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
70
MIN
100
MAX
5-V VCC
RANGE
’28F004AMy 70
’28F400AMy70
800
30
120
200
200
0
120
120
0
0
0
0
0
0.6
0.3
0.3
6
150
MIN
200
MAX
3.3-V VCC
RANGE
450
30
50
100
100
0
50
50
0
0
0
0
0
0.6
0.3
0.3
6
80
MIN
100
MAX
5-V VCC
RANGE
28F004AMy 80
’28F400AMy80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
µs
ns
UNIT
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
51
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
TMS28F004AFy and TMS28F400AFy
The TMS28F004AFy and the TMS28F400AFy configurations offer a 5-V memory read with a 5-V or 12-V
program and erase. This configuration is intended for systems using a single 5-V power supply and it is offered
in three temperature ranges: 0°C to 70°C, − 40°C to 85°C, and − 40°C to 125°C.
recommended operating conditions for TMS28F004AFy and TMS28F400AFy
VCC
VPP
Supply voltage
Supply voltage
MIN
NOM
MAX
5
5.5
During write/read/erase/erase suspend
5-V VCC range
4.5
During read only ( VPPL )
VPPL
5-V VPP range
0
4.5
5
5.5
12-V VPP range
11.4
12
12.6
During write/erase/erase suspend
TTL
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase
TA
Operating free-air temperature
CMOS
TTL
CMOS
V
6.5
2
VCC + 0.3
VCC + 0.2
VCC − 0.2
− 0.3
V
V
0.8
VSS − 0.2
2
11.4
UNIT
VSS + 0.2
V
V
12
13
V
0
1.5
V
L Suffix
0
70
E Suffix
− 40
85
Q Suffix
− 40
125
°C
°C
NOTE 7: Mimimum value at TA = 25°C.
word/byte typical write and block-erase performance for TMS28F004AFy and TMS28F400AFy
(see Notes 8 and 9)
PARAMETER
5-V VPP AND
5-V VCC RANGES
MIN
TYP
MAX
TYP
MAX
Main block erase time
1.9
1.1
14
Main block byte-program time
1.4
1.2
4.2
Main block word-program time
0.9
0.6
2.1
Parameter/ boot-block erase time
0.8
0.34
7
NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions.
9. Excludes system-level overhead (all times in seconds)
52
12-V VPP AND
5-V VCC RANGES
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MIN
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
VOH
VOL
VID
High-level dc
output voltage
TEST CONDITIONS
TTL
VCC = VCC MIN, IOH = − 2.5 mA
VCC = VCC MIN, IOH = − 100 µA
CMOS
Low-level dc output voltage
MAX
UNIT
2.4
V
VCC − 0.4
VCC = VCC MIN, IOL = 5.8 mA
During read algorithm-selection mode
A9 selection code voltage
MIN
11.4
0.45
V
12.6
V
±1
µA
Input current (leakage), except for A9
when A9 = VID (see Note 10)
VCC = VCC MAX, VI = 0 V to VCC MAX, RP = VHH
IID
IRP
A9 selection code current
A9 = VID
500
µA
RP boot-block unlock current
RP = VHH
500
µA
IO
IPPS
Output current (leakage)
VCC = VCC MAX, VO = 0 V to VCC MAX
VPP ≤ VCC
5-V VCC range
±10
µA
10
µA
II
IPPL
VPP standby current (standby)
VPP supply current (reset / deep
power-down mode)
IPP1
VPP supply current (active read)
IPP2
VPP supply current (active byte-write)
(see Notes 11 and 12)
IPP3
IPP4
IPP5
ICCS
VPP supply current (active word-write)
(see Notes 11 and 12)
VPP supply current (block-erase)
(see Notes 11 and 12)
5-V VCC range
5
µA
VPP ≥ VCC
5-V VCC range
200
µA
5-V VPP range,
5-V VCC range
25
12-V VPP range,
5-V VCC range
20
5-V VPP range,
5-V VCC range
25
12-V VPP range,
5-V VCC range
20
5-V VPP range,
5-V VCC range
20
12-V VPP range,
5-V VCC range
15
5-V VPP range,
5-V VCC range
200
12-V VPP range,
5-V VCC range
200
Programming in progress
Programming in progress
Block-erase in progress
VPP supply current (erase-suspend)
(see Notes 11 and 12)
VCC supply current
(standby)
RP = VSS ± 0.2 V, VPP ≤ VCC
Block-erase suspended
TTL-input level
CMOS-input level
VCC = VCC MAX, E = RP = VIH
ICC1
VCC supply current (reset / deep
power-down mode)
VCC supply current
(active read)
RP = VSS ± 0.2 V
mA
mA
A
µA
5-V VCC range
2
mA
5-V VCC range
130
µA
0°C to 70°C
ICCL
mA
8
− 40°C to 85°C
8
− 40°C to 125°C
40
µA
TTL-input level
E = VIL, IOUT = 0 mA,
f = 10 MHz, G = VIH
5-V VCC range
65
mA
CMOS-input level
E = VSS, IOUT = 0 mA,
f = 10 MHz, G = VCC
5-V VCC range
60
mA
NOTES: 10. DQ15/A−1 is tested for output leakage only.
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
53
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
ICC2
ICC3
ICC4
ICC5
TEST CONDITIONS
VCC supply current (active byte-write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
VCC supply current (active word-write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
VCC supply current (block-erase)
(see Notes 11 and 12)
VCC = VCC MAX
VPP = 12 V or 5 V
Block-erase in progress
VCC supply current (erase-suspend)
(see Notes 11 and 12)
VCC = VCC MAX, E = VIH,
Block-erase suspended
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MIN
MAX
5-V VPP range,
5-V VCC range
50
12-V VPP range,
5-V VCC range
45
5-V VPP range,
5-V VCC range
50
12-V VPP range,
5-V VCC range
45
5−V VPP range,
5-V VCC range
35
12-V VPP range,
5-V VCC range
30
5-V VCC range
10
UNIT
mA
mA
mA
mA
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AFy and TMS28F400AFy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AFy 60
’28F400AFy 60
’28F004AFy 70
’28F400AFy 70
’28F004AFy 80
’28F400AFy 80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
ALT.
SYMBOL
PARAMETER
MIN
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP low to VCC at 4.5 V MIN (see
Note 14)
tPL5V
tPL3V
Address valid to data valid
tAVQV
tPHQV
t5VPH
Setup time, RP high to data valid
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP high
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
MAX
0
MIN
MAX
0
MIN
UNIT
MAX
0
ns
60
70
80
ns
450
450
450
ns
2
2
µs
2
power-up and reset switching characteristics for TMS28F400AFy over recommended ranges of
supply voltage (automotive temperature range) (see Notes 11, 12, 13)
PARAMETER
ALT.
SYMBOL
Setup time, RP low to VCC at 4.5 V MIN
(see Note 14)
tPL5V
tPL3V
Address valid to data valid
tAVQV
tPHQV
’28F004AFy 70
’28F400AFy70
’28F004AFy 80
’28F400AFy80
’28F004AFy 90
’28F400AFy90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP high to data valid
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP high
t5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
POST OFFICE BOX 1443
MAX
0
MIN
MAX
0
70
• HOUSTON, TEXAS 77251−1443
ns
90
450
2
MAX
0
80
450
2
MIN
UNIT
450
2
ns
ns
µs
55
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
ALT.
SYMBOL
PARAMETER
’28F004AFy 60
’28F400AFy 60
’28F004AFy 70
’28F400AFy 70
’28F004AFy 80
’28F400AFy 80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
ta(A)
ta(E)
Access time from A0 −A17 (see Note 15)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
Access time from E
tAVQV
tELQV
tGLQV
tAVAV
Cycle time, read
Delay time, G low to low-impedance output
tELQX
tGLQX
MAX
MIN
MAX
MIN
UNIT
MAX
60
70
80
ns
60
70
80
ns
40
ns
35
40
60
70
80
ns
0
0
0
ns
0
0
0
ns
Disable time, G to high-impedance output
tEHQZ
tGHQZ
th(D)
Hold time, DQ valid from A0 −A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
5
5
5
ns
td(RP)
Output delay time from RP high
tPHQV
450
450
450
ns
tdis(BL)
Disable time, BYTE low to DQ8 −DQ15 in
high-impedance state
tFLQZ
25
30
30
ns
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
tFHQV
60
70
80
ns
56
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 1443
25
30
30
ns
25
30
30
ns
0
0
0
ns
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F400AFy over recommended ranges of supply voltage
(automotive temperature range)
read operations
ALT.
SYMBOL
PARAMETER
’28F400AFy 70
’28F400AFy 70
’28F400AFy 80
’28F400AFy 80
’28F004AFy 90
’28F400AFy 90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
ta(A)
ta(E)
Access time from A0 −A17 (see Note 15)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
Access time from E
tAVQV
tELQV
tGLQV
tAVAV
Cycle time, read
Delay time, G low to low-impedance output
tELQX
tGLQX
MAX
MIN
MAX
MIN
UNIT
MAX
70
80
90
ns
70
80
90
ns
45
ns
35
40
70
80
90
ns
0
0
0
ns
0
0
0
ns
Disable time, G to high-impedance output
tEHQZ
tGHQZ
th(D)
Hold time, DQ valid from A0 −A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
5
5
5
ns
td(RP)
Output delay time from RP high
tPHQV
300
300
300
ns
tdis(BL)
Disable time, BYTE low to DQ8 −DQ15 in
high-impedance state
tFLQZ
30
30
35
ns
tFHQV
70
80
90
ns
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
POST OFFICE BOX 1443
25
30
35
ns
25
30
35
ns
0
0
• HOUSTON, TEXAS 77251−1443
0
ns
57
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AFy (commercial and extended temperature ranges)
write/erase operations — W-controlled writes
ALT.
SYMBOL
’28F004AFy 60
’28F400AFy 60
’28F004AFy 70
’28F400AFy70
’28F004AFy 80
’28F400AFy80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( W )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
60
70
80
ns
tc( W )OP
Cycle time, duration of programming
operation
tWHQV1
6
6
6
µs
tc( W )ERB
Cycle time, erase operation (boot block)
tWHQV2
0.3
0.3
0.3
s
tc( W )ERP
Cycle time, erase operation (parameter
block)
tWHQV3
0.3
0.3
0.3
s
tc( W )ERM
Cycle time, erase operation (main block)
tWHQV4
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
Hold time, VPP from valid status-register bit
th(RP)
Hold time, RP at VHH from valid
status-register bit
tPHBR
tWHAX
tWHDX
Hold time, A0 −A17 (see Note 15)
ns
ns
0
0
0
ns
tWHEH
tQVVL
0
0
0
ns
0
0
0
ns
tQVPH
0
0
0
ns
tWHPL
tELPH
0
0
0
ns
50
50
50
ns
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHWH
tVPWH
100
100
100
ns
100
100
100
ns
50
50
50
ns
10
20
30
ns
450
450
450
ns
Hold time, WP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
Setup time, DQ
tAVWH
tDVWH
tsu(E)
tsu(RP)
Setup time, E before write operation
tELWL
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
trec(RPHW)
Pulse duration, W high
tWLWH
tWHWL
Recovery time, RP high to W going low
tPHWL
Setup time, WP before write operation
NOTE 15: A−1 −A17 for byte-wide
58
100
0
th(WP)
tsu(WP)
Pulse duration, W low
100
0
Hold time, E
Setup time, RP at VHH to W going high
100
0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AFy (automotive temperature range)
write/erase operations — W-controlled writes (continued)
ALT.
SYMBOL
’28F004AFy 70
’28F400AFy 70
’28F004AFy 80
’28F400AFy 80
’28F004AFy 90
’28F400AFy 90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( W )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
70
80
90
ns
tc( W )OP
Cycle time, duration of programming
operation
tWHQV1
6
6
7
µs
tc( W )ERB
Cycle time, erase operation (boot block)
tWHQV2
0.3
0.3
0.4
s
tc( W )ERP
Cycle time, erase operation (parameter
block)
tWHQV3
0.3
0.3
0.4
s
tc( W )ERM
Cycle time, erase operation (main block)
tWHQV4
0.6
0.6
0.4
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
Hold time, VPP from valid status-register bit
th(RP)
Hold time, RP at VHH from valid
status-register bit
Hold time, A0 −A17 (see Note 15)
Hold time, E
tPHBR
tWHAX
tWHDX
ns
ns
0
0
0
ns
tWHEH
tQVVL
0
0
0
ns
0
0
0
ns
tQVPH
0
0
0
ns
tWHPL
tELPH
0
0
0
ns
50
50
50
ns
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHWH
tVPWH
100
100
100
ns
100
100
100
ns
60
60
60
ns
20
30
40
ns
220
220
220
ns
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
Setup time, DQ
tAVWH
tDVWH
tsu(E)
tsu(RP)
Setup time, E before write operation
tELWL
tsu( VPP)1
tw( W )
Setup time, VPP to W switching high
tw( WH)
trec(RPHW)
Pulse duration, W high
tWLWH
tWHWL
Recovery time, RP high to W going low
tPHWL
Pulse duration, W low
100
0
Hold time, WP from valid status-register bit
Setup time, RP at VHH to W switching high
100
0
th(WP)
tsu(WP)
Setup time, WP before write operation
100
0
NOTE 15: A−1 −A17 for byte-wide
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
59
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AFy (commercial and extended temperature ranges)
write/erase operations — E-controlled writes
ALT.
SYMBOL
’28F004AFy 60
’28F400AFy 60
’28F004AFy70
’28F400AFy70
’28F004AFy80
’28F400AFy80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( E )
tc(E)OP
Cycle time, write
tc(E)ERB
tc(E)ERP
Cycle time, erase operation (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 −A17 (see Note 15)
th( W )
th (VPP)
Hold time, W
th(RP)
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
60
70
80
ns
tEHQV1
tEHQV2
6
6
6
µs
0.3
0.3
0.3
s
0.3
0.3
0.3
s
tEHQV3
tEHQV4
Delay time, boot-block relock
tPHBR
tEHAX
0.6
0.6
100
0.6
100
s
100
ns
0
0
0
ns
0
0
0
ns
0
0
0
ns
Hold time, VPP from valid status-register bit
tEHDX
tEHWH
tQVVL
0
0
0
ns
Hold time, RP at VHH from valid status-register
bit
tQVPH
0
0
0
ns
tWHPL
tELPH
0
0
0
ns
50
50
50
ns
tAVEH
tDVEH
tWLEL
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHEH
tVPEH
100
100
100
ns
100
100
100
ns
Hold time, DQ valid
th(WP)
tsu(WP)
Hold time, WP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
tsu( W )
tsu(RP)
Setup time, W before write operation
tsu( VPP)2
tw(E)
Setup time, VPP to E going high
50
50
ns
Pulse duration, E high
tELEH
tEHEL
50
tw( EH)
trec(RPHE)
10
20
30
ns
Recovery time, RP high to E going low
tPHEL
450
450
450
ns
Setup time, WP before write operation
Setup time, DQ
Setup time, RP at VHH to E going high
Pulse duration, E low
NOTE 15: A−1 −A17 for byte-wide
60
POST OFFICE BOX 1443
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AFy (automotive temperature range)
write/erase operations — E-controlled writes (continued)
ALT.
SYMBOL
’28F004AFy 70
’28F400AFy 70
’28F004AFy 80
’28F400AFy 80
’28F004AFy 90
’28F400AFy 90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( E )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
70
80
90
ns
tc(E)OP
Cycle time, duration of programming
operation
tEHQV1
6
6
7
µs
tc(E)ERB
Cycle time, erase operation (boot block)
tEHQV2
0.3
0.3
0.4
s
tc(E)ERP
Cycle time, erase operation (parameter
block)
tEHQV3
0.3
0.3
0.4
s
tEHQV4
tPHBR
0.6
tEHAX
tEHDX
tEHWH
0
0
0
ns
0
0
0
ns
0
0
0
ns
Hold time, VPP from valid status-register bit
tQVVL
0
0
0
ns
Hold time, RP
status-register bit
tQVPH
0
0
0
ns
tWHPL
tELPH
0
0
0
ns
50
50
50
ns
50
50
50
ns
50
50
50
ns
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 −A17 (see Note 15)
th( W )
th (VPP)
Hold time, W
th(RP)
Delay time, boot-block relock
Hold time, DQ valid
at
VHH
from
valid
th(WP)
tsu(WP)
Hold time, WP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
tsu( W )
tsu(RP)
Setup time, W before write operation
tsu( VPP)2
tw(E)
Setup time, VPP to E going high
tw( EH)
trec(RPHE)
Setup time, WP before write operation
Setup time, DQ valid
Setup time, RP at VHH to E going high
tAVEH
tDVEH
tWLEL
tPHHEH
tVPEH
0.6
100
0.7
100
s
100
ns
0
0
0
ns
100
100
50
ns
100
100
50
ns
60
60
60
ns
Pulse duration, E high
tELEH
tEHEL
20
30
40
ns
Recovery time, RP high to E going low
tPHEL
300
300
300
ns
Pulse duration, E low
NOTE 15: A−1 −A17 for byte-wide
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
TMS28F004AZy and TMS28F400AZy
The TMS28F004AZy and the TMS28F400AZy configurations offer a 5-V memory read with a 12-V program and
a 12-V erase for fast programming and erasing times. This configuration is offered in three temperature ranges:
0°C to 70°C, − 40°C to 85°C, and − 40°C to 125°C.
recommended operating conditions for TMS28F004AZy and TMS28F400AZy
VCC
Supply voltage
During write/read/erase/erase suspend
5-V VCC range
During read only
VPPL
12-V VPP range
VPP
Supply voltage
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase
TA
Operating free-air temperature
During write/erase/erase suspend
MIN
NOM
MAX
4.5
5
5.5
0
11.4
TTL
12
TTL
V
V
0.8
VSS − 0.2
2
11.4
12.6
VCC + 0.3
VCC + 0.2
VCC − 0.2
− 0.3
CMOS
V
6.5
2
CMOS
UNIT
VSS + 0.2
V
V
13
V
0
12
1.5
V
L Suffix
0
70
E Suffix
− 40
85
Q Suffix
− 40
125
°C
°C
NOTE 7: Mimimum value at TA = 25°C.
word/byte typical write and block-erase performance for TMS28F400AZy and TMS28F400AZy
(see Notes 8 and 9)
PARAMETER
12-V VPP AND
5-V VCC RANGES
MIN
TYP
MAX
Main block-erase time
1.1
14
Main block-byte program time
1.2
4.2
Main block-word program time
0.6
2.1
Parameter/ boot-block erase time
0.34
7
NOTES: 8. Typical values shown are at TA = 25°C and nominal conditions.
9. Excludes system-level overhead (all times in seconds)
62
POST OFFICE BOX 1443
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
electrical characteristics for TMS28F004AZy and TMS28F400AZy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
VOH
VOL
VID
High-level dc
output voltage
TEST CONDITIONS
TTL
VCC = VCC MIN, IOH = − 2.5 mA
VCC = VCC MIN, IOH = − 100 µA
CMOS
MAX
UNIT
2.4
V
VCC − 0.4
A9 selection code voltage
VCC = VCC MIN, IOL = 5.8 mA
During read algorithm-selection mode
0.45
V
12.6
V
Input current (leakage), except for A9
when A9 = VID (see Note 10)
VCC = VCC MAX,
VI = 0 V to VCCMAX, RP = VHH
±1
µA
A9 selection code current
RP boot-block unlock current
A9 = VID
500
µA
RP = VHH
500
µA
VCC = VCC MAX, VO = 0 V to
VCCMAX
IO
Output current (leakage)
±10
µA
IPPS
VPP standby current (standby)
VPP supply current (reset / deep
power-down mode)
VPP ≤ VCC
5-V VCC range
10
µA
RP = VSS ± 0.2 V, VPP ≤ VCC
5-V VCC range
5
µA
IPP2
VPP supply current (active read)
VPP supply current (active byte write)
(see Notes 11 and 12)
VPP ≥ VCC
5-V VCC range
200
µA
Programming in progress
12-V VPP range,
5-V VCC range
20
mA
IPP3
VPP supply current (active word write)
(see Notes 11 and 12)
Programming in progress
12-V VPP range,
5-V VCC range
20
mA
IPP4
VPP supply current (block erase)
(see Notes 11 and 12)
Block erase in progress
12-V VPP range,
5-V VCC range
15
mA
IPP5
VPP supply current (erase suspend)
(see Notes 11 and 12)
Block erase suspended
12-V VPP range,
5-V VCC range
200
µA
VCC supply current
(standby)
2
mA
ICCS
VCC = VCC MAX, E = RP = VIH
5-V VCC range
130
µA
II
IID
IRP
IPPL
IPP1
ICCL
ICC1
Low-level dc output voltage
MIN
TTL-input level
CMOS-input level
VCC supply current (reset / deep
power-down mode)
VCC supply current
(active read)
RP = VSS ± 0.2 V
11.4
0°C to 70°C
8
− 40°C to 85°C
8
− 40°C to 125°C
40
µA
TTL-input level
E = VIL, IOUT = 0 mA,
f = 10 MHz, G = VIH
5-V VCC range
65
mA
CMOS-input level
E = VSS, IOUT = 0 mA,
f = 10 MHz, G = VCC
5-V VCC range
60
mA
ICC2
VCC supply current (active byte write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
12-V VPP range,
5-V VCC range
50
mA
ICC3
VCC supply current (active word write)
(see Notes 11 and 12)
VCC = VCC MAX,
Programming in progress
12-V VPP range,
5-V VCC range
45
mA
ICC4
VCC supply current (block erase)
(see Notes 11 and 12)
VCC = VCC MAX,
Block erase in progress
12-V VPP range,
5-V VCC range
45
mA
ICC5
VCC supply current (erase suspend)
(see Notes 11 and 12)
VCC = VCC MAX, E = VIH,
Block erase suspended
5-V VCC range
10
mA
NOTES: 10. DQ15/A−1 is tested for output leakage only.
11. Not 100% tested; characterization data available
12. All ac current values are RMS unless otherwise noted.
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AZy and TMS28F400AZy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AZy 60
’28F400AZy 60
’28F004AZy 70
’28F400AZy 70
’28F004AZy 80
’28F400AZy 80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
ALT.
SYMBOL
PARAMETER
MIN
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP low to VCC at 4.5 V MIN
(see Note 14)
tPL5V
tPL3V
Address valid to data valid
tAVQV
tPHQV
t5VPH
Setup time, RP high to data valid
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP high
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
MAX
0
MIN
MAX
0
MIN
UNIT
MAX
0
ns
60
70
80
ns
450
450
450
ns
2
2
µs
2
power-up and reset switching characteristics for TMS28F400AZy over recommended ranges of
supply voltage (automotive temperature range)
PARAMETER
ALT.
SYMBOL
Setup time, RP low to VCC at 4.5 V MIN
(see Note 14)
tPL5V
tPL3V
Address valid to data valid
tAVQV
tPHQV
’28F004AZy 70
’28F400AZy70
’28F004AZy 80
’28F400AZy80
’28F004AZy90
’28F400AZy90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP high to data valid
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP high
t5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
64
POST OFFICE BOX 1443
MAX
0
MIN
MAX
0
70
• HOUSTON, TEXAS 77251−1443
ns
90
450
2
MAX
0
80
450
2
MIN
UNIT
450
2
ns
ns
µs
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F004AZy and TMS28F400AZy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
ALT.
SYMBOL
PARAMETER
’28F004AZy 60
’28F400AZy 60
’28F004AZy 70
’28F400AZy 70
’28F004AZy 80
’28F400AZy 80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
ta(A)
ta(E)
Access time from A0 −A17 (see Note 15)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
Access time from E
tAVQV
tELQV
tGLQV
tAVAV
Cycle time, read
Delay time, G low to low-impedance output
MAX
tELQX
tGLQX
MIN
MAX
MIN
UNIT
MAX
60
70
80
ns
60
70
80
ns
40
ns
35
40
60
70
80
ns
0
0
0
ns
0
0
0
ns
Disable time, G to high-impedance output
tEHQZ
tGHQZ
th(D)
Hold time, DQ valid from A0 −A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
5
5
5
ns
td(RP)
Output delay time from RP high
tPHQV
450
450
450
ns
tdis(BL)
Disable time, BYTE low to DQ8 −DQ15 in
high-impedance state
tFLQZ
25
30
30
ns
tFHQV
60
70
80
ns
ta(BH)
Access time from BYTE going high
NOTE 15: A−1 −A17 for byte-wide
25
30
30
ns
25
30
30
ns
0
0
0
ns
switching characteristics for TMS28F400AZy over recommended ranges of supply voltage
(automotive temperature range)
read operations
ALT.
SYMBOL
PARAMETER
’28F004AZy 70
’28F400AZy 70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
ta(A)
ta(E)
Access time from A0 −A17 (see Note 15)
ta(G)
tc(R)
Access time from G
td(E)
td(G)
Delay time, E low to low-impedance output
tdis(E)
tdis(G)
Disable time, E to high-impedance output
Access time from E
Cycle time, read
Delay time, G low to low-impedance output
MAX
MIN
MAX
MIN
UNIT
MAX
tAVQV
tELQV
70
80
90
ns
70
80
90
ns
tGLQV
tAVAV
35
40
45
ns
tELQX
tGLQX
Disable time, G to high-impedance output
tEHQZ
tGHQZ
th(D)
Hold time, DQ valid from A0 −A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
70
80
90
ns
0
0
0
ns
0
0
0
ns
25
30
35
ns
25
30
35
ns
0
0
5
0
5
ns
5
ns
NOTE 15: A−1 −A17 for byte-wide
POST OFFICE BOX 1443
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
switching characteristics for TMS28F400AZy over recommended ranges of supply voltage
(automotive temperature range) (continued)
read operations
ALT.
SYMBOL
PARAMETER
’28F004AZy 70
’28F400AZy 70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
td(RP)
Output delay time from RP high
tPHQV
300
300
300
ns
tdis(BL)
Disable time, BYTE low to DQ8 −DQ15 in
high-impedance state
tFLQZ
30
30
35
ns
ta(BH)
Access time from BYTE going high
tFHQV
70
80
90
ns
timing requirements for TMS28F004AZy and TMS28F400AZy (commercial and extended
temperature ranges)
write/erase operations — W-controlled writes
ALT.
SYMBOL
’28F004AZy 60
’28F400AZy 60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( W )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
60
70
80
ns
tc( W )OP
Cycle time, duration of programming
operation
tWHQV1
6
6
6
µs
tc( W )ERB
Cycle time, erase operation (boot block)
tWHQV2
0.3
0.3
0.3
s
tc( W )ERP
Cycle time, erase operation (parameter
block)
tWHQV3
0.3
0.3
0.3
s
tc( W )ERM
Cycle time, erase operation (main block)
tWHQV4
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
Hold time, VPP from valid status-register bit
th(RP)
Hold time, RP at VHH from valid
status-register bit
tPHBR
tWHAX
tWHDX
Hold time, A0 −A17 (see Note 15)
ns
ns
0
0
0
ns
tWHEH
tQVVL
0
0
0
ns
0
0
0
ns
tQVPH
0
0
0
ns
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHWH
tVPWH
100
100
100
ns
100
100
100
ns
50
50
50
ns
10
20
30
ns
450
450
450
ns
Setup time, A0 −A17 (see Note 15)
Setup time, DQ
tAVWH
tDVWH
tsu(E)
tsu(RP)
Setup time, E before write operation
tELWL
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
trec(RPHW)
Pulse duration, W high
tWLWH
tWHWL
Recovery time, RP high to W going low
tPHWL
NOTE 15: A−1 −A17 for byte-wide
66
100
0
tsu(A)
tsu(D)
Pulse duration, W low
100
0
Hold time, E
Setup time, RP at VHH to W going high
100
0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AZy (automotive temperature range)
write/erase operations — W-controlled writes (continued)
ALT.
SYMBOL
’28F004AZy 60
’28F400AZy 60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( W )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
70
80
90
ns
tc( W )OP
Cycle time, duration of programming
operation
tWHQV1
6
6
7
µs
tc( W )ERB
Cycle time, erase operation (boot block)
tWHQV2
0.3
0.3
.4
s
tc( W )ERP
Cycle time, erase operation (parameter
block)
tWHQV3
0.3
0.3
.4
s
tc( W )ERM
Cycle time, erase operation (main block)
tWHQV4
0.6
0.6
.7
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
Hold time, VPP from valid status-register bit
th(RP)
Hold time, RP at VHH from valid
status-register bit
Hold time, A0 −A17 (see Note 15)
Hold time, E
tPHBR
tWHAX
tWHDX
ns
ns
0
0
0
ns
tWHEH
tQVVL
0
0
0
ns
0
0
0
ns
tQVPH
0
0
0
ns
tAVWH
tDVWH
tELWL
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHWH
tVPWH
100
100
100
ns
100
100
100
ns
60
60
60
ns
20
30
40
ns
220
220
220
ns
tsu(E)
tsu(RP)
Setup time, E before write operation
tsu( VPP)1
tw( W )
Setup time, VPP to W going high
tw( WH)
trec(RPHW)
Pulse duration, W high
tWLWH
tWHWL
Recovery time, RP high to W going low
tPHWL
Pulse duration, W low
100
0
Setup time, A0 −A17 (see Note 15)
Setup time, RP at VHH to W going high
100
0
tsu(A)
tsu(D)
Setup time, DQ
100
0
NOTE 15: A−1 −A17 for byte-wide
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524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F004AZy and TMS28F400AZy (commercial and extended
temperature ranges)
write/erase operations — E-controlled writes
ALT.
SYMBOL
’28F004AZy 60
’28F400AZy 60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( E )
tc(E)OP
Cycle time, write
tc(E)ERB
tc(E)ERP
Cycle time, erase operation (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 −A17 (see Note 15)
th( W )
th (VPP)
Hold time, W
th(RP)
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
tAVAV
tEHQV1
tEHQV2
tEHQV3
tEHQV4
Delay time, boot-block relock
tPHBR
tEHAX
MAX
MIN
MAX
MIN
UNIT
MAX
60
70
80
ns
6
6
6
µs
0.3
0.3
0.3
s
0.3
0.3
0.3
s
0.6
0.6
0.6
s
100
100
100
ns
0
0
0
ns
0
0
0
ns
0
0
0
ns
Hold time, VPP from valid status-register bit
tEHDX
tEHWH
tQVVL
0
0
0
ns
Hold time, RP at VHH from valid status-register
bit
tQVPH
0
0
0
ns
tAVEH
tDVEH
tWLEL
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHEH
tVPEH
100
100
100
ns
100
100
100
ns
Hold time, DQ valid
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
tsu( W )
tsu(RP)
Setup time, W before write operation
tsu( VPP)2
tw(E)
Setup time, VPP to E going high
50
50
ns
Pulse duration, E high
tELEH
tEHEL
50
tw( EH)
trec(RPHE)
10
20
30
ns
Recovery time, RP high to E going low
tPHEL
450
450
450
ns
Setup time, DQ
Setup time, RP at VHH to E going high
Pulse duration, E low
NOTE 15: A−1 −A17 for byte-wide
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
timing requirements for TMS28F400AZy (automotive temperature range)
write/erase operations — E-controlled writes (continued)
ALT.
SYMBOL
’28F004AZy 70
’28F400AZy 70
’28F004AZy 80
’28F400AZy 80
’28F004AZy 90
’28F400AZy 90
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
MIN
tc( E )
Cycle time, write
MAX
MIN
MAX
MIN
UNIT
MAX
tAVAV
70
80
90
ns
tc(E)OP
Cycle time, duration of programming
operation
tEHQV1
6
6
7
µs
tc(E)ERB
Cycle time, erase operation (boot block)
tEHQV2
0.3
0.3
0.4
s
tc(E)ERP
Cycle time, erase operation (parameter
block)
tEHQV3
0.3
0.3
0.4
s
tEHQV4
tPHBR
0.6
0
0
0
ns
0
0
0
ns
0
0
0
ns
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 −A17 (see Note 15)
th( W )
th (VPP)
Hold time, W
tEHAX
tEHDX
tEHWH
Hold time, VPP from valid status-register bit
tQVVL
0
0
0
ns
Hold time, RP at VHH from valid
status-register bit
tQVPH
0
0
0
ns
50
50
50
ns
50
50
50
ns
0
0
0
ns
tPHHEH
tVPEH
100
100
100
ns
100
100
100
ns
60
60
60
ns
20
30
40
ns
300
300
300
ns
th(RP)
Delay time, boot-block relock
Hold time, DQ valid
tsu(A)
tsu(D)
Setup time, A0 −A17 (see Note 15)
Setup time, DQ valid
tAVEH
tDVEH
tsu( W )
tsu(RP)
Setup time, W before write operation
tWLEL
tsu( VPP)2
tw(E)
Setup time, VPP to E going high
tw( EH)
trec(RPHE)
Pulse duration, E high
tELEH
tEHEL
Recovery time, RP high to E going low
tPHEL
Setup time, RP at VHH to E going high
Pulse duration, E low
0.6
100
0.7
100
s
100
ns
NOTE 15: A−1 −A17 for byte-wide
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69
70
Data (D)
Address (A)
VCC (3 V, 5 V)
RP (P)
0V
3.0 V
3.3 V
tsu(DV)
Valid 3.3 Outputs
ta(DV)
Valid
tsu(VCC)
Figure 10. Power-Up Timing and Reset Switching
th(RP3)
4.5 V
PARAMETER MEASUREMENT INFORMATION
5.0 V
th(RP5)
tsu(DV)
Valid 5.0 Outputs
ta(DV)
Valid
Template Release Date: 7−11−94
1
231413533614 16
111
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
tc(R)
A −1 −A17 (byte-wide)
A0 −A17 (word-wide)
Address Valid
ta(A)
E
tdis(E)
ta(E)
G
tdis(G)
ta(G)
W
td(G)
th(D)
td(E)
DQ0 −DQ7 (byte-wide)
DQ0 −DQ15 (word-wide)
VCC
Hi-Z
Hi-Z
td(RP)
RP
Figure 11. Read-Cycle Timing
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A −1 −A17 Standby
(byte-wide)
A0 −A17
(word-wide)
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte / Word
Programming
Read StatusRegister Bits
Write
Read-Array
Command
tc(W)
tsu(A)
th(A)
E
tsu(E)
th(E)
G
tc( W )OP
tw( WH )
W
DQ0 − DQ7
(byte-wide)
DQ0 − DQ15
(word-wide)
tw( W )
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
Hi-Z
40h or 10h
trec(RPHW)
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
th( VPP)
tsu( VPP)1
VPP
Figure 12. Write-Cycle Timing ( W-Controlled Write)
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FFh
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
−A17Standby
A −1
(byte-wide)
A0 −A17
(word-wide)
Write
Program-Setup
Command
Automated
Byte / Word
Programming
Write Valid
Address
And Data
tc( W )
Read Status
Register Bits
Write
Read-Array
Command
tsu(A)
th(A)
W
tsu( W )
th( W )
G
tc(E)OP
tw(EH)
E
DQ0 −
DQ7
(bytewide)
DQ0 −
DQ15
(wordwide)
tw(E)
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
FFh
Hi-Z
40h or 10h
tsu(RP)
trec(RPHE)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
th( VPP)
VPP
Figure 13. Write-Cycle Timing (E-Controlled Write)
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power
Up and
A −1 −A17 Standby
(byte-wide)
A0 −A17
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
E
tsu(E)
th(E)
G
tc( W )ERB
tc( W )ERP
tc( W )ERM
tw( WH)
W
DQ0 −
DQ7
(bytewide)
DQ0 −
DQ15
(wordwide)
tw( W )
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHW)
FFh
Hi-Z
tsu(RP)
th(RP)
VHH
VIH
RP
tsu(WP)
th(WP)
WP
tsu( VPP)1
th( VPP)
VPPH
VPPL
VPP
Figure 14. Erase Cycle Timing (W-Controlled Write)
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A −1 −A17 Standby
(byte-wide)
A0 −A17
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
W
tsu( W )
th( W )
G
tc(E)ERB
tc(E)ERP
tc(E)ERM
tw(EH)
E
DQ0 −DQ7
(byte-wide)
DQ0 −DQ15
(word-wide)
tw(E)
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHE)
FFh
Hi-Z
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
th( VPP)
VPP
Figure 15. Erase-Cycle Timing (E-Controlled Write)
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
A−1 −A17
(byte-wide)
A0 −A17
(word-wide)
Address Valid
tc( R )
ta(A)
E
ta(E)
tdis(E)
G
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
DQ0 −DQ7
Hi-Z
Hi-Z
Byte DQ0 −DQ7
td(G)
Word DQ0 −DQ7
td(E)
DQ8 −DQ14
Hi-Z
Hi-Z
ta(A)
tdis(BL)
Word DQ8 −DQ14
DQ15/A −1
Hi-Z
A −1 Input
Word DQ15
Figure 16. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
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Hi-Z
524288 BY 8-BIT/144 BY 16-BIT
SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
A −1 −A17
(byte-wide)
A0 −A17
(word-wide)
Address Valid
tc( R )
ta(A)
E
ta(E)
tdis(E)
G
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
Byte DQ0 −DQ7
ta(BH)
DQ0 −DQ7
Hi-Z
Hi-Z
td(G)
Word DQ0 −DQ7
td(E)
DQ8 −DQ14
Hi-Z
Hi-Z
Word DQ8 −DQ14
Word DQ15
DQ15/A −1
A −1 Input
Hi-Z
Hi-Z
Figure 17. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
1,27
0,16 M
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°−ā 8°
0,80
Seating Plane
2,625 MAX
0,50 MIN
0,10
4073325 / A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
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SMJS829A − JANUARY 1996 − REVISED AUGUST 1997
MECHANICAL DATA
DCD (R-PDSO-G**)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
40 PIN SHOWN
NO. OF
PINS **
MAX
MIN
40
0.402
(10,20)
0.385
(9,80)
48
0.476
(12,10)
0.469
(11,90)
1
40
0.020 (0,50)
A
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21) M
21
20
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.006 (0,15)
NOM
0.047 (1,20) MAX
Seating Plane
0.028 (0,70)
0.020 (0,50)
0.004 (0,10)
0.010 (25,00) NOM
4073307/B 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
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79
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