GSI GS74117AX-10

GS74117AX
FP-BGA
Commercial Temp
Industrial Temp
256K x 16
4Mb Asynchronous SRAM
Features
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
Fine Pitch BGA 256K x 16 Bump Configuration
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 150/130/105/95 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package:
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
Description
The GS74117A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS74117A is available in a 6 x 10 mm Fine
Pitch BGA package.
Pin Descriptions
Symbol
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
DQ1
UB
A3
A4
CE
DQ16
C
DQ3
DQ2
A5
A6
DQ15 DQ14
D
VSS
DQ4
A17
A7
DQ13
VDD
E
VDD
DQ5
NC
A16
DQ12
VSS
F
DQ6
DQ7
A8
A9
DQ10 DQ11
G
DQ8
NC
A10
A11
WE
DQ9
H
NC
A12
A13
A14
A15
NC
Package X
6 x 10 mm Bump Pitch
Top View
Description
A0–A17
Address input
DQ1–DQ16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
Write enable input
OE
Output enable input
VDD
+3.3 V power supply
VSS
Ground
NC
No connect
Rev: 1.02 10/2002
1
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Block Diagram
A0
Address
Input
Buffer
Row
Decoder
Memory Array
Column
Decoder
A17
CE
WE
Control
OE
_____
UB
LB _____
I/O Buffer
DQ1
DQ16
Truth Table
CE
OE
WE
LB
UB
DQ1 to DQ8
DQ9 to DQ16
VDD Current
H
X
X
X
X
Not Selected
Not Selected
ISB1, ISB2
L
L
Read
Read
L
H
Read
High Z
H
L
High Z
Read
L
L
Write
Write
L
H
Write
Not Write, High Z
H
L
Not Write, High Z
Write
L
L
L
X
H
L
L
H
H
X
X
High Z
High Z
L
X
X
H
H
High Z
High Z
IDD
Note: X: “H” or “L”
Rev: 1.02 10/2002
2/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
Input Voltage
VIN
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Output Voltage
VOUT
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Allowable power dissipation
PD
0.7
W
Storage temperature
TSTG
–55 to 150
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -7/-8/-10/-12
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VDD +0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Ambient Temperature,
Commercial Range
TAc
0
—
70
o
Ambient Temperature,
Industrial Range
TAI
–40
—
85
oC
C
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Rev: 1.02 10/2002
3/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
CIN
VIN = 0 V
5
pF
Output Capacitance
COUT
VOUT = 0 V
7
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
IIL
VIN = 0 to VDD
– 1 uA
1 uA
Output Leakage
Current
ILO
Output High Z
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4 mA
2.4
—
Output Low Voltage
VOL
ILO = +4 mA
—
0.4 V
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70°C
–40 to 85°C
Unit
7 ns
8 ns
10 ns
12 ns
7 ns
8 ns
10 ns
12 ns
IDD
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
150
130
105
90
160
140
115
100
mA
Standby
Current
ISB1
CE ≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
28
30
25
22
38
40
35
32
mA
Standby
Current
ISB2
CE ≥ VDD – 0.2 V
All other inputs
≥ VDD – 0.2 V or ≤ 0.2 V
Operating
Supply
Current
Rev: 1.02 10/2002
10
4/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20
mA
© 2001, Giga Semiconductor, Inc.
GS74117AX
AC Test Conditions
Output Load 1
Parameter
Conditions
Input high level
VIH = 2.4 V
Input low level
VIL = 0.4 V
50Ω
Input rise time
tr = 1 V/ns
VT = 1.4 V
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output Load 2
Output reference level
1.4 V
3.3 V
Output load
Fig. 1& 2
DQ
Rev: 1.02 10/2002
589Ω
DQ
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
5/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
30pF1
5pF1
434Ω
© 2001, Giga Semiconductor, Inc.
GS74117AX
AC Characteristics
Read Cycle
Parameter
Symbol
Read cycle time
-7
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tRC
7
—
8
—
10
—
12
—
ns
Address access time
tAA
—
7
—
8
—
10
—
12
ns
Chip enable access time (CE)
tAC
—
7
—
8
—
10
—
12
ns
Byte enable access time (UB, LB)
tAB
—
3
—
3.5
—
4
—
5
ns
Output enable to output valid (OE)
tOE
—
3
—
3.5
—
4
—
5
ns
Output hold from address change
tOH
3
—
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
tLZ*
3
—
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
tOLZ*
0
—
0
—
0
—
0
—
ns
Byte enable to output in low Z (UB, LB)
tBLZ*
0
—
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
tHZ*
—
3.5
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
tOHZ*
—
3
—
3.5
—
4
—
5
ns
Byte disable to output in High Z (UB, LB)
tBHZ*
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC
Address
tAA
tOH
Data Out
Rev: 1.02 10/2002
Previous Data
Data valid
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Read Cycle 2: WE = VIH
tRC
Address
tAA
CE
tAC
tHZ
tLZ
tAB
UB, LB
tBHZ
tBLZ
OE
tOE
tOHZ
Data valid
tOLZ
High impedance
Data Out
Write Cycle
Parameter
Symbol
Write cycle time
-7
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tWC
7
—
8
—
10
—
12
—
ns
Address valid to end of write
tAW
5
—
5.5
—
7
—
8
—
ns
Chip enable to end of write
tCW
5
—
5.5
—
7
—
8
—
ns
Byte enable to end of write
tBW
5
—
5.5
—
7
—
8
—
ns
Data set up time
tDW
3.5
—
4
—
4.5
—
6
—
ns
Data hold time
tDH
0
—
0
—
0
—
0
—
ns
Write pulse width
tWP
5
—
5.5
—
7
—
8
—
ns
Address set up time
tAS
0
—
0
—
0
—
0
—
ns
Write recovery time (WE)
tWR
0
—
0
—
0
—
0
—
ns
Write recovery time (CE)
tWR1
0
—
0
—
0
—
0
—
ns
Output Low Z from end of write
tWLZ*
3
—
3
—
3
—
3
—
ns
Write to output in High Z
tWHZ*
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.02 10/2002
7/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tBW
UB, LB
tAS
tWP
WE
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
Data Out
High impedance
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tBW
UB, LB
tWP
WE
tDW
Data valid
Data In
Data Out
Rev: 1.02 10/2002
tDH
High impedance
8/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Write Cycle 3: UB, LB control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tBW
UB, LB
tWP
WE
tDW
Data valid
Data In
Data Out
Rev: 1.02 10/2002
tDH
High impedance
9/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Package X—6 mm x 10 mm FP-BGA
Symbol
D
E
Pin A1
Index
Top View
A
Unit: mm
A
1.10±0.10
A1
0.20~0.30
fb
f0.30~0.40
c
0.36(TYP)
D
10.0±0.05
D1
5.25
E
6.0±0.05
E1
3.75
e
0.75(TYP)
aaa
0.10
c
A1
Pin A1
Index
Side View
aaa
A B C D E F G H
1
2
3
4
5
6
fb Solder Ball
e
E1
e
D1
Bottom View
Rev: 1.02 10/2002
10/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
Ordering Information
Part Number*
Package
Access Time
Temp. Range
GS74117AX-7
6 mm x 10 mm BGA
7 ns
Commercial
GS74117AX-8
6 mm x 10 mm BGA
8 ns
Commercial
GS74117AX-10
6 mm x 10 mm BGA
10 ns
Commercial
GS74117AX-12
6 mm x 10 mm BGA
12 ns
Commercial
GS74117AX-7I
6 mm x 10 mm BGA
7 ns
Industrial
GS74117AX-8I
6 mm x 10 mm BGA
8 ns
Industrial
GS74117AX-10I
6 mm x 10 mm BGA
10 ns
Industrial
GS74117AX-12I
6 mm x 10 mm BGA
12 ns
Industrial
Status
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS74117AX-8T
Rev: 1.02 10/2002
11/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
GS74117AX
4Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
74117A_r1
Types of Changes
Format or Content
Format/Content
Page #/Revisions/Reason
• Creation of new datasheet
74117A_r1; 74117A_r1_01
Content
• Updated Recommended Operating Conditions table on page 3
• Updated Read Cycle and Write Cycle AC Characteristics tables
74117A_r1_01; 74117A_r1_02
Content
• Removed 6 ns speed bin from entire document
Rev: 1.02 10/2002
12/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.