SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 • FEATURES • • • • • Member of the Texas Instruments Widebus+™ Family Operates From 2.7 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 3.7 ns at 3.3 V Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) • • GKE PACKAGE (TOP VIEW) <br/> <br/> 1 2 3 4 5 6 TERMINAL ASSIGNMENTS 1 2 3 A 1B2 1B1 B 1B4 1B3 C 1B6 D A B C D E 4 5 6 1DIR 1OE 1A1 1A2 GND GND 1A3 1A4 1B5 VCC VCC 1A5 1A6 1B8 1B7 GND GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 F F 2B4 2B3 VCC VCC 2A3 2A4 G G 2B6 2B5 GND GND 2A5 2A6 H H 2B7 2B8 2DIR 2OE 2A8 2A7 J J 3B2 3B1 3DIR 3OE 3A1 3A2 K K 3B4 3B3 GND GND 3A3 3A4 L M N P R L 3B6 3B5 VCC VCC 3A5 3A6 M 3B8 3B7 GND GND 3A7 3A8 N 4B2 4B1 GND GND 4A1 4A2 P 4B4 4B3 VCC VCC 4A3 4A4 R 4B6 4B5 GND GND 4A5 4A6 T 4B7 4B8 4DIR 4OE 4A8 4A7 T DESCRIPTION/ORDERING INFORMATION This 32-bit (quad-octal) noninverting bus transceiver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVCZ32245A is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. ORDERING INFORMATION TA –40°C to 85°C (1) PACKAGE (1) LFBGA – GKE Tape and reel ORDERABLE PART NUMBER SN74LVCZ32245AGKER TOP-SIDE MARKING ZC245A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE 2 DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR A3 2DIR A4 1A1 H4 1OE A5 2A1 A2 H3 E5 E2 1B1 To Seven Other Channels 3DIR 2B1 To Seven Other Channels J3 4DIR J4 3A1 2OE T4 3OE J5 4A1 J2 T3 4OE N5 N2 3B1 To Seven Other Channels 4B1 To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V –0.5 VCC + 0.5 state (2) (3) UNIT VO Voltage range applied to any output in the high or low IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) –65 V mA 40 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage MIN MAX 2.7 3.6 2 V V V 0 5.5 0 VCC 3-state 0 5.5 Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate 150 TA Operating free-air temperature –40 V 0.8 High or low state VO (1) UNIT VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 6 V mA mA ns/V µs/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 2.7 V to 3.6 V II Control inputs Ioff MIN TYP (1) MAX 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 VI = 0 to 5.5 V VI or VO = 5.5 V UNIT VCC – 0.2 2.7 V IOH = –12 mA VOL VCC V 0.2 V 3.6 V ±5 µA 0 ±5 µA 3.6 V ±5 µA IOZPU VO = 0.5 V to 2.5 V, OE = don't care 0 to 1.5 V ±5 µA IOZPD VO = 0.5 V to 2.5 V, OE = don't care 1.5 V to 0 ±5 µA IOZ (2) VO = 0 to 5.5 V VI = VCC or GND ICC 3.6 V ≤ VI ≤ 5.5 V (3) ∆ICC IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND 120 3.6 V 120 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 5 pF Cio A or B ports VO = VCC or GND 3.3 V 6.5 pF (1) (2) (3) 4 All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B ten OE tdis OE PARAMETER VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX B or A 4.2 1.3 4 ns A or B 6.1 1.4 5.6 ns A or B 7.1 2 6.6 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B B or A ten OE A or B tdis OE A or B PARAMETER VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V UNIT MIN MAX 3.9 1 3.7 ns 5.9 1.1 5.4 ns 6.7 1.6 6.2 ns Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled f = 10 MHz VCC = 3.3 V TYP 42 4 UNIT pF 5 SN74LVCZ32245A 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES423 – JANUARY 2003 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF or 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VOH VCC/2 VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 PACKAGING INFORMATION Status (1) Package Type Package Drawing SN74LVCZ32245AGKER NRND LFBGA GKE 96 1000 SN74LVCZ32245AZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) Orderable Device Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSL Peak Temp (3) SNPB Level-3-220C-168 HR SNAGCU Level-3-250C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 27-Apr-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVCZ32245AGKER GKE 96 HIJ 330 24 5.7 13.7 2.0 8 24 Q1 SN74LVCZ32245AZKER ZKE 96 HIJ 330 24 5.7 13.7 2.0 8 24 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVCZ32245AGKER GKE 96 HIJ 346.0 346.0 41.0 SN74LVCZ32245AZKER ZKE 96 HIJ 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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