SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 FEATURES • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE DESCRIPTION/ORDERING INFORMATION This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16245-EP is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C SSOP – DL Tape and reel CALVCH16245IDLREP ALVCH16245 –55°C to 125°C SSOP – DL Tape and reel CALVCH16245MDLREP ALCH16245M (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX –0.5 4.6 Except I/O ports (2) –0.5 4.6 I/O ports (2) (3) –0.5 VCC + 0.5 –0.5 VCC + 0.5 V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 UNIT –65 V V mA 63 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 Recommended Operating Conditions VCC (1) Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V IOH High-level output current V 0.8 VCC = 1.65 V –4 VCC = 2.3 V –12 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 mA IOL Low-level output current ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature (I temp) –40 85 °C TA Operating free-air temperature (M temp) –55 125 °C (1) mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VCC 1.65 V to 3.6 V 1.65 V IOH = –6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 IOH = –12 mA II(hold) V 3V 2.4 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 IOL = 24 mA UNIT 1.2 IOH = –24 mA IOL = 12 mA II TYP (1) MAX VCC – 0.2 IOH = –4 mA VOH VOL MIN V ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V –25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V –45 VI = 0.8 V 3V 75 VI = 2 V 3V –75 µA µA VI = 0 to 3.6 V (2) 3.6 V ±500 IOZ (3) VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA ∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA Ci Control inputs VI = VCC or GND 3.3 V 4 pF Cio A or B port VO = VCC or GND 3.3 V 8 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. Switching Characteristics over recommended operating free-air I temperature (–40°C to 85°C) range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B ten tdis PARAMETER 4 VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX UNIT MIN MAX B or A 1 3.7 3.6 1 3 ns OE A or B 1 5.7 5.4 1 4.4 ns OE A or B 1 5.2 4.6 1 4.1 ns Submit Documentation Feedback SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 Switching Characteristics over recommended operating free-air M temperature (–55°C to 125°C) range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B ten OE tdis OE PARAMETER VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX B or A 1 4.5 1 4.0 ns A or B 1 8.2 1 5.5 ns A or B 1 7.5 1 5.0 ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance (1) TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 22 29 (1) 4 5 UNIT pF This information was not available at the time of publication. Submit Documentation Feedback 5 SN74ALVCH16245-EP 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES608A – SEPTEMBER 2004 – REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL (see Note A) RL S1 Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLZ VLOAD/2 VM tPZH tPHL VOH VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 8R16245MDLREPG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CALVCH16245IDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CALVCH16245MDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04763-01XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04763-02XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF SN74ALVCH16245-EP : • Catalog: SN74ALVCH16245 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CALVCH16245IDLREP SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 CALVCH16245MDLREP SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CALVCH16245IDLREP SSOP DL 48 1000 346.0 346.0 49.0 CALVCH16245MDLREP SSOP DL 48 1000 346.0 346.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. 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