SED1278 CMOS DOT MATRIX LCD CONTROLLER DRIVER ■ DESCRIPTION The SED1278 is a character LCD controller-driver, capable of driving displays as large as 2 lines of 8 characters (5 × 8 pixels), with minimum external components. The SED1278 has an internal CGROM consisting of 240 characters (5 × 7) plus the underline cursor, JIS, ASCII, and eight user-programmable characters in RAM. The SED1278 has 40 segment output and 16 common output built-in. Thus, one chip is capable of displaying up to 16 characters. The SED1278 can display one line of 48 characters using an SED1681F (80-bit output) as an expansion segment driver. The SED1278 is fabricated using a silicon gate CMOS technology process and features very low power dissipation. This makes the device suitable for handheld and portable applications. ■ FEATURES • Low-power CMOS technology • 40 segment output • 16 common output • Duty: 1/8 or 1/16 (set by command) • 4/8-bit CPU data interface, TTL compatible • Two frame AC drive wave form • CGROM: .................................... 240 characters • CGRAM: ........................................ 8 characters • Display data RAM: ... 80 × 8 bits (80 characters) expansion segment driver: • Recommended SED1181F (64 output) • Built-in power on power-on reset • Built-in RC oscillator • Built-in LCD driver voltage-divider network • TTL compatible CPU interface Logic: 4.5V to 5.5V • Supply voltage ................... LCD: 3.5V to 5.5V Package: • QFP5-80 pins (F0A, F0B, F0C, F0D, F0G, F0H) Al pad (D0A, D0B, D0C, D0D, D0G, D0H) LA SED1681F (80 output) ■ SYSTEM BLOCK DIAGRAM 40 SEG DATA SED1278 CONTROL 16 COM 20 CHAR × 2 LINES 64 SEG CPU XSCL, LP D0 287 SED1181 SED1278 ■ BLOCK DIAGRAM OSC1 OSC2 Cursor/ Brink Control Instruction Decoder Address Counter ACC DB7 I/O Buffer Instruction Register DB0 M 7 8 P X Timing Generator Display Data RAM DD RAM 80 Bytes I/O Control E RS Oscillation Circuit 7 Data Register R/W Refresh Address Counter 8 Shift Register 16 Bits Common Driving Output Circuit M P X XSCL LP FR 8 COM1 COM16 SEG1 VDD Character Generator RAM (CG-RAM) 64 Bytes 8 VSS V1 V2 Character Generator RAM (CG-RAM) 5 x 10 x 240 Bits 5 V3 V4 Segment Driving Output Circuit SEG40 5 M P Latch Circuit 40 Bits X V5 5 Parallel/Serial Data Converter Shift Register 40 Bits SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2 ■ PIN CONFIGURATION 65 60 55 50 45 70 40 35 SED1278F Index 75 80 1 5 30 10 15 20 25 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VSS OSC1 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 288 DB1 DB0 E R/W RS DP FR VDD XSCL LP V5 V4 V3 V2 V1 OSC2 D0 SED1278 ■ PIN DESCRIPTION Symbol No. of signals RS 1 Register select signal Functions R/W 1 Read/write select signal *1 E 1 Read/write execute signal DB0 to DB7 8 Data bus LP 1 Data latching pulse XSCL 1 Data transfer clock FR 1 LCD AC driving signal DO 1 Serial data COM1 to COM16 16 Common outputs COM9 to COM16 : non-select for 1/8 duty COM12 to COM16: non-select for 1/11 duty SEG1 to SEG40 40 Segment outputs V1 to V5 5 LCD driving power (V5≥VSS) VDD 1 +5V VSS 1 0V (GND) OSC1 2 OSC2 *1 Used to connect resistor (typ. 91KΩ) for oscillation; OSC1 is for external clock input. RS R/W 0 0 0 1 1 0 1 1 E Operation 1 Instruction write cycle Busy flag read cycle Address counter read cycle DD RAM or CG RAM data write cycle 1 DD RAM or CG RAM data read cycle ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • (VSS = 0V, Ta = 25°C) Parameter Symbol Rating Unit Supply voltage (1) VDD –0.3 to 7.0 V Supply voltage (2) V1 to V5 –0.3 to VDD+0.3 V Input voltage VI –0.3 to VDD+0.3 V Output voltage VO –0.3 to VDD+0.3 V mW Power dissipation PD 300 Operating temperature Topr –20 to 75 °C Storage temperature Tstg –65 to 150 °C Soldering temperature and time Tsol 260°C•10s (at lead) — Note: The following condition must always hold true: VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 289 SED1278 • DC Characteristics (VDD = 5.0V ±10%, VSS = 0V, Ta = –20 to 75°C) Parameter Symbol Applicable Pin Min Typ Max Unit “H” level input voltage (1) VIH1 Condition DB0~DB7 2.0 — VDD V “L” level input voltage (1) VIL1 RS, R/W, E “H” level input voltage (2) VIH2 “L” level input voltage (2) VIL2 “H” level output voltage (1) VOH1 IOH=–0.205mA “L” level output voltage (1) VOL1 IOL=1.6mA OSC1 DB0~DB7 “H” level output voltage (2) VOH2 IOH=–0.04mA “L” level output voltage (2) VOL2 IOL=0.04mA Driver-on resistor (COM) RCOM |VCOM–Vn|=0.5V XSCL LP D0 COM1~16 Driver-on resistor (SEG) RSEG |VSEG–Vn|=0.5V SEG1~40 VSS — 0.8 V VDD–1.0 — VDD V VSS — 1.0 V 2.4 — — V 0.4 V — — 0.9VDD — — V — — 0.1VDD V — 2 10 kΩ — 2.5 10 kΩ µA I/O leakage current IIL VI=0 to VDD — — 1 Pull-up MOS current –IP VDD=5V 50 125 250 µA Supply current Iop Rf oscillation, from external clock VDD=5V, fOSC=fCP=270kHz — 0.5 0.8 mA fEXTCL 125 250 350 kHz Duty 45 50 55 % External clock rise time trEXTCL — — 0.2 µs External clock fall time tfEXTCL — — 0.2 µs 190 270 350 kHz VDD External clock operation External clock operating frequency External clock duty Internal clock operation (Rf oscillation) Oscillation frequency fOSC Rf=91kΩ±2% Internal clock operation (Ceramic filter oscillation) • ° Oscillation frequency fOSC Ceramic filter 245 250 255 kHz LCD driving voltage VLCD VDD–V5 3.0 — VDD V AC Characteristics Read cycle Parameter (VDD = 5.0V ± 10%, VSS = 0V, Ta = –20 to 75°C) Min Typ Max Unit Enable cycle time Symbol tcycE Conditions 500 — — ns Enable “H” level pulse width tWEH 220 — — ns Enable rise/fall time trE, tfE — — 25 ns RS, R/W setup time tAS 40 — — ns RS, R/W address hold time tAH 10 — — ns Read data output delay tRD — — 120 ns Read data hold time tDHR 20 — — ns CL=100pF 290 SED1278 ° Write cycle (VDD = 5.0V±10%, VSS = 0V, Ta = –20 to 75°C) Parameter • ° Min Typ Max Unit Enable cycle time Symbol tcycE Conditions 500 — — ns Enable “H” level pulse width tWEH 220 — — ns Enable rise/fall time trE, tfE — — 25 ns RS, R/W setup time tAS 40 — — ns RS, R/W address hold time tAH 10 — — ns Data setup time tDS 60 — — ns Write data hold time tDH 10 — — ns Timing Chart Read cycle RS VIH1 VIL1 R/W VIH1 VIH1 VIL1 tAS tAH VIH1 tWEH E VIL1 trE VIH1 VIH1 VIL1 VIL1 tDHR tRD VOH1 VOL1 DB0 to DB7 tAH tfE VOH1 VOL1 Significant Data tcycE ° Write cycle RS VIH1 VIL1 VIH1 VIL1 tAS R/W tAH VIL1 VIL1 tWEH E VIL1 VIH1 VIH1 trE DB0 to DB7 tAH tfE VIL1 tDH tDS VIH1 VIL1 Significant Data tcycE 291 VIL1 VIH1 VIL1 SED1278 ■ DISPLAY COMMAND Parameter RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLEAR DISPLAY 0 0 0 0 0 0 0 0 0 1 CURSOR HOME 0 0 0 0 0 0 0 0 1 * ENTRY MODE SET 0 0 0 0 0 0 0 1 I/D S Note DB1=1 : Increment, DB1=0 : Decrement DB0=1 : The display is shifted. DB0=0 : The display is not shifted. DB2=1 : Display on DB2=0 : Display off DISPLAY ON/OFF 0 0 0 0 0 0 CURSOR/DISPLAY SHIFT 0 0 0 0 0 1 1 D S/C R/L C B * * DB1=1 : Cursor on DB0=1 : Brinking on DB1=0 : Cursor off DB0=0 : Brinking off DB3=1 : Shifts display one character DB2=1 : Right shift, DB2=0 : Left shift DB4=1 : 8 bits, DB4=0 : 4 bits DB3=1 : 2 lines display (1/16 duty), SYSTEM SET 0 0 0 0 1 DL N F * * DB3=0 : 1 line display DB2=1 : 5x10 dots, 1/11 duty ( DB2=0 : 5x7dots, 1/8 duty SET CGRAM ADDRESS 0 0 0 SET DDRAM ADDRESS 0 READ BUSY FLAG/ ADDRESS COUNTER 0 WRITE DATA 1 0 1 ADD 1 BF AC 0 Write Data READ DATA 1 Read Data 1 1 ACG * Don’t care 292 ) The address length that can be set is 64 addresses. The address length that can be set is 80 addresses. DB7=1 : Busy (instruction not accepted) DB7=0 : Ready (instruction accepted) SED1278 ■ EXAMPLE OF APPLICATION (2 lines × 20 characters) SED1278 LCD COM1 16 × 100 Dots 16 COM16 SEG1 40 60 D0 SEG59 D0 SEG0 SEG40 DO1 D1 DO0 LP XSCL FR VDD VSS V2 V3 VSSH SED1181FLA/DLA LP XSCL FR VDD VSS V2 V3 V5 OSC1 OSC2 Rf SED1278 is usually connected to 8-bit MPU via I/O ports. 293 OPEN SED1278 ■ PAD LAYOUT 4,500 (0,0) X •••••••• •••••••• 3,670 Y ••••••••••••••• 1 25 • • • • • • • • • • • • • • • • • • • • •80 •• ••••••••••••••• 24 40 • • • • • • • • • • • • • • • • • • • • •65 •• 41 64 Pad size: 109 × 109 294 Monitor Pad SED1278 • PAD COORDINATES Pad No. Pad Name X Y Pad No. Pad Name X Y 1 SEG22 2087 1671 41 DB2 –2087 –1671 2 SEG21 1905 1671 42 DB3 –1905 –1671 3 SEG20 1723 1671 43 DB4 –1723 –1671 DB5 –1541 –1671 4 SEG19 1541 1671 44 5 SEG18 1359 1671 45 DB6 –1359 –1671 6 SEG17 1177 1671 46 DB7 –1177 –1671 7 SEG16 995 1671 47 COM1 –995 –1671 1671 48 COM2 –814 –1671 8 SEG15 814 9 SEG14 633 1671 49 COM3 –633 –1671 10 SEG13 452 1671 50 COM4 –452 –1671 11 SEG12 272 1671 51 COM5 –272 –1671 12 SEG11 91 1671 52 COM6 –91 –1671 13 SEG10 –91 1671 53 COM7 91 –1671 14 SEG9 –272 1671 54 COM8 272 –1671 15 SEG8 –452 1671 55 COM9 452 –1671 COM10 633 –1671 16 SEG7 –633 1671 56 17 SEG6 –814 1671 57 COM11 814 –1671 18 SEG5 –995 1671 58 COM12 995 –1671 19 SEG4 –1177 1671 59 COM13 1177 –1671 COM14 1359 –1671 –1671 20 SEG3 –1359 1671 60 21 SEG2 –1541 1671 61 COM15 1541 22 SEG1 –1723 1671 62 COM16 1723 –1671 23 GND –1905 1671 63 SEG40 1905 –1671 24 OSC1 –2087 1671 64 SEG39 2087 –1671 25 OSC2 –2087 1365 65 SEG38 2087 –1365 26 V1 –2087 1183 66 SEG37 2087 –1183 27 V2 –2087 1001 67 SEG36 2087 –1001 SEG35 2087 –819 28 V3 –2087 819 68 29 V4 –2087 637 69 SEG34 2087 –637 30 V5 –2087 455 70 SEG33 2087 –455 31 LP –2087 273 71 SEG32 2087 –273 91 72 SEG31 2087 –91 32 XSCL –2087 33 VCC –2087 –91 73 SEG30 2087 91 34 FR –2087 –273 74 SEG29 2087 273 35 DO –2087 –455 75 SEG28 2087 455 –637 76 SEG27 2087 637 36 RS –2087 37 R/W –2087 –819 77 SEG26 2087 819 38 E –2087 –1001 78 SEG25 2087 1001 39 DB0 –2087 –1183 79 SEG24 2087 1183 –1365 80 SEG23 2087 1365 40 DB1 –2087 295 SED1278 ■ SED1278F0A/D0A CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 296 E F SED1278 ■ SED1278F0B/D0B CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 297 E F SED1278 ■ SED1278F0C/D0C CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 298 E F SED1278 ■ SED1278F0D/D0D CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 299 E F SED1278 ■ SED1278F0G/D0G CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) 300 E F SED1278 ■ SED1278F0H/D0H CHARACTER FONT 0 CG 0 RAM (1) 1 2 Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D E F CG 1 RAM (2) CG 2 RAM (3) CG 3 RAM (4) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) CG 4 RAM (5) CG 5 RAM (6) CG 6 RAM (7) CG 7 RAM (8) CG 8 RAM (1) CG 9 RAM (2) CG A RAM (3) CG B RAM (4) CG C RAM (5) CG D RAM (6) CG E RAM (7) CG F RAM (8) * Character codes (00H-0FH) of SED1278F are assigned to the area of character generator RAM (CG RAM). The CG ROM of the SED1278F is masked; if you wish to have your own CG ROM, consult S-MOS Marketing Department for conversion of the masked ROM. 301 THIS PAGE INTENTIONALLY BLANK 302