NT7603 PRELIMINARY Single-Chip 16Cx2L Dot-Matrix LCD Controller / Driver Features Internal LCD drivers 16 common signal drivers 80 segment signal drivers Maximum display dimensions 16 characters * 2 lines or 32 characters * 1 line Interfaces with 4-bit or 8-bit MPU Versatile display functions provided on chip: Display Clear, Cursor Home, Display ON/OFF, Cursor ON/OFF, Character Blinking, Cursor Shift, and Display Shift Three duty factors, selected by PROGRAM: 1/8, 1/11, and 1/16 Displays Data RAM (DD RAM): 80 X 8 bits (Displays up to 80 characters) Character Generator RAM (CG RAM): 64 X 8 bits for general data, 8 5 X 8 programmable dot patterns, or 4 5 X 10 programmable dot patterns Low voltage reset ITO option for A-type and B-type LCD waveform Character Generator ROM (CG ROM): 2 kinds of CG ROM sizes: 192 characters: 160 5 X 8 dot patterns 32 5 X 10 dot patterns 240 characters: 192 5 X 8 dot patterns 48 5 X 10 dot patterns Custom CG ROM is also available Built-in power-on reset function Logic power supply: single +5V supply LCD driver power supply: V1~V5 (VDD+0.3 - VDD-7.0) , divided by Built-in LCD power division resister. Two oscillator operations (Freq. = 500KHz - 540KHz): • Built-in RC oscillation • External clock CMOS Process Available in COG FORM General Description The NT7603 is a dot matrix LCD controller and driver LSI that can operate with either a 4-bit or an 8-bit microprocessor (MPU). NT7603 receives control character codes from the MPU, stores them in an internal RAM (up to 80 characters), transforms each character code into a 5 X 7, 5 X 8, or 5 X 10 dot matrix character pattern, and then displays the codes on the LCD panel. The built-in Character Generator ROM consists of 256 different character patterns. The NT7603 also contains Character Generator RAM where the user can store 8 different character patterns at run time. These memory features make character display flexible. NT7603 also provides many display instructions to achieve versatile LCD display functions. The NT7603 is fabricated on a single LSI chip using the CMOS process, resulting in very low power requirements. 1/25 Ver 0.5 NT7603 Pad Configuration 149 84 150 83 166 67 1 66 Item Pad No. Chip size - Pad pitch 1– 166 Size X Y 5156 1349 70 2/25 Unit µm Ver 0.5 NT7603 Block Diagram V1 V2 V3 V4 V5 OPT_R0 OPT_R1 OPT_LCD VDD GND 8 OSC1 OSC2 INSTRUCTION DECODE TEST TIMING GENERATOR 7 INSTRUCTION REGISTER (IR) 8 ADDRESS COUNTER TESTM LCD DRIVER VOLTAGE GENERATOR 7 RS 7 7 R/W 7 E CURSOR ADDRESS COUNTER 7 DISPLAY DATA RAM (DD RAM) 80X8 BITS I/O BUFFER 4 16 COMMON SIGNAL DRIVER 16 COM1 I COM16 80-BIT LATCH CIRCUIT 80 SEGMENT SIGNAL DRIVER 80 SEG1 I SEG80 8 8 DB7~DB4 16-BIT SHIFT REGISTER DATA REGISTER (DR) DB3~DB0 4 BUSY FLAG (BF) 8 CURSOR /BLINK CONTROLLER 8 7 DHARACTER GENERATOR RAM (CG RAM) 64X8 BITS CHARACTER GENERATOR ROM (CG ROM) 5 5 PARALLER - TO - SERIAL CONVERTER 3/25 TESTD Ver 0.5 NT7603 Pad Description (Total 166 pads for COG type.) Pad No. Designation I/O External Connection 1 – 15 GND P Power supply 16 OSC1 I For external clock operation, clock inputs to OSC1. 17 OSC2 O Clock output. 18 V1 P Power supply Power supply for LCD driver. VDD ≥V1 ≥V2 ≥V3 ≥V4 ≥V5 ≥GND 19 V2 P Power supply Power supply for LCD driver 20 V3 P Power supply Power supply for LCD driver 21 V4 P Power supply Power supply for LCD driver 22 – 25 V5 P Power supply Power supply for LCD driver 26, 28 OPT_R0, OPT_R1 I ITO Option 29 – 43 VDD P Power supply Description GND: 0V The built-in bias resister select: OPT_R1, OPT_R0: No ITO=1. ITO on=0 1,1: 2.2K ; 1,0: 4K ; 0,1: 6.8K Î 0,0:No built-in bias resister: è è è VDD: +5V 44, 45 RS I MPU Register select signal 0: Instruction register (write), Busy flag, address counter (read) 1: Data register (write, read) 46, 47 R/W I MPU Read/Write control signal 0: Write 1: Read 48, 49 E I MPU Read/Write start signal 50, 51 DB0 52, 53 DB1 54, 55 DB2 I/O MPU Lower 4 tri-state bi-directional data bus for transmitting data between MPU and NT7603. Not used during 4-bit operation. 56, 57 DB3 58, 59 DB4 60, 61 DB5 62, 63 DB6 I/O MPU Higher 4 tri-state bi-directional data bus for transmitting data between MPU and NT7603. DB7 is also used as busy flag. 64, 65 DB7 66 OPT_LCD I ITO Option No ITO. (Option =1): B-Type waveform ITO On. (Option =0): A-Type waveform TESTD O Test output Test data output. ( No connect for user) 68 164 – 157 COM1 – 8 O LCD panel 69 – 76, COM9 – 16 O LCD panel Common signal output pins, for place on the upper glass (IC face up). 156 – 77 SEG1 – 80 O LCD panel Segment signal output pins 165 TEST I Test pin 166 TESTM O Test output 67, 27 GND_OUT P Test pin internally pull-down. ( No connect for user) LCD driver clock output. ( No connect for user) GND output pin, use for pull-down ITO option. 4/25 Ver 0.5 NT7603 Functional Description The NT7603 is dot-matrix LCD controller and driver LSI. It operates with either a 4-bit or an 8-bit microprocessor (MPU). The NT7603 receives both instructions and data from the MPU. Some instructions set operation modes, such as the function mode, data entry mode, and display mode; as well as some control LCD display functions, such as clear display, restore display, shift display, and cursor. Other instructions include read and write both data and addresses. All instructions allow users convenient and powerful functions to control the LCD dot-matrix displays. Data is written into and read from the Data Display RAM (DD RAM) or the Character Generator RAM (CG RAM). As display character codes, the data stored in the DD RAM decodes a set of dot-matrix character patterns that are built into the Character Generator ROM (CG ROM). The CG ROM, with many character patterns (up to 256 patterns), defines the character pattern fonts. The NT7603 regularly scans the character patterns through the segment drivers. The CG RAM stores character pattern fonts at run time if users intend to show character patterns that are not defined in the CG ROM. This feature makes character display flexible. Other unused bytes can be used as generalpurpose data storage. The LCD driver circuit consists of 16 common signal drivers and 80 segment signal drivers allowing a variety of application configurations to be implemented. Character Generator ROM (CG ROM) The character generator ROM generates LCD dot character patterns from the 8-bit character pattern codes. The NT7603 provides 2 CG ROM configurations: 1. 192 Characters: The CG ROM contains 160 5 X 8 dot character patterns and 32 5 X 10 dot character patterns, which the relation between the character codes and character patterns is shown in Table 1. The character codes from 00H to 0FH are used to get character patterns from the CG RAM. Character codes from 10H to 1FH and from 80H to 9FH map to full character patterns. Character codes from E0H to FFH are assigned to generate 5 X 10 dot character patterns, and other codes are used to generate 5x8 dot character patterns. 2. 240 Characters: The CG ROM contains 192 5 X 8 dot character patterns and 48 5 X 10 dot character patterns, which the relation between the character codes and character patterns is shown in Table 2. The character codes from 00H to 0FH are used to get character patterns from the CG RAM. Character codes from 10H to 1FH and from E0H to FFH are assigned to generate 5 X 10 dot character patterns, and other codes to generate 5 X 8 dot character patterns. No null character pattern exists in this type. Note that the underlined cursor, displayed on the 8th duty may be obscure if the 8th row of a dot character pattern is coded. We recommend that users display the cursor in the blinking mode if they code 5x8 dot character patterns is their custom CG ROM. Custom character patterns are available by maskprogramming ROM. For convenience of character pattern development, NOVATEK has developed a user-friendly editor program for the NT7603 to help determine the character patterns users prefer. By executing the program on the computer, users can easily create and modify their character patterns. By transferring the resulting files generated by the program through a modem or some other communication method, the user and NOVATEK have established a reliable, fast link for programming the CG ROM. 5/25 Ver 0.5 NT7603 Absolute Maximum Ratings* *Comments Power Supply Voltage (VDD) . . . . . . . . . . -0.3V to +7.0V Power Supply Voltage (V1 to V5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD+0.3V Input Voltage (VI) . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Temperature (TOPR) . . . . . . .-20°C to +70°C Storage Temperature (TSTG) . . . . . . . .-55°C to +125°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. All voltage values are referenced to GND = 0V V1 to V5, must maintain VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ GND. DC Electrical Characteristics (VDD = 5.0V, GND = 0V, TA = 25°C) Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin VDD Operating Voltage 4.5 5.0 5.5 V VIH1 "H" Level Input Voltage (1) 2.2 - VDD V DB0 – DB7, RS, VIL1 "L" Level Input Voltage (1) -0.3 - 0.8 V R/W, E VIH2 "H" Level Input Voltage (2) VDD -1.0 - VDD V OSC1 VIL2 "L" Level Input Voltage (2) GND - 1.0 V VOH1 "H" Level Output Voltage (1) 2.4 - - V IOH = -0.25mA DB0 - DB7 VOL1 "L" Level Output Voltage (1) - - 0.4 V IOL = 1.2mA (TTL) VCOM Driver Voltage Descending (COM) - - 0.3 V ID = 5µA COM1 - 16 VSEG Driver Voltage Descending (SEG) - - 0.3 V ID = 5µA SEG1 - 80 IIL Input Leakage Current -1 - 1 µA VIN = 0 to VDD -IP Pull-up MOS Current 50 125 250 µA VDD = 5V mA Rf oscillation, from external clock VDD = 5V, fOSC = fCP = 540KHz, include LCD bias current. IOP Power Supply Current - 1 6/25 1.5 Not include OSCI RS, R/W, DB0-DB7 VDD Ver 0.5 NT7603 DC Electrical Character (continued) Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin External Clock Operation fCP External Clock Operating Frequency 250 540 700 KHz tDUTY External Clock Duty Cycle 45 50 55 % tRCP External Clock Rise Time 0.1 - 0.5 µs tFCP External Clock Fall Time 0.1 - 0.5 µs Internal Clock Operation (Built-in RC Oscillator) fOSC Oscillator Frequency 380 540 700 KHz VLCD1 VLCD2 LCD Driving Voltage 3.0 - VDD V Rf = 50KΩ (reference only) VDD - V5 AC Characteristics Read Cycle (VDD = 5.0V, GND = 0V, TA = 25°C) Symbol Parameter Min. Typ. Max. Unit Conditions tCYCE Enable Cycle Time 500 - - ns Figure 1 tWHE Enable "H" Level Pulse Width 300 - - ns Figure 1 - - 25 ns Figure 1 - - ns Figure 1 10 - - ns Figure 1 - - 190 ns Figure 1 20 - - ns Figure 1 tRE, tFE Enable Rise/Fall Time tAS RS, R/W Setup Time 1 60 2 100 tAH RS, R/W Address Hold Time tRD Read Data Output Delay tDHR Read Data Hold Time 7/25 Ver 0.5 NT7603 AC Characteristics (continued) Write Cycle (VDD = 5.0V, GND = 0V, TA = 25°C) Symbol Parameter Min. Typ. Max. Unit Conditions tCYCE Enable Cycle Time 500 - - ns Figure 2 tWHE Enable "H" Level Pulse Width 300 - - ns Figure 2 - - 25 ns Figure 2 - - ns Figure 2 tRE, tFE Enable Rise/Fall Time tAS RS, R/W Setup Time 1 60 2 100 tAH RS, R/W Address Hold Time 10 - - ns Figure 2 tDS Data Output Delay 100 - - ns Figure 2 tDHR Data Hold Time 10 - - ns Figure 2 Min. Typ. Max. Unit Conditions Notes: 1: 8-bit operation mode 2: 4-bit operation mode Power Supply Conditions Using Internal Reset Circuit Symbol Parameter tRON Power Supply Rise Time 0.1 - 10 ms Figure 3 tOFF Power Supply OFF Time 1 - - ms Figure 3 8/25 Ver 0.5 NT7603 Timing Waveforms Read Operation V IH1 V IL1 tA S RS V IH1 V IL1 tA H R/W tW H E tF E V IH1 V IL1 E V IL1 tD H R tR E tR D V IH1 V IL1 DB0 ~ DB7 V IL1 V IH1 V IL1 VAILD DATA tC Y C E Figure 1. Bus Read Operation Sequence (Reading out data from NT7603 to MPU) Write Operation V IH1 V IL1 RS V IH1 V IL1 tA S tA H R/W V IL1 tW H E tF E V IH1 V IL1 E V IL1 tD H W tR E tD S V IH1 V IL1 DB0 ~ DB7 VAILD DATA V IL1 V IH1 V IL1 tC Y C E Figure 2. Bus Write Operation Sequence (Writing out data from NT7603 to MPU) Interface Signals with Segment Driver LSI 4.5V VDD 0.2V 0 . 1 m s > tR O N > 1 0 m s 0.2V 0.2V tO F F tR O N > 1ms tO F F Figure 3. tOFF stipulates the time of power ODD for instantaneous Power supply to or when power supply repeats ON and OFF. 9/25 Ver 0.5 NT7603 Note 1: The NT7603 has two clock options: A. Internal Oscillator (Built-in RC) OSC1 OSC2 OPEN OPEN B. External Clock Operation OSC1 OSC2 PULSE INPUT OPEN Note 2: Input/Output Terminals: A. Input Terminal Applicable Terminal: E (No Pull Up MOS) VDD PMOS NMOS Applicable Terminal: RS, R/W (with Pull Up MOS) VDD VDD Pull Up MOS PMOS PMOS NMOS 10/25 Ver 0.5 NT7603 B. Output Terminal Applicable Terminal: TESTM VDD PMOS NMOS C. I/O Terminal Applicable Terminal: DB0 to DB7 VDD VDD Pull Up MOS PMOS PMOS VDD ENABLE PMOS NMOS DATA NMOS (OUTPUT CIRCUIT) (TRISTATE) Note 3: ITO Options: Set Option=0: Place ITO on the Option Pad. Set Option=1: No ITO on the Option Pad. No ITO: GND OUTPUT PAD ITO On: OPTION PAD OPTION GND_OUT (Internal pull up) GND OUTPUT PAD OPTION PAD OPTION GND_OUT (Internal pull up) ITO Option=1 Option=0 11/25 Ver 0.5 NT7603 Table 1. NT7603-01 Correspondence between Character Codes and Character Patterns (NOVATEK Standard 192 Character CG ROM) 12/25 Ver 0.5 NT7603 Table 2. Example of 240 Character CG ROM 13/25 Ver 0.5 NT7603 Instruction Set Instruction Code Function Execution time (max) (fOSC = 250KHz) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 0 0 0 0 0 0 0 0 0 1 Clear entire display area. 1.64ms Display/ Cursor Home 0 0 0 0 0 0 0 0 1 * Restore display from shift and load address counter with DD RAM address 00H. 1.64ms 40µs Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Specify direction of cursor movement and display shift mode. This operation takes place after each data transfer (read/write). Display ON/OFF 0 0 0 0 0 0 1 D C B Specify activation of display (D) cursor (C) and blinking of character at cursor position (B). 40µs Display/ Cursor Shift 0 0 0 0 0 1 S/C R/L * * Shift display or move cursor. 40µs Function Set 0 0 0 0 1 DL N F * * Set interface data length (DL), number of display line (N), and character font (F). 40µs RAM Address Set 0 0 0 1 Load the address counter with a CG RAM address. Subsequent data access is for CG RAM data. 40µs DD RAM Address Set 0 0 1 Load the address counter with a DD RAM address. Subsequent data access is for DD RAM data. 40µs Busy Flag/ Address Counter Read 0 1 AC Read Busy Flag (BF) and contents of Address Counter (AC). 40µs CG RAM/ DD RAM Data Write 1 0 Write data Write data to CG RAM or DD RAM. 40µs CG RAM/ DD RAM Data Read 1 1 Read data Read data from CG RAM or DD RAM. 40µs I/D = 1 : Increment S = 1 : Display Shift On D = 1 : Display On C = 1 : Cursor Display On B = 1 : Cursor Blink On S/C = 1 : Shift Display R/L = 1 : Shift Right DL = 1 : 8-Bit N = 1 : Dual Line F = 1 : 5x10 dots BF = 1 : Internal Operation BF = 0 : Ready for Instruction ACG ADD I/D = 0 : Decrement DD RAM : Display Data RAM S/C R/L DL N F = 0 : Move Cursor = 0 : Shift Left = 0 : 4-Bit = 0 : Signal Line = 0 : 5x8 dots CG RAM : Character Generator RAM ACG : Character Generator RAM Address ADD : Display Data RAM Address AC : Address Counter Note 1: Symbol "*" signifies an insignificant bit (disregard). Note 2: Correct input value for "N" is predetermined for each model. 14/25 Ver 0.5 NT7603 Interface to LCD (1) Character Font and Number of Lines The NT7603 provide a 5 X 7 dot character font 1-line mode, a 5 X 10 dot character font 1-line mode and a 5 X 7 dot character font 2-line mode, as shown in the table below. Three types of common signals are available as displayed in the table. The number of lines and the font type can be selected by the program. Number of Lines Character Font Number of Common Signals Duty Factor Bias 1 5 X 7 dots + Cursor (or 5x8 dots) 8 1/8 1/4 1 5 X 10 dots + Cursor 11 1/11 1/4 2 5 X 7 dots + Cursor (or 5x8 dots) 16 1/16 1/5 (2) Connection to LCD The following 4 LCD connection examples show the various combinations between characters and lines. NT7603 can directly drive the following combinations: (a) 5 X 8 Font - 16 character X 1 line (1/8 duty cycle, 1/4 bias) LCD PANEL COM1 COM8 SEG1 NT7603 SEG80 15/25 Ver 0.5 NT7603 (b) 5 X 10 Font - 16 character X 1 line (1/11 duty cycle, 1/4 bias) LCD PANEL COM1 COM8 NT7603 SEG1 SEG80 COM11 COM9 (c) 5 X 8 Font - 16 character X 2 line (1/16 duty cycle, 1/5 bias) LCD PANEL COM1 COM8 NT7603 SEG1 SEG80 COM16 COM9 16/25 Ver 0.5 NT7603 (d) 5 X 8 Font - 32 character X 1 line (1/16 duty cycle, 1/5bias) LCD PANEL COM1 COM8 SEG1 NT7603 SEG80 COM16 COM9 (3)Orientation type of NT7603: Type1: Place the chip on the upper glass(IC face up) C1,S1 C8,S1 LCD PANEL C9,S80 C16,S80 1 NT7603 17/25 Ver 0.5 NT7603 (3) Bias Power Connection NT7603 provides 1/4 or 1/5 bias for various duty cycle applications. The built-in power division resister divide voltage is described in the following table. The division resister is The connection of NT7603, power supply, and resistors are also shown as follows: Power Division 1/8, 1/11 Duty Cycle - 1/4 Bias 1/16 Duty Cycle - 1/5 Bias V1 VDD - 1/4 VLCD VDD - 1/5 VLCD V2 VDD - 1/2 VLCD VDD - 2/5 VLCD V3 VDD - 1/2 VLCD VDD - 3/5 VLCD V4 VDD - 3/4 VLCD VDD - 4/5 VLCD V5 VDD - VLCD VDD - VLCD The bias is auto selected by duty cycle. When LCD is set to 1/16 duty, the bias is set to 1/5. Otherwise, the bias is set to 1/4. The ITO Option can select the division resister value: VDD OPT_R1 OPT_R0 No ITO (1) No ITO (1) No ITO (1) ITO On (0) ITO On (0) No ITO (1) ITO On (0) No ITO (0) VDD Division Resister è 4Kè 6.8Kè V1 2.2K V2 NT7603 V LCD Built-in bias resister 2.2K,4K or 6.8K ohm. V3 V4 V5 No built-in resister (external input) VR GND VDD VDD VDD VDD R R V1 V1 R R V2 NT7603 V2 V LCD R NT7603 V3 V LCD V3 R R V4 V4 R R V5 V5 VR VR GND GND Exit Power division. (The resistance value depends on the LCD panel size.) 18/25 Ver 0.5 NT7603 (4) LCD Waveform A-type, 1/8 Duty Cycle, 1/4 Bias 400 CLOCKS COM1 1 2 3 4 5 8 1 2 VDD V1 V2 (V3) V4 V5 1 Frame 1 Frame = 1sec × 400 × 8 = 11.9ms 270K F r a m e Frequency = 1 = 84 .3Hz 11.9ms A-type, 1/11 Duty Cycle, 1/4 Bias 400 CLOCKS COM1 1 2 3 4 5 11 1 2 VDD V1 V2 (V3) V4 V5 1 Frame 1 Frame = Frame 1sec × 400 ×11 = 16.3ms 270K Frequency = 1 16 3 = 61.4Hz A-type, 1/16 Duty Cycle, 1/5 Bias 200 CLOCKS COM1 1 2 3 4 5 16 1 2 VDD V1 V2 V3 V4 V5 1 Frame 1 Frame = Frame 1sec × 200 × 16 = 11 .9ms 270K 19/25 Frequency = 1 11 9 = 84.3Hz Ver 0.5 NT7603 B-type, 1/8 Duty Cycle, 1/4 Bias 200 CLOCKS COM1 1 2 3 4 5 6 7 8 9 16 1 2 VDD V1 V2 (V3) V4 V5 1 Frame 1 Frame = 1sec × 200 × 16 = 11. 9ms 270K F r a m e Frequency = 1 = 84 .3Hz 11.9ms B-type, 1/11 Duty Cycle, 1/4 Bias 200 CLOCKS COM1 1 2 3 4 5 6 7 8 9 10 11 12 21 22 Frequency = 1 16 3 31 32 Frequency = 1 11 9 1 2 VDD V1 V2 (V3) V4 V5 1 Frame 1 Frame = Frame 1sec × 200 × 22 = 16. 3ms 270K = 61.4Hz B-type, 1/16 Duty Cycle, 1/5 Bias 100 CLOCKS COM1 1 2 3 4 5 13 14 15 16 17 1 2 VDD V1 V2 V3 V4 V5 1 Frame 1 Frame = Frame 1sec × 100 × 32 = 11.9ms 270K 20/25 = 84 .3Hz Ver 0.5 NT7603 Application Circuit (for reference only) VDD LCD PANEL COM1~16 NT7603 SEG1~80 DB0~7 MPU E, R/W, RS V5 VR GND 21/25 Ver 0.5 NT7603 Ordering Information Part No. CG ROM Package Shipment Style NT7603BDB-01 192 CGROM (ref P12) COG CHIP FORM Bumped Die on Blue tape NT7603BDT-01 192 CGROM (ref P12) COG CHIP FORM Bumped Die on chip Tray NT7603BDW-01 192 CGROM (ref P12) COG CHIP FORM Bumped Die on Wafer 22/25 Ver 0.5 NT7603 Pad Configuration of NT7603 Chip Window: Unit: µm 2 1220 × 5010 µm A2 A1 A1 N N B1 150 M 149 N B3 84 M B1 83 M L B4 r L L r B2 L B1 M 1 166 N 66 B3 B 1 67 C1 C2 C1 C2 A1 230 C1 66 A2 5010 C2 511.55 B1 50 r 35 B2 1220 M 42 B3 70 N 90 B4 500.2 L 70 PAD Location NO. 1 2 3 4 5 6 7 8 9 10 11 12 PAD NAME GND GND GND GND GND GND GND GND GND GND GND GND X -2275 -2205 -2135 -2065 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 Y -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 NO. 13 14 15 16 17 18 19 20 21 22 23 24 23/25 PAD NAME GND GND GND OSC1 OSC2 V1 V2 V3 V4 V5 V5 V5 X -1435 -1365 -1295 -1225 -1155 -1085 -1015 -945 -875 -805 -735 -665 Y -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 Ver 0.5 NT7603 NO. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 PAD NAME V5 OPT_R0 GND OPT_R1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD RS RS RW RW E E DB[0] DB[0] DB[1] DB[1] DB[2] DB[2] DB[3] DB[3] DB[4] DB[4] DB[5] DB[5] DB[6] DB[6] DB[7] DB[7] OPT_LCD GND TESTD COM[9] COM[10] COM[11] COM[12] COM[13] X -595 -525 -455 -385 -315 -245 -175 -105 -35 35 105 175 245 315 385 455 525 595 665 735 805 875 945 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205 2275 2439 2439 2439 2439 2439 2439 2439 Y -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -540 -560 -490 -420 -350 -280 -210 -140 NO. 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 24/25 PAD NAME COM[14] COM[15] COM[16] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] X 2439 2439 2439 2439 2439 2439 2439 2439 2439 2439 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 Y -70 0 70 140 210 280 350 420 490 560 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 Ver 0.5 NT7603 NO. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 PAD NAME SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] X -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 Y 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 540 NO. 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 25/25 PAD NAME SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] TEST TESTM ALK_L ALK_R X -2065 -2135 -2205 -2275 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -2439 -1993.45 1993.45 Y 540 540 540 540 560 490 420 350 280 210 140 70 0 -70 -140 -210 -280 -350 -420 -490 -560 109.8 109.8 Ver 0.5