SED1600 CMOS 80-SEGMENT LCD DRIVER High Voltage Output • 80-bit 1/100 to 1/300 Display Duty • ■ DESCRIPTION The SED1600 is a dot matrix LCD segment (column) driver for driving a high-capacity LCD panel at duty cycles higher than 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the architecture of the SED1600, the LCD driving voltage, V0, is isolated from the VDD supply. This provides the ability to adjust the offset bias independently of VDD. These unique features allow the SED1600 to interface with a variety of LCD panels. The SED1600 does not require a controller to output an enable signal to implement daisy chain technology. This provides for easy interfacing with the LCD controllers such as the SED1330, SED1351, SED1335, or the SED1341. The SED1600 is used in conjunction with the SED1610 (86-row driver), SED1630 (68-bit row driver), SED1631 (100-row driver), SED1632 (86-bit row driver), SED1633 (100-bit row driver), and SED1634 (100bit driver) to drive a large-capacity dot matrix LCD panel. ■ FEATURES • Low-power CMOS technology • 80-bit segment (column) driver 4-bit data bus with enable chain tech• High-speed nology • Duty cycle ............................... 1/100 to 1/300 • Shift clock frequency .............. 6MHz max to adjust offset bias of the LCD source from • Ability V • Daisy chain enable support • Selectable output shift direction • No enable signal by controller is required • Wide range of LCD voltage .... –12 to –28V • Supply voltage ........................ 5.0V ± 10% • Package ..... QFP5-100 pin (F ) DD AA DIE: Al pad chip (DAA) Au bump (DAB) ■ SYSTEM BLOCK DIAGRAM D0 ~ D3 XSCL LCD CONTR LP, FR YSCL YD SED1600F (1) SED1600F (n) 80 80 n*80 SEG DUTY: 1/100 ~ 1/300 ROW DRIVER 100~300 469 SED1600 SEG0 SEG1 SEG2 SEG79 ■ BLOCK DIAGRAM VDD VSS V0 V2 V3 V5 LCD Driver 80 bit Voltage Control FR Level Shifter 80 bit LP Register 2 80 bit D0 D1 D2 D3 Data Control 4 Register 1 SHL EIO1 EIO2 ø1 ø2 Enable Control ø20 Clock Generator XSCL SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 ■ PINOUT 80 75 70 65 60 55 50 85 45 SED1600 90 40 Index 95 35 100 1 5 10 15 20 25 30 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 * EIO2 D0 D1 D2 D3 NC NC NC NC VDD VSS V0 V2 V3 V5 SHL XSCL LP FR EIO1 470 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 * NC: No Connection SED1600 ■ PIN DESCRIPTION Pin Name SEG0 to SEG79 I/O O Function LCD driving segment (column) outputs Each output changes at the falling edge of LP. D0 TO D3 I Display data inputs. XSCL I Shift clock of display data (falling edge trigger). Latch pulse of display data (falling edge trigger). LP I EI01, EI02 I/O SHL I Enable I/O, which is controlled by SHL input . Output is reset by LP, and automatically falls when 80 bits of data are taken in. Shift direction selection and EIO pin I/O control. When data (a, b, c, d) (e, f, g, h)······(w, x, y, z) are input to pins (D3, D2, D1, D0) respectively, the following relation is established between the data and segment outputs: SEG SHL EIO 79 78 77 76 75 74 73 72 ...... 3 2 1 0 1 2 L a b c d e f g h ...... w x y z Output Input H z y x w v u t s ...... d c b a Input Output FR I VDD, VSS Power Supplies AC signal of LCD driving outputs. Logic circuit power. VDD: 0 V (GND) VSS: –5.0 V V0, V2, V3, V5 Power Supplies LCD driving power. V5: –12 to –28 V VDD ≥ V0 ≥ V2 > V3 ≥ V5 ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • Parameter Supply voltage (1) Supply voltage (2) Supply voltage (2) Input voltage (1) Output voltage (1) Output current (1) Output current (2) Allowable power dissipation Operating temperature Storage temperature Soldering temperature, time (VDD = 0V) Symbol VSS V5 V0, V2, V3* VI VO IO IOSEG PD Topr Tstg Tsol Ratings –7.0 to +0.3 –30.0 to +0.3 V5 –0.3 to +0.3 VSS –0.3 to +0.3 VSS –0.3 to +0.3 20 20 300 –20 to +75 –65 to +150 260°C, 10 sec (at lead) * V0, V2 and V3 must always satisfy the condition VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5. 471 Unit V V V V V mA mA mW °C °C — SED1600 • (Unless otherwise specified, VDD = V0 = 0V, VSS = –5.0 V ± 10%, Ta = –20 to 85°C) DC Electrical Characteristics Parameter Operating voltage Recommended op. voltage Minimum operating voltage Symbol Condition VSS V5 Pin Min Typ VSS –5.5 V5 –28.0 Max Unit –5.0 –4.5 V — –12.0 V –8.0 Operating voltage — Recommended value V0 –2.5 — 0 V Operating voltage V2 Recommended value V2 3/9·V5 — V0 V Operating voltage V3 Recommended value V3 V5 — 6/9·V5 V “H” input voltage VIH 0.2VSS — — V “L” input voltage VIL EI01, EI02, XSCL, LP, D0 to D3, FR, SHL — — 0.8VSS V “H” output voltage VOH IOH = –0.6 mA –0.4 — — V “L” output voltage VOL IOL = 0.6 mA — — VSS+0.4 V ILI VSS ≤ VI ≤ 0 V XSCL, SHL, FR — — 2.0 µA ILI/O VSS ≤ VI ≤ 0 V EI01, EI02 — — 5.0 µA IDDS V5 = –12.0 to –28.0 V VIH = VDD, VIL = VSS VDD — — 25 µA — 1.5 3.5 — 2.0 4.5 — 3.0 8.0 VSS — 120 500 µA V5 — 20 100 µA — — 8.0 pF — — 15.0 pF Input leakage current Stand–by current EI01, EI02 D0 to D3, LP –20.0V Output resistance RSEG Current dissipation (1) ISSO1 Current dissipation (2) ISSO2 Input capacitance CI |∆VON| = 0.5V V5 –14.0V SEG0 to SEG79 –8.0V VSS = –5.0 V, VIH = VDD VIL = VSS, fXSCL =1.92 MHz fLP = 12 kHz, Frame period = 60 Hz; Input data: Inverted bit by bit, No-load VSS = –5.0 V, V2 = –4.0 V V3 = –16.0 V, V5 = –20.0 V All other conditions are same as ISSO1 D0 to D3, LP Ta = 25°C XSCL, SHL, FR CI/O EI01, EI02 472 kΩ SED1600 • AC Electrical Characteristics Parameter XSCL period (VSS = –5.0 V ±10%, Ta = –20 to 85°C) Symbol Conditions Min Typ Max Unit tCCL tr, tf ≤ 10 ns 166 — — ns XSCL “H” pulse width tWCLH 70 — — ns XSCL “L” pulse width tWCLL tDS tDH tLD 70 — — ns 60 — — ns 40 — — ns 0 — — ns tSL tLS tLH 70 — — ns 70 — — ns 70 — — ns LP “H” pulse width tWLPH 70 — — ns LP “L” pulse width tWLPL tDFR tsuEIH thEIH Data setup time Data hold time XSCL-rise to LP-rise time XSCL-fall to LP-fall time LP-rise to XSCL-rise time LP-fall to XSCL-fall time Allowable FR delay time Enable “H” setup time Enable “H” hold time Enable “L” setup time Enable “L” hold time Input signal rise time Input signal fall time tsuEIL thEIL tr tf 230 — — ns –500 — 500 ns 40 — — ns 0 — — ns 0 — — ns 0 — — ns — — 50* ns — — 50* ns * Note: The specifications for tr and tf are provided to prevent a malfunction which may occur when noise is mixed with a slowdown signal. To assure high-speed XSCL, both tr and tf must satisfy the following relation: tCCL – (tWCLH + tWCLL) tr, tf < 2 473 SED1600 Timing Chart • Input Timing ° FR LP XSCL 20 D0 to D3 1 2 20 1 1 2 20 1 2 2 20 1 2 3 EIO output 1 EIO output 2 1 through 3 each show a cascade number of the driver. VIH = 0.2 VSS VIL = 0.8 VSS FR tWLPH tDFR tWLPL LP tLD tLS tSL XSCL tr tf tLH tDS tWCLH tDH tCCL tWCLL D0 to D3 thEIL tsuEIH EIO1 EIO2 474 thEIH tsuEIL SED1600 ° Output Timing FR VIH = 0.2 VSS VIL = 0.8 VSS LP XSCL tpdEOLLP EIO1 EIO2 tpdEOHCL tpdEOLCL tpdSLP VOH = 0.2 VSS VOL = 0.8 VSS tpdSFR Vn –0.5V Vn +0.5V SEG output Vn = V0, V2, V3, V5 (VSS = –5.0 V ±10%, Ta = –20 to 85°C) Parameter Symbol (LP-rise to disable) time tpdEOLLP tpdEOLCL tpdEOHCL tpdSLP (XSCL-fall to disable) time (XSCL-fall to enable) time (LP-fall to SEG output) time (FR to SEG output) delay time tpdSFR Conditions XSCL = “L” LP = “H” Typ Max Unit — — 70 ns ns — — 70 — — 100 ns V5 = –12.0 to –28.0 V — — 4.5 µs CL = 100 pF — — 4.5 µs 475 CL = 15 pF Min SED1600 (for 200 × 640 DOT MATRIX LCD) YSCL 1 SHL DIO1 DIO2 FR VSS SED1630 200 × 640 DOT MATRIX 0 VSS R SED1630 0 + + R V4 + 6 V5 SED1600 R VDD 22Ω VSSH WF XSCL XD0 to XD3 6 22Ω 79 SEG 0 EIO2 1 EIO1 SHL 79 0 EIO2 2 EIO1 SHL 79 0 EIO2 8 EIO1 SHL XSCL D 0to 3 LP FR 11R V3 SED1600 + V2 YSCL 3 SHL DIO1 DIO2 FR XSCL D0 to 3 LP FR R SED1600 V1 LCD PANEL XSCL D0 to 3 LP FR V0 63 VDD 67 YSCL 2 SHL DIO1 DIO2 FR + + CONTROLLER (SED1330, SED1341) YD 67 LP COM 0 ■ EXAMPLE OF APPLICATION (SED1600) * 4 Note: * Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01µF) near pins VSS and V5 of each LSI for noise protection. 476 SED1600 ■ PAD LAYOUT / PAD COORDINATION SED1600DAA (AL PAD) • 80 75 70 65 60 55 50 85 Y 45 90 X (0,0) 40 95 35 D1600DAA 100 1 5 10 15 20 Chip Specification Chip size Pad pitch Chip thickness Pad surface area • 25 30 Dimension (mm) 5.59 × 3.50 0.160 min. 0.40 ±0.025 0.10mm No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 X (µm) –2461 –2261 –2069 –1886 –1709 –1538 –1366 –1203 –1040 –880 –720 –560 –400 –240 –80 80 240 400 560 720 880 1040 1203 1366 1538 1709 1885 2069 2261 2461 2632 2632 2632 2632 Y (µm) –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1588 –1548 –1374 –1206 –1040 No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 X (µm) 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2461 2261 2069 1885 1709 1538 1366 1203 1040 880 720 560 400 240 80 –80 –240 –400 Y Pad X (µm) No. Name (µm) –881 69 SEG68 –560 –721 70 SEG69 –720 –561 71 SEG70 –880 –401 72 SEG71 –1040 –241 73 SEG72 –1203 –81 74 SEG73 –1366 79 75 SEG74 –1538 239 76 SEG75 –1709 399 77 SEG76 –1885 559 78 SEG77 –2069 719 79 SEG78 –2261 879 80 SEG79 –2461 1039 81 EI02 –2632 1204 82 D0 –2632 1372 83 D1 –2632 1546 84 D2 –2632 1588 85 D3 –2632 1588 86 (D4) –2632 1588 87 (D5) –2632 1588 88 (D6) –2632 1588 89 (D7) –2632 1588 90 VDD –2632 1588 91 VSS –2632 1588 92 V0 –2632 1588 93 V2 –2632 1588 94 V3 –2632 1588 95 V5 –2632 1588 96 SHL –2632 1588 97 XSCL –2632 1588 98 LP –2632 1588 99 FR –2632 1588 100 EI01 –2632 1588 1588 Y (µm) 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1546 1372 1204 1039 879 719 559 399 239 79 –81 –241 –401 –561 –721 –881 –1041 –1206 –1374 –1548 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 X (µm) –2227 –2074 –1920 –1766 –1613 –1459 –1305 –1152 –998 –845 –691 –538 –384 –230 –77 77 230 384 538 691 845 998 1152 1305 1459 1613 1766 1920 2074 2227 2381 2622 2622 2622 Y (µm) –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1578 –1346 –1188 –1030 No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 X (µm) 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2381 2227 2074 1920 1766 1613 1459 1305 1152 998 845 691 538 384 230 77 –77 –230 –384 Y Pad X (µm) No. Name (µm) –871 69 SEG68 –538 –713 70 SEG69 –691 –554 71 SEG70 –845 –396 72 SEG71 –998 –238 73 SEG72 –1152 –79 74 SEG73 –1305 79 75 SEG74 –1459 238 76 SEG75 –1613 396 77 SEG76 –1766 554 78 SEG77 –1920 713 79 SEG78 –2074 871 80 SEG79 –2227 1030 81 EI02 –2381 1188 82 D0 –2622 1346 83 D1 –2622 1578 84 D2 –2622 1578 85 D3 –2622 1578 86 (D4) –2622 1578 87 (D5) –2622 1578 88 (D6) –2622 1578 89 (D7) –2622 1578 90 VDD –2622 1578 91 VSS –2622 1578 92 V0 –2622 1578 93 V2 –2622 1578 94 V3 –2622 1578 95 V5 –2622 1578 96 SHL –2622 1578 97 XSCL –2622 1578 98 LP –2622 1578 99 FR –2622 1578 100 EI01 –2381 1578 1578 Y (µm) 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1346 1193 1039 886 732 578 425 271 106 –58 –223 –388 –553 –718 –886 –1039 –1193 –1346 –1578 SED1600DAB (AU PAD) 153.6µ Pitch 75 70 65 60 55 50 Y 85 45 90 X (0,0) 40 95 35 D1600DAB 100 1 5 10 15 20 25 30 20/1 153.6µ Pitch Chip Specification Chip size Pad pitch Chip thickness Dimension (mm) 5.59 × 3.50 0.153 min. 0.525 ±0.025 158.4µ Pitch 168µ 153.6µ 164.8µ Pitch Pitch 153.6µ Pitch 80 477 THIS PAGE INTENTIONALLY BLANK 478