PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Description Features The ICS570B is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. The ICS570B, part of ICS’ ClockBlocks™ family, was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The device incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state. • Packaged in 8 pin SOIC. • Pin-for-pin replacement and upgrade to ICS570/ICS570A • Functional equivalent to AV9170 (not a pinfor-pin replacement). • Low input to output skew of 300 ps max (>60 MHz outputs). • Low skew (100 ps) outputs. • Ability to choose between 14 different multipliers from 0.5X to 32X. • Input clock frequency up to 150 MHz at 3.3V. The ICS570B is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. • Can recover degraded input clock duty cycle. • Output clock duty cycle of 45/55. • Power Down and Tri-State Mode. • Full CMOS clock swings with 25mA drive capability at TTL levels. The ICS570B was done to improve input to output jitter from the original ICS570M and ICS570A verisons, and is recommended for all new 3.3 V only designs. • Advanced, low power CMOS process. For 5V applications, use the ICS570A. • Industrial temperature version available • Operating voltage of 3.3 V (±5%). Block Diagram ICLK S1, S0 FBIN 2 divide by N Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator Output Buffer CLK Output Buffer CLK/2 ÷2 External feedback can come from CLK or CLK/2 (see table on page 2). MDS 570B A 1 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Pin Assignment S1 1 8 CLK/2 VDD 2 7 CLK GND 3 6 S0 ICLK 4 5 FBIN 8 pin 150 mil SOIC Clock Multiplier Decoding Table (Multiplies input clock by shown amount) S1 #1 0 0 0 M M M 1 1 1 S0 #6 0 M 1 0 M 1 0 M 1 FBIN from CLK FBIN from CLK/2 CLK CLK/2 CLK CLK/2 pin # 7 pin # 8 pin # 7 pin # 8 Power Down and Tri-State x3 x1.5 x6 x3 x4 x2 x8 x4 x8 x4 x16 x8 x6 x3 x12 x6 x10 x5 x20 x10 x1 ÷2 x2 x1 x16 x8 x32 x16 x2 x1 x4 x2 25°C ICLK Input Range FB from CLK/2 * (3.3V, MHz) 2.5 to 25 2.5 to 19 2.5 to 9.5 2.5 to 12.5 2.5 to 7.5 5 to 75 2.5 to 5 2.5 to 37.5 85°C ICLK Input Range FB from CLK/2 * (3.3V, MHz) 3 to 25 2.5 to 19 2.5 to 9.5 2.5 to 12.5 2.5 to 7.5 8 to 75 2.5 to 5 4.5 to 37.5 0 = connect directly to ground. M = leave unconnected (self-biases to VDD/2). 1 = connect directly to VDD. *Input range with CLK feedback is double that for CLK/2. Pin Descriptions Number 1 2 3 4 5 6 7 8 Name S1 VDD GND ICLK FBIN S0 CLK CLK/2 Type I P P CI CI I O O Description Select 1 for output clock. Connect to GND, VDD, or float per decoding table above. Connect to +3.3V. Connect to ground. Reference clock input. Feedback clock input. Select 0 for output clock. Connect to GND, VDD, or float per decoding table above. Clock output per table above. Clock output per table above. Low skew divide by two of pin 7 clock. Key: CI = clock input, I = input, O = output, P = power supply connection External Components The ICS570B requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS570B to minimize lead inductance. No external power supply filtering is required for this device. A 27 Ω series terminating resistor can be used next to each output pin. MDS 570B A 2 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Electrical Specifications Parameter Conditions ABSOLUTE MAXIMUM RATINGS (Note 1) Minimum Typical Maximum Units 7 V Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 VDD+0.5 V Clock Output Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature ICS570B 0 70 °C ICS570BI -40 85 °C Soldering Temperature Max of 10 seconds Storage temperature 260 °C -65 150 °C 3.15 3.45 V DC CHARACTERISTICS (VDD = 3.3V) Operating Voltage, VDD Input High Voltage, VIH ICLK, FBIN Input Low Voltage, VIL ICLK, FBIN 2 Input High Voltage, VIH S0, S1 Input High Voltage, VIM (mid-level) S0, S1 Input Low Voltage, VIL S0, S1 Output High Voltage, VOH, CMOS level IOH=-4mA VDD-0.4 Output High Voltage, VOH IOH=-12mA 2.4 Output Low Voltage, VOL IOL=12mA IDD Operating Supply Current, 50 in, 100 out No Load, 3.3V Short Circuit Current Each Output V 0.8 VDD-0.5 V VDD/2 V 0.5 V V V 0.4 Input Capacitance, S1, S0 V V 16 mA ±100 mA 5 pF AC CHARACTERISTICS (VDD = 3.3V) Input Frequency, ICLK (see table on page 2) FBIN from CLK/2 Output Clock Frequency, CLK See Table on Page 2 10 MHz 175 ps Output to output skew Note 2 Input to Output Jitter 40-150 MHz Input skew, ICLK to FBIN Note 2 CLK>30MHz -300 300 ps Input skew, ICLK to FBIN Note 2 VDD=3.3V, CLK<10MHz -600 600 ps Output Clock Rise Time, 3.3V 0.8 to 2.0V, note 3 0.75 ns Output Clock Fall Time, 3.3V 2.0 to 0.8V, note 3 0.75 ns Output Clock Duty Cycle at VDD/2 Notes 100 150 100-250 45 49 to 51 ps 55 % 1. Stresses beyond these can permanently damage the device 2. Assumes clocks with same rise time, measured from rising edges at VDD/2. 3. With 27 Ω terminating resistor and 15 pF loads. MDS 570B A 3 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Clock Period Jitter Tables All jitter values are considered typical measured at 25°C with 27Ω series termination resistor and 15pF loads on both CLK and CLK2. The feedback is from CLK2 to FBIN. Note that if an output is unused, it should be left unconnected to improve output jitter on the active output clocks. Absolute and One Sigma Jitter (ps), VDD = 3.3V S1 0 0 M M M 1 1 1 S0 M 1 0 M 1 0 M 1 CLKIN (MHz) 8.333 6.25 3.125 4.167 2.5 25 1.5625 12.5 CLK = 50M MultiplierAbsolute 1 sigma 6x ±110 80 8x ±125 90 16x ±130 90 12x ±120 90 20x ±115 90 2x ±130 50 32x ±120 90 4x ±120 60 CLK/2 = 25M Multiplier Absolute 1 3x ±55 4x ±50 8x ±55 6x ±55 10x ±55 1x ±55 16x ±55 2x ±55 sigma 20 20 20 20 20 20 20 20 CLK/2 = 50M Multiplier Absolute 1 3x ±45 4x ±45 8x ±45 6x ±45 10x ±40 1x ±40 16x ±45 2x ±60 sigma 20 20 20 20 20 20 20 30 CLK/2 = 75M Multiplier Absolute 1 3x ±50 4x ±50 8x ±50 6x ±45 10x ±45 1x ±45 16x ±50 2x ±60 sigma 20 20 20 20 20 20 20 20 Absolute and One Sigma Jitter (ps), VDD = 3.3V S1 0 0 M M M 1 1 1 S0 M 1 0 M 1 0 M 1 CLKIN (MHz) 16.667 12.5 6.25 8.333 5 50 3.125 25 CLK = 100M MultiplierAbsolute 1 sigma 6x ±100 70 8x ±100 70 16x ±110 80 12x ±100 70 20x ±105 70 2x ±90 60 32x ±95 70 4x ±105 70 Absolute and One Sigma Jitter (ps), VDD = 3.3V S1 0 0 M M M 1 1 1 S0 M 1 0 M 1 0 M 1 CLKIN CLK = 150M (MHz) MultiplierAbsolute 1 sigma 25 6x ±115 70 18.375 8x ±120 80 9.375 16x ±130 90 12.5 12x ±130 90 7.5 20x ±130 90 75 2x ±115 90 4.6875 32x ±130 90 37.5 4x ±110 70 MDS 570B A 4 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Recommended Circuit: S1 CLK VDD CLK/2 GND S0 INPUT FBIN ICLK ICK CLK CLK CLK/2 CLK/2 x2 Mode (S1, S0 = 1, 1) CLK Feedback x2 Mode (S1, S0 = 1, 0) CLK/2 Feedback Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the CLK/2 could be a falling edge compared with ICLK. Therefore, whenever possible, we recommend the use of CLK/2 feedback. This will synchronize the rising edges of all 3 clocks. MDS 570B A 5 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com PRELIMINARY INFORMATION ICS570B Multiplier and Zero Delay Buffer Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) 8 pin (150 mil) SOIC E H INDEX AREA h x 45° D A1 C e B Symbol A A1 B C D E e H h L Inches Min Max 0.0532 0.0688 0.004 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 A L Ordering Information Part/Order Number ICS570B ICS570BT ICS570BI ICS570BIT Marking ICS570B ICS570B ICS570BI ICS570BI Package/Comments 8 pin SOIC 8 pin SOIC on tape and reel 8 pin SOIC 8 pin SOIC on tape and reel Temperature 0 to 70 °C 0 to 70 °C -40 to +85 °C -40 to +85 °C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ClockBlocks is a trademark of ICS MDS 570B A 6 Revision 053001 Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com