PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Description Features The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. ICS introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570. The ICS571, part of ICS’ ClockBlocks™ family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. • Packaged in 8 pin SOIC. • Can function as low phase noise x2 multiplier. • Low skew outputs. One is ÷2 of other. • Input clock frequency up to 160 MHz at 3.3V. • Phase noise of better than -100 dBc/Hz from 1kHz to 1MHz offset from carrier • Can recover poor input clock duty cycle. • Output clock duty cycle of 45/55 at 3.3V. • High drive strength for >100 MHz outputs. • Full CMOS clock swings with 25mA drive capability at TTL levels. • Advanced, low power CMOS process. • Operating voltages of 3.0 to 5.5 V. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the ICS571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two. Block Diagram ICLK FBIN Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator Output Buffer CLK Output Buffer CLK/2 ÷2 External feedback can come from CLK or CLK/2 (see table on page 2). 1 Revision 072899 Printed 11/14/00 Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax MDS 571 B PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Pin Assignment ICLK 1 8 FBIN VDD 2 7 CLK GND 3 6 VDD CLK/2 4 5 GND Feedback Configuration Table and Frequency Ranges (at 3.3V) Feedback From CLK CLK Input clock frequency CLK/2 2xInput clock frequency CLK/2 Input clock frequency/2 Input clock frequency Input Range 20 -160 MHz 10 - 80 MHz Pin Descriptions Number 1 2 3 4 5 6 7 8 Name ICLK VDD GND CLK/2 GND VDD CLK FBIN Type CI P P O P P O CI Description Reference clock input. Connect to +3.3V or +5V. Must be same as other VDD. Connect to ground. Clock output per Table above. Low skew divide by two of pin 7 clock. Connect to ground. Connect to +3.3V or +5V. Must be same as other VDD. Clock output per Table above. Feedback clock input. Connect to CLK or CLK/2 per table above. Key: CI = clock input, I = input, O = output, P = power supply connection External Components The ICS571 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND on each side of the chip (between pins 2 and 3, and also between pins 6 and 5). They must be connected close to the ICS571 to minimize lead inductance. No external power supply filtering is required for this device. A 33 Ω terminating resistor can be used next to each output pin. 2 Revision 072899 Printed 11/14/00 Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax MDS 571 B PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Electrical Specifications Parameter Conditions ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND Clock Output Referenced to GND Ambient Operating Temperature Soldering Temperature Max of 10 seconds Storage temperature DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted) Operating Voltage, VDD Input High Voltage, VIH, ICLK, FBIN Pins 1, 8 Input Low Voltage, VIL, ICLK, FBIN Pins 1, 8 Output High Voltage, VOH, CMOS level IOH=-4mA Output High Voltage, VOH IOH=-25mA Output Low Voltage, VOL IOL=25mA IDD Operating Supply Current, 133 in, 133 out No Load, 3.3V IDD Operating Supply Current, 50 in, 100 out No Load, 3.3V Short Circuit Current Each Output Input Capacitance, ICLK, FBIN AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted) Input Frequency, clock input FB from CLK Input Frequency, clock input FB from CLK/2 Skew CLK/2 with respect to CLK Note 2 Input clock to output connected to FBIN Note 2 Output Clock Rise Time, 5V 0.8 to 2.0V, 15 pF load Output Clock Fall Time, 5V 2.0 to 0.8V, 15 pF load Output Clock Rise Time, 3.3V 0.8 to 2.0V, 15 pF load Output Clock Fall Time, 3.3V 2.0 to 0.8V, 15 pF load Output Clock Duty Cycle, 5V at VDD/2 Output Clock Duty Cycle, 3.3V at VDD/2 Absolute Clock Period Jitter, CLK, note 3 Deviation from mean One Sigma Clock Period Jitter, CLK, note 3 Phase Noise, relative to carrier 1kHz offset Phase Noise, relative to carrier 100kHz offset Notes: Minimum Typical -0.5 -0.5 0 -65 3 VDD/2+1 VDD/2 VDD/2 Maximum Units 7 VDD+0.5 VDD+0.5 70 260 150 V V V °C °C °C 5.5 V V V V V V mA mA mA pF VDD/2-1 VDD-0.4 2.4 0.4 34 26 ±100 5 20 10 150 -500 40 45 500 0.3 0.4 0.45 0.55 52 to 55 49 to 51 ±80 50 -105 -115 160 80 850 500 60 55 MHz MHz ps ps ns ns ns ns % % ps ps dBc/Hz dBc/Hz 1. Stresses beyond these can permanently damage the device. 2. Assumes clocks with same rise time, measured from rising edges at VDD/2. Measured with 33Ω termination resistors and 15 pF loads. Applies to both 3.3V and 5V operation. 3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK. 3 Revision 072899 Printed 11/14/00 Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax MDS 571 B PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Package Outline and Package Dimensions 8 pin SOIC E H Pin 1 h x 45° D Q A c e b L Symbol A b D E H e h L Q Inches Min Max 0.055 0.068 0.013 0.019 0.185 0.200 0.150 0.160 0.225 0.245 .050 BSC 0.015 0.016 0.035 0.004 0.01 Millimeters Min Max 1.397 1.7272 0.330 0.483 4.699 5.080 3.810 4.064 5.715 6.223 1.27 BSC 0.381 0.406 0.889 0.102 0.254 Ordering Information Part/Order Number ICS571M ICS571MT Marking ICS571M ICS571M Package 8 pin SOIC 8 pin SOIC on tape and reel Temperature 0 to 70 °C 0 to 70 °C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ClockBlocks is a trademark of ICS 4 Revision 072899 Printed 11/14/00 Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax MDS 571 B