ICS ICS83115

ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83115 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83115 single ended
clock input accepts LVCMOS or LVTTL input levels. The ICS83115 operates at full 3.3V supply mode over the
commercial temperature range. Guaranteed output and part-topart skew characteristics make the ICS83115 ideal for those
clock distribution applications demanding well defined performance and repeatability.
• 16 LVCMOS/LVTTL outputs
ICS
• 1 LVCMOS/LVTTL clock input
• Maximum output frequency: 200MHz
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Additive phase jitter, RMS: 0.09ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
OE2
PIN ASSIGNMENT
VDD
Q0
Q15
Q1
Q14
Q2
Q13
Q3
Q12
Q4
Q11
Q5
Q10
Q6
Q9
Q7
Q8
OE1
IN
83115BR
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE2
Q15
Q14
Q13
VDD
VDD
Q12
Q11
GND
GND
Q10
Q9
Q8
OE0
OE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.7mm body package
R Package
(Top View)
4
OE1
OE1
Q0
Q1
Q2
VDD
VDD
Q3
Q4
GND
GND
Q5
Q6
Q7
IN
OE0
OE2
4
OE0
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1
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
OE1
2, 3, 4, 7,
8, 11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
5, 6, 23, 24
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7,
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
VDD
9, 10, 19, 20
14
Input
Pullup
Description
Output enable. When LOW, forces outputs Q2 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
Output
Power
Core supply pin.
GND
Power
Power supply ground.
IN
Input
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Output enable. When LOW, forces outputs Q8 thru Q13 to
15
OE0
Input
Pullup
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When LOW, forces outputs Q0, Q1, Q15 and Q14 to
28
OE2
Input
Pullup
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Test Conditions
RPULLUP
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
RPULLDOWN
Input Pulldown Resistor
ROUT
Output Impedance
C PD
Minimum
Typical
VDD = 3.465V
VDD = 3.3V
5
Maximum
Units
4
pF
11
pF
51
KΩ
51
KΩ
7
12
Ω
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Q2:Q7
(Control OE1)
HiZ
OE 0
OE1
OE2
0
0
0
Q0, Q1, Q14, Q15
(Control OE2)
HiZ
Q8:Q13
(Control OE0)
HiZ
0
0
1
Active
HiZ
HiZ
0
1
0
HiZ
Active
HiZ
0
1
1
Active
Active
HiZ
1
0
0
HiZ
HiZ
Active
1
0
1
Active
HiZ
Active
1
1
0
HiZ
Active
Active
1
1
1
Active
Active
Active
NOTE: OE0:OE2 are 5V tolerant.
83115BR
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2
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
49°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0° TO 70°C
Symbol
Parameter
VDD
Power Supply Voltage
Test Conditions
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
50
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0° TO 70°C
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
OE0:OE2
IN
Minimum
Maximum
Units
2
Typical
VDD + 0.3
V
2
VDD + 0.3
V
OE0:OE2
-0.3
0.8
V
IN
-0.3
1.3
V
OE0:OE2
VDD = VIN = 3.465V
5
µA
IN
VDD = VIN = 3.465V
150
µA
OE0:OE2
VDD = 3.465V, VIN = 0V
-150
µA
IN
VDD = 3.465V, VIN = 0V
-5
µA
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IOZL
IOZH
2.6
V
0.5
V
Output HiZ Current Low
5
µA
Output HiZ Current High
5
µA
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
83115BR
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3
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0° TO 70°C
Symbol Parameter
fMAX
Output Frequency
tpLH
Propagation Delay; NOTE 1
Test Conditions
IJ 200MHz
Minimum
1.7
Typical
2.4
Maximum
Units
200
MHz
3.1
ns
Integration Range:
12KHz - 20MHz
0.09
t sk(o)
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Skew; NOTE 2, 4
Measured on rising edge @VDD/2
150
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Measured on rising edge @VDD/2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
55
%
tEN
Output Enable Time
20
ns
tDIS
Output Disable Time
20
ns
t jit(Ø)
20% to 80%
650
45
ps
250
ps
800
ps
1150
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83115BR
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4
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Additive Phase Jitter, RMS
-20
@ 155.52MHz (12KHz to 20MHz)
= 0.09ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
83115BR
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5
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD
Qx
VDD
2
Qx
LVCMOS
VDD
2
Qy
GND
t sk(b)
-1.65V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
Part 1
Qx
OUTPUT SKEW
VDD
2
V
DD
CLK
2
Part 2
VDD
2
V
DD
Qy
Q0:Q15
2
t sk(pp)
t
PD
PROPAGATION DELAY
PART-TO-PART SKEW
V
DD
80%
80%
2
Q0:Q15
Pulse Width
Clock
Outputs
20%
20%
tR
t
PERIOD
tF
odc =
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
83115BR
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6
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
28 LEAD SSOP, 150MIL
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
49°C/W
36°C/W
30°C/W
NOTE: Most modern PCB designs use multi-layered boards.
TRANSISTOR COUNT
The transistor count for ICS83115 is: 985
83115BR
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7
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - R SUFFIX
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
FOR
28 LEAD SSOP, 150 MIL
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
28
A
1.35
1.75
A1
0.10
0.25
A2
1.50
b
0.20
0.30
c
0.18
0.25
D
9.80
10.00
E
5.80
6.20
E1
3.80
4.00
e
0.635 BASIC
L
0.40
1.27
α
0°
8°
ZD
0.84 REF
Reference Document: JEDEC Publication 95, MO-137
83115BR
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8
REV. A SEPTEMBER 21, 2004
ICS83115
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83115BR
ICS83115BRT
ICS83115BRLF
ICS83115BRLFT
Marking
ICS83115BR
ICS83115BR
ICS83115BRLF
ICS83115BRLF
Package
28 Lead SSOP
28 Lead SSOP on Tape and Reel
28 Lead "Lead Free" SSOP
28 Lead "Lead Free" SSOP on Tape and Reel
Count
48 per tube
2500
48 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
83115BR
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9
REV. A SEPTEMBER 21, 2004