ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8305I is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. • 4 LVCMOS/LVTTL outputs ICS • Selectable differential or LVCMOS/LVTTL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • Maximum output frequency: 350MHz • Output skew: 40ps (maximum) • Part-to-part skew: 700ps (maximum) Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well defined performance and repeatability. • Additive phase jitter, RMS: 0.04ps (typical) • 3.3V core, 3.3V, 2.5V or 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant BLOCK DIAGRAM CLK_EN PIN ASSIGNMENT GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK D Q LE LVCMOS_CLK CLK nCLK 00 1 Q0 1 Q1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q0 VDDO Q1 GND Q2 VDDO Q3 GND CLK_SEL ICS8305I Q2 16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View Q3 OE 8305AGI www.icst.com/products/hiperclocks.html 1 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 9, 13 GND Power 2 OE Input 3 VDD Power 4 CLK_EN Input 5 CLK Input 6 nCLK Input 7 CLK_SEL Input 8 LVCMOS_CLK Input 10, 12, 14, 16 Q3, Q2, Q1, Q0 Output Clock outputs. LVCMOS / LVTTL interface levels. 11, 15 VDDO Power Output supply pins. Power supply ground. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Core supply pin. Synchronizing clock enable. When LOW, the output clocks are Pullup disabled. When HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Clock select input. When HIGH, selects CLK, nCLK inputs. Pullup When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 kΩ 11 pF CPD ROUT 8305AGI 5 www.icst.com/products/hiperclocks.html 2 7 12 Ω REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Selected Source LVCMOS_CLK Outputs Q0:Q3 Disabled; LOW 1 CLK, nCLK Disabled; LOW 1 0 LVCMOS_CLK Enabled 1 1 CLK, nCLK Enabled OE 1 CLK_EN 0 1 0 1 1 Inputs CLK_SEL 0 0 X X HiZ NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. Enabled Disabled nCLK CLK, LVCMOS_CLK CLK_EN Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM 8305AGI www.icst.com/products/hiperclocks.html 3 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.65 1.8 1.95 V 21 5 mA mA Output Supply Voltage Power Supply Current Output Supply Current TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units CLK_EN, CLK_SEL, OE 2 VDD + 0.3 V LVCMOS_CLK 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V 5 µA 150 µA VIH Input High Voltage VIL Input Low Voltage IIH Input High Current CLK_EN, CLK_SEL, OE VDD = VIN = 3.465V LVCMOS_CLK VDD = VIN = 3.465V IIL Input Low Current CLK_EN, CLK_SEL, OE VDD = 3.465V, VIN = 0V -150 µA LVCMOS_CLK VDD = 3.465V, VIN = 0V -5 µA VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1. 8 V VDDO = 1.8V ± 0.15V VDDO - 0.3 V VOH VOL CLK_EN, CLK_SEL, OE LVCMOS_CLK Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 IOZL Output Tristate Current Low IOZH Output Tristate Current High VDDO = 3.3V ± 5% 0.5 V VDDO = 2.5V ± 5% 0.5 V VDDO = 1.8V ± 0.15V 0.4 V -5 µA 5 µA NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. 8305AGI www.icst.com/products/hiperclocks.html 4 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units nCLK VIN = VDD = 3.465V Test Conditions Minimum Typical 150 µA CLK VIN = VDD = 3.465V 150 µA nCLK VIN = 0V, VDD = 3.465V -150 µA CLK VIN = 0V, VDD = 3.465V -5 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 1.3 V VDD - 0.85 V TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) Test Conditions Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 tR / tF Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time o dc Output Duty Cycle tEN Output Enable Time; NOTE 4 tjit Minimum Typical Maximum Units Ref = CLK/nCLK 350 MHz Ref = LVCMOS_CLK 300 MHz 2.8 ns 40 ps 700 ps 1.75 Measured on the Rising Edge 0.04 20% to 80% 100 ƒ≤ 200MHz 45 55 % ƒ > 200MHz 42 58 % 5 ns 5 ns Output Disable Time; NOTE 4 tDIS NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 8305AGI ps www.icst.com/products/hiperclocks.html 5 700 ps REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit tR / tF Test Conditions Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time o dc Output Duty Cycle tEN Output Enable Time; NOTE 4 Maximum Units Ref = CLK/nCLK Minimum Typical 350 MHz Ref = LVCMOS_CLK 300 MHz 2.95 ns 40 ps 800 ps 1.75 Measured on the Rising Edge 0.04 ps 20% to 80% 100 700 ps ƒ≤ 166MHz 45 55 % f > 166MHz 42 58 % 5 ns Output Disable Time; NOTE 4 5 ns tDIS NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± -0.15V, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH t sk(o) t sk(pp) Test Conditions Output Frequency LVCMOS_CLK; Propagation Delay, NOTE 1A Low to High CLK, nCLK; NOTE 1B Output Skew; NOTE 2, 6 tR / tF Par t-to-Par t Skew; NOTE 3, 6 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time o dc Output Duty Cycle tEN tDIS tjit Minimum Typical Maximum Units Ref = CLK/nCLK 350 MHz Ref = LVCMOS_CLK 300 MHz 3.7 ns 45 ps 900 ps 1.75 Measured on the Rising Edge 0.04 ps 20% to 80% 100 700 ps ƒ≤ 166MHz 45 55 % f > 166MHz 42 58 % Output Enable Time; NOTE 4 5 ns Output Disable Time; NOTE 4 5 ns For notes, see Table 5B. 8305AGI www.icst.com/products/hiperclocks.html 6 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 Input/Output Additive Phase Jitter at 155.52MHz -10 -20 = 0.04ps typical -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 8305AGI www.icst.com/products/hiperclocks.html 7 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% 2.05V±5% SCOPE VDD, VDDO VDDO Qx LVCMOS SCOPE VDD Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.4V±0.09V 0.9V±0.075V VDD SCOPE VDD VDDO nCLK V Qx LVCMOS Cross Points PP V CMR CLK GND GND -0.9V±0.075V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 V DDO Qx Qx 2 DDO 2 Qy 2 tsk(o) OUTPUT SKEW 8305AGI DDO PART 2 V Qy V V DDO 2 tsk(pp) PART-TO-PART SKEW www.icst.com/products/hiperclocks.html 8 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER VDD 2 LVCMOS_CLK 80% 80% tR tF nCLK Clock Outputs CLK 20% 20% VDDO 2 Q0:Q3 t PD ➤ ➤ PROPAGATION DELAY OUTPUT RISE/FALL TIME V DDO 2 Q0:Q3 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8305AGI www.icst.com/products/hiperclocks.html 9 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8305AGI www.icst.com/products/hiperclocks.html 10 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8305AGI BY www.icst.com/products/hiperclocks.html 11 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER SCHEMATIC EXAMPLE This application note provides general design guide using ICS8305I LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305I LVCMOS clock buffer. In this example, the input is driven by an LVCMOS driver. CLK_EN is set at logic low to select LVCMOS_CLK input. VDD Zo = 50 VDD R1 43 R4 1K R5 1K U1 1 2 3 4 5 6 7 8 VDD Zo = 50 Ro ~ 7 Ohm R3 GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK Q0 VDDO Q1 GND Q2 VDDO Q3 GND 16 15 14 13 12 11 10 9 LVCMOS Receiv er Zo = 50 R2 43 43 R6 1K 3,.3V LVCMOS ICS8305 (U1,3) (U1,11) (U1,15) C1 C2 C3 0.1u 0.1u 0.1u VDD VDD=3.3V LVCMOS Receiv er FIGURE 4. EXAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8305I is: 459 8305AGI www.icst.com/products/hiperclocks.html 12 REV. B MAY 19, 2005 ICS8305I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8305AGI www.icst.com/products/hiperclocks.html 13 REV. B MAY 19, 2005 Integrated Circuit Systems, Inc. ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number ICS8305AGI ICS8305AGIT ICS8305AGILF ICS8305AGILFT NOTE: Par ts that are ordered Marking Package Shipping Packaging Temperature 8305AGI 16 Lead TSSOP tube -40°C to 85°C 8305AGI 16 Lead TSSOP 2500 tape & reel -40°C to 85°C 8305AGIL 16 Lead "Lead-Free" TSSOP tube -40°C to 85°C 8305AGIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8305AGI www.icst.com/products/hiperclocks.html 14 REV. B MAY 19, 2005 Integrated Circuit Systems, Inc. ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page A T8 14 T5A - T5C B T1 5&6 7 2 B T8 14 B 8305AGI Description of Change Ordering Information table - corrected Par t/Order Number typo from ICS88305AGIT to ICS8305AGIT. AC Characteristics Tables - changed tjit from 0.05ps typical to 0.04ps typical. Updated Additive Phase Jitter plot. Pin Description Table - corrected CLK_EN description. Ordering Information Table - added Lead-Free par t number www.icst.com/products/hiperclocks.html 15 Date 1/20/04 2/26/04 12/7/04 5/19/05 REV. B MAY 19, 2005