PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8344 is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. ICS8344 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. • 24 LVCMOS outputs, 7Ω typical output impedance ,&6 • Output frequency up to 167MHz • 275ps output skew, 600ps part to part skew • Translates any differential input signal (PECL, HSTL, LVDS) to LVCMOS without external bias networks • Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input • Translates and inverts any single-ended input signal to LVCMOS with resistor bias on CLK input • Multiple differential clock input pairs for redundant clock applications Guaranteed output and part-to-part skew characteristics make the ICS8344 ideal for those clock distribution applications demanding well defined performance and repeatability. • LVCMOS control inputs • Multiple output enable pins for disabling unused outputs in reduced fanout applications • 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes • 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch • 0°C to 70°C ambient operating temperature • Industrial temperature versions available upon request BLOCK DIAGRAM PIN ASSIGNMENT Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15 CLK_SEL CLK0 nCLK0 0 CLK1 nCLK1 1 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23 Q0 - Q7 OE1 O8 - Q15 OE2 O16 - Q23 OE3 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8344 Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0 OE1 OE2 OE3 CLK0 nCLK0 VDDI GND CLK1 nCLK1 VDDI GND CLK_SEL 48-Lead LQFP Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8344 www.icst.com REV. B FEBRUARY 2, 2001 1 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 5, 6 7, 8, 11, 12 Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 Output Q15 thru Q23 outputs. 7Ω typical output impedance. VDDO Power Output power supply. Connect 3.3V or 2.5V. GND Power Power supply ground. Connect to ground. CLK_SEL Input 15, 19 VDDI Power 16 nCLK1 Input 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 Type 17 CLK1 Input 20 nCLK0 Input 21 CLK0 Input 22 OE3 Input 23 OE2 Input 24 OE1 Input 25, 26, 29, 30 31, 32, 35, 36 37, 38, 41, 42 43, 44, 47, 48 Q0, Q1, Q2, Q3 Q4, Q5, Q6, Q7 Q8, Q9, Q10, Q11 Q12, Q13, Q14, Q15 Description Pulldown Pullup Clock select input. Selects between CLK0, nCLK0 and CLK1, nCLK1 as the differential pair that controls the output. Input power supply. Connect 3.3V or 2.5V. Inver ting input of secondar y differential clock input pair. Pulldown Non-inver ting input of secondar y differential clock input pair. Pullup Inver ting input of primar y differential clock input pair. Pulldown Non-inver ting input of primar y differential clock input pair. Output enable. Controls enabling and disabling of outputs Pullup Q16 thru Q23. Output enable. Controls enabling and disabling of outputs Pullup Q8 thru Q15. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q7. Output Q0 thru Q7 outputs. 7Ω typical output impedance. Output Q8 thru Q15 outputs. 7Ω typical output impedance. TABLE 2. PIN CHARACTERISTICS Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical CLK0, nCLK0, CLK1, nCLK1 CLK_SEL, OE1, OE2, OE3 Maximum Units pF pF VDDI, VDDO = 3.465V VDDI = 3.465V, VDDO = 2.625V VDDI, VDDO = 2.625V pF CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω 8344 www.icst.com 2 pF pF REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Bank 1 Bank 2 Bank 3 Input Output Input Output Input Output OE1 Q0-Q7 OE2 Q8-Q15 OE3 Q16-Q23 0 Hi-Z 0 Hi-Z 0 Hi-Z 1 Active 1 Active 1 Active TABLE 3B. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK_SEL CLK0, nCLK0 CLK1, nCLK1 0 Selected De-selected 1 De-selected Selected TABLE 3C. CLOCK INPUTS FUNCTION TABLE Inputs OE1, OE2, OE3 CLK Outputs nCLK Q0 thru Q23 Input to Output Mode Polarity 1 0 1 LOW Differential to Single Ended Non Inver ting 1 1 0 HIGH Differential to Single Ended Non Inver ting 1 0 Biased; NOTE 1 LOW Single Ended to Differential Non Inver ting 1 1 Biased; NOTE 1 HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 0 HIGH Single Ended to Differential Inver ting 1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is VDDI/2. 8344 www.icst.com 3 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0°C to 70°C -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDDI Input Power Supply Voltage VDDO Output Power Supply Voltage IDDI Test Conditions Quiescent Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V 120 mA Maximum Units 5 µA 150 µA VDDI = VIH = 3.465V VIL = 0V TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 µA -5 µA NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table. TABLE 4C. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage VOL Output Low Voltage 8344 CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL Test Conditions Minimum VDDI = 3.465V VDDI = 3.135V Maximum Units 2 3.8 V -0.3 0.8 V 5 µA 150 µA VDDI = VIN = 3.465V VDDI = VIN = 3.465V Typical OE1, OE2, OE3 VDDI = 3.465, VIN = 0V -150 µA CLK_SEL VDDI = 3.465, VIN = 0 VDDI = VDDO = 3.135V IOH = -36mA VDDI = VDDO = 3.135V IOL = 36mA -5 µA 2.6 V www.icst.com 4 0.6 V REV. B FEBRUARY 2, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8344 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Maximum Input Frequency VPP Peak-to-Peak Input Voltage f = 167MHz VCMR Common Mode Input Voltage tpLH Minimum Typical Maximum Units 167 MHz 0.3 1.3 V f = 167MHz 0.9 2 V Propagation Delay, Low-to-High 0MHz ≤ f ≤ 167MHz 2.6 4.3 ns tpHL Propagation Delay, High-to-Low 0MHz ≤ f ≤ 167MHz 2.4 4.3 ns tsk(b) Bank Skew; NOTE 2 Measured on the rising edge of VDDO/2 150 ps tsk(o) Output Skew; NOTE 3 Measured on the rising edge of VDDO/2 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4 Measured on the rising edge of VDDO/2 600 ps tR Output Rise Time; NOTE 5 30% to 70% 1000 ps tF Output Fall Time; NOTE 5 30% to 70% 200 1000 ps 0MHz ≤ f ≤ 167MHz tCYCLE/2- 0.65 tCYCLE/2 tCYCLE/2 + 0.65 ns f = 167MHz 2.35 2.5 3.65 ns tPW Output Pulse Width 200 tEN Output Enable Time; NOTE 5 f = 66.7MHz 5 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 4 ns NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50Ω to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. 8344 www.icst.com 5 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VDDI Input Power Supply Voltage VDDO Output Power Supply Voltage IDDI Test Conditions Quiescent Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V 120 mA Maximum Units 5 µA 150 µA VDDI = VIH = 3.465V VIL = 0V TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 µA -5 µA NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table. TABLE 4F. LVCMOS DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage VOL Output Low Voltage 8344 Test Conditions Minimum Typical Maximum Units VDDI = 3.465V 2 3.8 V VDDI = 3.465V -0.3 .8 V CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 VDDI = VIN = 3.465V 5 µA CLK_SEL VDDI = VIN = 3.465V 150 µA OE1, OE2, OE3 CLK_SEL VDDI = 3.465, VIN = 0V -150 µA VDDI = 3.465, VIN = 0 VDDI = 3.135V, VDDO = 2.375V IOH = -36mA VDDI = 3.135V, VDDO = 2.365V IOL = 27mA -5 µA 1.8 V www.icst.com 6 0.63 V REV. B FEBRUARY 2, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8344 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Maximum Input Frequency VPP Peak-to-Peak Input Voltage f = 167MHz VCMR Common Mode Input Voltage tpLH Maximum Units 167 MHz 0.3 1.3 V f = 167MHz 0.9 2 V Propagation Delay, Low-to-High 0MHz ≤ f ≤ 167MHz 2.6 4.5 ns tpHL Propagation Delay, High-to-Low 0MHz ≤ f ≤ 167MHz 2.6 4.2 ns tsk(b) Bank Skew; NOTE 2 Measured on the rising edge of VDDO/2 150 ps tsk(o) Output Skew; NOTE 3 Measured on the rising edge of VDDO/2 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4 Measured on the rising edge of VDDO/2 600 ps tR Output Rise Time; NOTE 5 30% to 70% 300 1700 ps tF Output Fall Time; NOTE 5 30% to 70% 300 1400 ps tP W Output Pulse Width tCYCLE/2 + 0.65 ns 3.65 ns 0MHz ≤ f ≤ 167MHz f = 167MHz Minimum Typical tCYCLE/2 tCYCLE/2 - 0.65 2.35 tEN Output Enable Time; NOTE 5 f = 66.7MHz 6 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50Ω to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. 8344 www.icst.com 7 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VDDI Input Power Supply Voltage VDDO Output Power Supply Voltage IDDI Test Conditions Quiescent Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 2.375 2.5 2.625 V 120 mA Maximum Units 5 µA 150 µA VDDI = VIH = 3.465V VIL = 0V TABLE 4H. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 -150 µA -5 µA NOTE: For CLKx, nCLKx input levels, see VPP and VCMR in AC Characteristics table. TABLE 4I. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage VOL Output Low Voltage 8344 CLK_SEL, OE1, OE2, OE3 CLK_SEL, OE1, OE2, OE3 OE1, OE2, OE3 CLK_SEL Test Conditions Minimum VDDI = 2.625V VDDI = 2.375V Maximum Units 2 2.9 V -0.3 0.8 V 5 µA 150 µA VDDI = VIN = 2.625V VDDI = VIN = 2.625V Typical OE1, OE2, OE3 VDDI = 2.625, VIN = 0V -150 µA CLK_SEL VDDI = 2.625, VIN = 0 VDDI = VDDO = 2.375V IOH = -27mA VDDI = VDDO = 2.375V IOL = 27mA -5 µA 1.77 V www.icst.com 8 0.6 V REV. B FEBRUARY 2, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8344 LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5C. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 167 MHz fMAX Maximum Input Frequency VPP Peak-to-Peak Input Voltage f = 167MHz 0.3 1.3 V VCMR Common Mode Input Voltage f = 167MHz 0.9 2 V tpLH Propagation Delay, Low-to-High 0MHz ≤ f ≤ 167MHz 2.7 4.3 ns tpHL Propagation Delay, High-to-Low 0MHz ≤ f ≤ 167MHz 2.7 4.3 ns tsk(b) Bank Skew; NOTE 2 Measured on the rising edge of VDDO/2 150 ps tsk(o) Output Skew; NOTE 3 Measured on the rising edge of VDDO/2 275 ps tsk(pp) Par t-to-Par t Skew; NOTE 4 Measured on the rising edge of VDDO/2 600 ps tR Output Rise Time; NOTE 5 30% to 70% 300 1700 ps tF Output Fall Time; NOTE 5 30% to 70% 300 1400 ps tPW Output Pulse Width 0MHz ≤ f ≤ 167MHz tCYCLE/2 - 0.65 tCYCLE/2 + 0.65 ns f = 167MHz 2.35 3.65 ns tCYCLE/2 tEN Output Enable Time; NOTE 5 f = 66.7MHz 6 ns tDIS Output Disable TIme; NOTE 5 f = 66.7MHz 6 ns NOTE 1: All parameters measured at 167MHz and VPPmin unless noted otherwise. All outputs terminated with 50 Ω to VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the skew at different outputs on different devices operating at the same supply voltages with equal load conditions. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. 8344 www.icst.com 9 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS VDDI CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 1A - LVDS, HSTL DIFFERENTIAL INPUT LEVELS VDDI CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL VDDI CLK or nCLK GND FIGURE 1C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL 8344 www.icst.com 10 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FIGURE 2A, 2B - TIMING WAVEFORMS CLK VPP nCLK tPHL tPLH Q VDDO/2 FIGURE 2A - PROPAGATION DELAYS fin = 167MHz, Vpp = 300mV, tr = tf = 200ps OEx 3.3V OEx 0V tPHZ Q tPZH VOH VOH - 300mV VDDO/2 tPLZ tPZL VDDO/2 VOL + 300mV Q VOL FIGURE 2B - DISABLE AND ENABLE TIMES fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps 8344 www.icst.com 11 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK VPP nCLK ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ VDDO/2 tsk(b) ○ ○ VDDO/2 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Q0, Q8, Q16 tsk(b) Q7, Q15, Q23 VDDO/2 VDDO/2 FIGURE 3A - BANK SKEW fin = 167MHz, Vpp = 300mV, tr = tf = 200ps Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK VPP nCLK Q0 - Q7 VDDO/2 VDDO/2 tsk(o) tsk(o) Q8 - Q15 Q16 - Q23 VDDO/2 VDDO/2 FIGURE 3B - OUTPUT SKEW fin = 167MHz, Vpp = 300mV, tr = tf = 200ps 8344 www.icst.com 12 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER FIGURE 4A - SKEW DEFINITIONS & WAVEFORMS Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK VPP nCLK PART 1 Q0 - Q7 Q8 - Q15 Q16 - Q23 VDDO/2 VDDO/2 tsk(p) PART 2 tsk(p) Q0 - Q7 Q8 - Q15 Q16 - Q23 VDDO/2 VDDO/2 FIGURE 4B - OUTPUT SKEW fin = 167MHz, Vpp = 300mV, tr = tf = 200ps 8344 www.icst.com 13 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX D D2 θ 52 1 2 3 E 40 39 L E1 E2 N 13 14 27 26 e A D1 A2 -Cccc C b A1 SEATING PLANE c TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BCC SYMBOL MINIMUM NOMINAL MAXIMUM 48 N 1.60 A A1 0.05 A2 1.35 1.40 0.15 1.45 b 0.17 0.22 0.27 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 E 9.00 BASIC E1 7.00 BASIC E2 5.50 0.5 BASIC e L 0.45 q 0° 0.60 0.75 7° 0.08 ccc Reference Document: JEDEC Publication 95, MS-026 8344 www.icst.com 14 REV. B FEBRUARY 2, 2001 PRELIMINARY ICS8344 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8344BY ICS8344BYT ICS8344BY 48 Lead LQFP 250 per tray 0°C to 70°C ICS8344BY 48 Lead LQFP on Tape and Reel 2000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344 www.icst.com 15 REV. B FEBRUARY 2, 2001