PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843031 is a 1 Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS843031 can synthesize 1 Gigabit Ethernet, SONET, or Serial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The ICS843031 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 18pF parallel resonant crystals • VCO frequency range: 580MHz - 700MHz • RMS phase jitter @312.5MHz (1.875MHz - 20MHz): 0.5ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request FREQUENCY TABLE Inputs M/N Ratio (Multiplier) Output Frequency (MHz) 25.92 12 311.04 26.04166 12 312.5 26.5625 12 318.75 Crystal Frequency (MHz) BLOCK DIAGRAM PIN ASSIGNMENT OE XTAL_IN OSC XTAL-OUT Phase Detector VCO ÷2 nQ0 Q0 VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q0 nQ0 VCC OE ICS843031 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ÷24 (fixed) The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843031AG www.icst.com/products/hiperclocks.html REV. A NOVEMBER 29, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 Power 4 VCC XTAL_OUT, XTAL_IN V EE 5 OE Input 7, 8 nQ0, Q0 Output 2, 3 Type Description Core supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Input Power Pullup Output enable pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characterristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ 843031AG Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Test Conditions VCC Core Supply Voltage I EE Power Supply Current Minimum Typical Maximum 3.135 3.3 3.465 65 Units V mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage OE Test Conditions 2 VCC + 0.3 V VIL Input Low Voltage OE -0.3 0.8 V IIH Input High Current OE VCC = VIN = 3.465V IIL Input Low Current OE VCC = 3.465V, VIN = 0V Minimum Typical 5 -150 µA µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency 12 50 Ω Shunt Capacitance 7 pF TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions Integration Range: 1.875MHz to 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. 843031AG www.icst.com/products/hiperclocks.html 3 Minimum Typical Maximum Units 312.5 MHz 0.5 ps 550 ps 50 % REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 312.5MHZ ➤ 0 -10 -20 1 Gigabit Ethernet Filter -30 -40 -50 312.5MHz -60 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.50ps (typical) -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -70 -110 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 1 Gigabit Ethernet Filter to raw data -180 -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843031AG www.icst.com/products/hiperclocks.html 4 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power V CC LVPECL nQx VEE Offset Frequency f1 f2 -1.3V ± 0.165V RMS Jitter = Area Under Offset Frequency Markers 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0 80% Q0 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843031AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843031 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 26.04167MHz, 18pF XTAL_OUT C1 12p X1 18pF Parallel Cry stal XTAL_IN C2 12p Figure 1. CRYSTAL INPUt INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines.Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 843031AG 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843031. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843031 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 65mA = 225.2mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 225.2mW + 30mW = 255.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.255W * 90.5°C/W = 93.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843031AG 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843031AG www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843031 is: 2360 843031AG www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843031AG www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 29, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS843031 FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS843031AG 3031A 8 lead TSSOP 100 per tube 0°C to 70°C ICS843031AGT 3031A 8 lead TSSOP on Tape and Reel 2500 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843031AG www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 29, 2004