ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843023I is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS843023I uses a 25MHz crystal to synthesize 250MHz. The ICS843023I has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS843023I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal • Output frequency range: 245MHz - 320MHz • VCO range: 490MHz - 640MHz • RMS phase jitter @ 250MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.39ps (typical) Phase noise: Offset Noise Power 100Hz ............... -86.3 dBc/Hz 1kHz .............. -114.6 dBc/Hz 10kHz .............. -125.6 dBc/Hz 100kHz ................ -126 dBc/Hz • 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT OE 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO Q ÷2 (fixed) nQ VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q nQ VCC OE ICS843023I ÷20 (fixed) 843023AGI 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 Power Core supply pin. Input Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4 VCC XTAL_OUT, XTAL_IN VEE Power 5 OE Input 7, 8 nQ, Q Output Negative supply pin. Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and the device is in power down mode. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. 2, 3 Type Description Pullup Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ 843023AGI Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 75 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2. 5 2.625 V VCCA Analog Supply Voltage 2.375 2. 5 2.625 V IEE Power Supply Current 70 mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum Maximum Units VCC = 3.3V 2 Typical VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 5 µA VIL Input Low Voltage IIH Input High Current OE VCC = VIN = 3.465V or 2.625V IIL Input Low Current OE VCC = 3.465V or 2.625V, VIN = 0V -150 µA TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 843023AGI www.icst.com/products/hiperclocks.html 3 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Maximum Units 32 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Typical Fundamental Frequency 24.5 TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions Minimum Typical 245 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot after this section. Maximum Units 320 MHz 0.39 ps 300 600 ps 47 53 % Maximum Units 320 MHz TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions Typical 245 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot after this section. 843023AGI Minimum www.icst.com/products/hiperclocks.html 4 0.39 ps 300 600 ps 47 53 % REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 250MHZ (3.3V) ➤ 0 -10 -20 Gigabit Ethernet Filter -40 250MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -30 -110 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding Gigabit Ethernet Filter to raw data -190 100 1k 10k 100k 1M 10M 100M 500M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 250MHZ (2.5V) 0 ➤ -10 -20 Gigabit Ethernet Filter -30 -40 250MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -50 -110 -120 -130 -140 -150 -160 ➤ -170 -180 -190 100 1k 10k Phase Noise Result by adding Gigabit Ethernet Filter to raw data 100k 1M 10M 100M 500M OFFSET FREQUENCY (HZ) 843023AGI www.icst.com/products/hiperclocks.html 5 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V 2V V CC Qx SCOPE VCC LVPECL Qx SCOPE LVPECL nQx nQx VEE VEE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT Noise Power Phase Noise Plot 80% 80% VSW I N G Clock Outputs Phase Noise Mask f1 Offset Frequency 20% 20% tR tF f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQ Q t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843023AGI www.icst.com/products/hiperclocks.html 6 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR APPLICATION INFORMATION CRYSTAL INPUT INTERFACE The ICS843023I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 1. CRYSTAL INPUt INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 843023AGI 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. TERMINATION FOR FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 843023AGI www.icst.com/products/hiperclocks.html 8 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843023I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843023I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA= 259.87mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 259.87mW + 30mW = 289.87mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.290W * 90.5°C/W = 111.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843023AGI 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 9 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (V CCO_MAX • -V OH_MAX ) = 0.9V For logic low, VOUT = V OL_MAX (V CCO_MAX -V OL_MAX =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843023AGI www.icst.com/products/hiperclocks.html 10 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843023I is: 2360 843023AGI www.icst.com/products/hiperclocks.html 11 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843023AGI www.icst.com/products/hiperclocks.html 12 REV. A JUNE 29, 2005 ICS843023I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843023AGI 023AI 8 Lead TSSOP tube -40°C to 85°C ICS843023AGIT 023AI 8 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS843023AGILF TB D 8 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843023AGILFT TBD 8 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843023AGI www.icst.com/products/hiperclocks.html 13 REV. A JUNE 29, 2005