ICS ICS843252AGLFT

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843252 is a 2 differential output LVPECL
Synthesizer designed to generate Ethernet referHiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency
select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz.
• Two 3.3V differential LVPECL output pairs
ICS
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Crystal oscillator interface
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.47ps (typical)
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies
mentioned above. The ICS843252 ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS843252 is packaged in a small
16-pin TSSOP package.
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
SELA[0:1} Pullup
PIN ASSIGNMENT
2
XTAL_IN
XTAL_OUT
Phase
Detector
OSC
VCO
490MHz - 680MHz
Feedback Divider
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷1
÷2
÷3
÷4 (default)
00
01
10
11
÷2
÷4
÷5
÷8 (default)
nQA
QB
nQB
nQB
QB
VCCO _B
SELB1
SELB0
VCCO _A
QA
nQA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
V EE
SELA1
SELA0
VCC
V CCA
FB_SEL
ICS843252
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
FB_SEL Pulldown
SELB[0:1} Pullup
QA
2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843252AG
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REV. A NOVEMBER 9, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Νυ μ β ε ρ
Ναμ ε
Τψπ ε
1, 2
nQB, QB
Output
Differential clock outputs. LVPECL interface levels.
3
4,
5
6
VCCO_B
SELB1,
SELB0
VCCO_A
Power
Output supply pin for QB, nQB outputs.
Division select pins for Bank B. Default = High.
LVCMOS/LVTTL interface levels.
Output supply pin for QA output.
7, 8
QA, nQA
Output
9
FB_SEL
Input
10
VCCA
Power
Input
Δ ε σχριπ τιο ν
Pullup
Power
Pulldown
Differential clock outputs. LVPECL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Power
Core supply pin.
VCC
SELA0,
Division select pins for Bank A. Default = HIGH.
Input
Pullup
SELA1
LVCMOS/LVTTL interface levels.
Power
Negative supply pin.
VEE
XTAL_OUT,
Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
15, 16
Input
XTAL_IN
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
11
12,
13
14
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 3A. BANK A FREQUENCY TABLE
Inputs
Bank A
Output Divider
M/N
Multiplication
Factor
25
QA/nQA
Output
Frequency
(MHz)
625
Crystal Frequency
(MHz)
FB_SEL
SELA1
SELA0
Feedback
Divider
25
0
0
0
25
1
843252AG
25
0
0
1
25
2
12.5
312.5
20
0
0
1
25
2
12.500
250
22.5
0
1
0
25
3
8.333
187.5
25
0
1
1
25
4
6.25
156.25
24
0
1
1
25
4
6.25
150
20
0
1
1
25
4
6.25
125
19.44
1
0
0
32
1
32
622.08
19.44
1
0
1
32
2
16
311.04
15.625
1
0
1
32
2
16
250
18.75
1
1
0
32
3
10.667
200
19.44
1
1
1
32
4
8
155.52
18.75
1
1
1
32
4
8
150
15.625
1
1
1
32
4
8
125
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3
REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 3B. BANK B FREQUENCY TABLE
25
0
0
0
25
2
12.5
QB/nQB
Output
Frequency
(MHz)
312.5
20
0
0
0
25
2
12.5
250
Inputs
Crystal Frequency
(MHz)
FB_SEL
SELB1
SELB0
Feedback
Divider
Bank B
Output Divider
M/N
Multiplication
Factor
25
0
0
1
25
4
6.25
156.25
24
0
0
1
25
4
6.25
150
20
0
0
1
25
4
6.25
125
25
0
1
0
25
5
5
125
25
0
1
1
25
8
3.125
78.125
24
0
1
1
25
8
3.125
75
20
0
1
1
25
8
3.125
62.5
19.44
1
0
0
32
2
16
311.04
15.625
1
0
0
32
2
16
250
19.44
1
0
1
32
4
8
155.52
18.75
1
0
1
32
4
8
150
15.625
1
0
1
32
4
8
125
15.625
1
1
0
32
5
6.4
100
19.44
1
1
1
32
8
4
77.76
18.75
1
1
1
32
8
4
75
15.625
1
1
1
32
8
4
62.5
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLES
Inputs
Inputs
Outputs
Outputs
SELA1
SELA0
QA
SELB1
SELB0
QB
0
0
÷1
0
0
÷2
0
1
÷2
0
1
÷4
1
0
÷3
1
0
÷5
1
1
÷4 (default)
1
1
÷8 (default)
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs
FB_SEL
Feedback Divide
0
÷25 (default)
1
÷32
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO_A, VCCO_B
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
122
mA
ICCA
Analog Supply Current
7
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VIH
Input High Voltage
Test Conditions
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
Input
High Current
VCC = VIN = 3.465V
150
µA
IIH
VCC = VIN = 3.465V
5
µA
IIL
Input
Low Current
FB_SEL
SELA0, SELA1,
SELB0, SELB1
FB_SEL
SELA0, SELA1,
SELB0, SELB1
Minimum
Typical
VCC = 3.465V, VIN = 0V
-5
µA
VCC = 3.465V, VIN = 0V
-150
µA
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_B - 2V.
843252AG
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5
REV. A NOVEMBER 9, 2005
PRELIMINARY
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
FB_SEL = ÷25
19.6
27.2
MHz
FB_SEL = ÷32
15.313
21.25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
680
MHz
Frequency
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fOUT
t sk(o)
t jit(Ø)
t R / tF
Parameter
Output Frequency Range
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Test Conditions
Minimum
Output Divider = ÷1
490
Typical
Output Divider = ÷2
245
340
MHz
Output Divider = ÷3
163.33
226.67
MHz
Output Divider = ÷4
122.5
170
MHz
Output Divider = ÷5
98
136
MH z
Output Divider = ÷8
61.25
85
MHz
Outputs @ Same Frequency
TBD
ps
Outputs @ Different Frequencies
TBD
ps
625MHz (1.875MHz - 20MHz)
0.36
ps
312.5MHz (1.875MHz - 20MHz)
0.43
ps
156.25MHz (1.875MHz - 20MHz)
0.47
ps
125MHz (1.875MHz - 20MHz)
0.47
ps
20% to 80%
35 0
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843252AG
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6
%
REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
156.25MHZ
➤
0
10Gb Ethernet Filter
156.25MHz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.47ps (typical)
Raw Phase Noise Data
➤
➤
NOISE POWER
dBc
Hz
-10
-20
-30
-40
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843252AG
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7
REV. A NOVEMBER 9, 2005
PRELIMINARY
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
Qx
VCC ,
VCCA, VCCO_A. _B
nQx
SCOPE
Qx
nQy
LVPECL
Qy
nQx
VEE
tsk(o)
-1.3V±0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Noise Power
Phase Noise Plot
Phase Noise Mask
80%
80%
VSW I N G
f1
Offset Frequency
Clock
Outputs
f2
20%
20%
tR
tF
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQA, nQB
QA, QB
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
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ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843252 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10 Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 19.53125 or 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS843252 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
843252AG
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REV. A NOVEMBER 9, 2005
PRELIMINARY
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION
FOR
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
843252AG
125Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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10
REV. A NOVEMBER 9, 2005
PRELIMINARY
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Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843252.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843252 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 122mA = 422.73mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 422.73mW + 60mW = 482.73mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.483W * 81.8°C/W = 109.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843252AG
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REV. A NOVEMBER 9, 2005
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ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V _MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843252AG
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ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843252 is: 3822
843252AG
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843252AG
www.icst.com/products/hiperclocks.html
14
REV. A NOVEMBER 9, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843252
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS843252AG
843252AG
16 Lead TSSOP
tube
0°C to 70°C
ICS843252AGT
843252AG
16 Lead TSSOP
2500 tape & reel
0°C to 70°C
ICS843252AGLF
TBD
16 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS843252AGLFT
TB D
16 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
843252AG
www.icst.com/products/hiperclocks.html
15
REV. A NOVEMBER 9, 2005