PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockS™ lay Buffer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The device is designed only for 1:1 input/output frequency ratios. The output divider allows a wide input/output frequency range with the 250MHz to 500MHz VCO. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be doubled by utilizing the ability of the outputs to drive two series terminated lines. The differential reference clock input will accept any differential signal levels. • Fully integrated PLL BLOCK DIAGRAM PIN ASSIGNMENT • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 36ps (typical) • Output skew: 125ps (maximum) • Static Phase Offset: TBD±100ps (typical) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature FB_IN GND Q6 Q6 Q5 VDDO 1 Q4 Q7 PLL Q3 GND CLK ÷2 ÷4 ÷8 ÷16 Q8 Q2 0 nCLK 32 31 30 29 28 27 26 25 Q1 SEL1 VDDO PLL_SEL Q0 SEL0 VDDA 1 24 VDDO VDD 2 23 Q5 CLK 3 22 GND nCLK 4 21 Q4 GND 5 20 VDDO DIV_SEL0 6 19 Q3 DIV_SEL1 7 18 GND GND 8 17 MR/nOE Q7 ICS8602 9 10 11 12 13 14 15 16 Q8 GND Q2 VDDO Q1 GND Q0 VDDO FB_IN PLL_SEL MR/nOE 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8602BY www.icst.com/products/hiperclocks.html 1 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type Analog supply pin. 2 VDD Power Core supply pin. 3 CLK Input 4 nCLK Input 5, 8, 12 16, 18, 22, 25, 29 GND Power 6, 7 DIV_SEL0, DIV_SEL1 Input 9 FB_IN Input 10, 14, 20, 24, 27, 31 11, 13, 15, 19, 21, 23, 26, 28, 30 VDDO Power Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 Output 17 MR/nOE Input 32 PLL_SEL Input Description Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Feedback input to phase detector for regenerating clocks Pulldown with "zero delay". LVCMOS / LVTTL interface levels. Pulldown Output supply pins. Clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and Pulldown the outputs are tri-stated (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. Pullup When LOW, selects reference clock. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 KΩ TBD pF 7 Ω CPD ROUT 4 VDD, VDDA, VDDO = 3.47V TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0 PLL BYPASS MODE TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1 DIV_SEL1 8602BY DIV_SEL0 pF fOUT = fIN Frequency Range (MHz) Minimum Maximum Frequency Divider DIV_SEL1 DIV_SEL0 fIN fOUT 0 fIN fIN/2 0 0 125 250 0 0 1 62.5 125 0 1 fIN fIN/4 0 fIN fIN/8 1 fIN fIN/16 1 0 31.25 62.5 1 1 1 15.625 31.25 1 www.icst.com/products/hiperclocks.html 2 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.1°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDO Output Supply Voltage IDD Power Supply Current 40 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 160 mA V TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH Input High Current Input Low Current Test Conditions DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA 2.6 V Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit. TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units CLK VDD = VIN = 3.465V Test Conditions 150 µA nCLK VDD = VIN = 3.465V 5 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical CLK VDD = 3.465, VIN = 0V -5 µA nCLK VDD = 3.465, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum voltage for CLK, nCLK is VDD + 0.3V. 8602BY www.icst.com/products/hiperclocks.html 3 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low-to-High; NOTE 1 tpLH Test Conditions PLL_SEL=0V, 0MHz ≤ f ≤ 250MHz tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 3.3V, fREF = 133MHz, fVCO = 266MHz PLL_SEL = 3.3V, fREF = 50MHz, fVCO = 100MHz Measured on rising edge at VDDO/2 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4 Measured on rising edge at VDDO/2 tL PLL Lock Time tR Output Rise Time 20% to 80% @ 50MHz tF Output Fall Time 20% to 80% @ 50MHz t(Ø) Static Phase Offset; NOTE 2 Minimum Maximum Units 15.625 Typical 250 MHz TBD TBD ns TBD±100 ps TBD±100 ps 125 36 ps ps 1 ms 400 950 ps 400 950 ps odc Output Duty Cycle f = 250MHz 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % 8602BY www.icst.com/products/hiperclocks.html 4 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION VDD, VDDA, VDDO = 1.65V±5% VDD SCOPE nCLK V Qx LVCMOS V Cross Points PP CMR CLK GND GND = -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT V V DDO Q0:Q8 DIFFERENTIAL INPUT LEVEL Qx 2 tcycle n+1 ➤ ➤ n DDO DDO 2 ➤ tcycle V V DDO 2 2 ➤ V DDO Qy t jit(cc) = tcycle n –tcycle n+1 2 tsk(o) 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT SKEW V DDO 2 Q0:Q8 80% 80% Pulse Width t 20% 20% PERIOD Clock Outputs t t PW odc = t PERIOD odc & tPERIOD nCLK CLK CLK VDD 2 Q0:Q8 ➤ ➤ t(Ø) t F OUTPUT RISE/FALL TIME nCLK FB_IN R VDDO 2 t PD t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) STATIC PHASE OFFSET 8602BY PROPAGATION DELAY www.icst.com/products/hiperclocks.html 5 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8602 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 8602BY 3.3V VDD .01µF 10Ω V DDA .01µF 10 µF FIGURE 2. POWER SUPPLY FILTERING www.icst.com/products/hiperclocks.html 6 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 8602BY nCLK Zo = 50 Ohm FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY www.icst.com/products/hiperclocks.html 7 BY REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8602 is: 1828 8602BY www.icst.com/products/hiperclocks.html 8 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8602BY www.icst.com/products/hiperclocks.html 9 REV. F APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8602BY ICS8602BY 32 Lead LQFP 250 per tray 0°C to 70°C ICS8602BYT ICS8602BY 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8602BY www.icst.com/products/hiperclocks.html 10 REV. F APRIL 16, 2003